From: "Richard Genoud (TI)" <richard.genoud@bootlin.com>
To: Tom Rini <trini@konsulko.com>,
Manorit Chawdhry <m-chawdhry@ti.com>,
Apurva Nandan <a-nandan@ti.com>, "Andrew F . Davis" <afd@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>, Bryan Brattlof <bb@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
Jayesh Choudhary <j-choudhary@ti.com>,
Simon Glass <sjg@chromium.org>,
Alper Nebi Yasak <alpernebiyasak@gmail.com>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>,
Kendall Willis <k-willis@ti.com>, Udit Kumar <u-kumar1@ti.com>,
Abhash Kumar <a-kumar2@ti.com>,
Thomas Richard <thomas.richard@bootlin.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Richard Genoud <richard.genoud@bootlin.com>,
u-boot@lists.u-boot-project.org
Subject: [PATCH v5 11/21] board: mach-k3: r5: common: Set PMIC NSLEEP triggers bits at resume
Date: Fri, 28 Aug 2026 15:57:20 +0200 [thread overview]
Message-ID: <20260828135730.1565643-12-richard.genoud@bootlin.com> (raw)
In-Reply-To: <20260828135730.1565643-1-richard.genoud@bootlin.com>
If we are resuming NSLEEP triggers bits of PMIC-A and PMIC-B shall be set
to prevent transition to S2R state while clearing interrupts.
For example PMIC RTC Linux driver accesses to interrupt registers, in this
case if NSLEEP triggers bits are not set it triggers a S2R transition.
Suggested-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
Signed-off-by: Richard Genoud (TI) <richard.genoud@bootlin.com>
---
arch/arm/mach-k3/r5/lpm-common.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/mach-k3/r5/lpm-common.c b/arch/arm/mach-k3/r5/lpm-common.c
index 0e5feae6d12d..4b67b9417c29 100644
--- a/arch/arm/mach-k3/r5/lpm-common.c
+++ b/arch/arm/mach-k3/r5/lpm-common.c
@@ -29,6 +29,9 @@
/* PMIC register where the magic value resides */
#define K3_LPM_SCRATCH_PAD_REG_3 0xcb
+/* PMIC NSLEEP register */
+#define K3_LPM_NSLEEP_TRIGGER_REG 0x86
+
/* Wake-up source IDs */
#define K3_LPM_WAKE_SOURCE_MAIN_IO 0x80
#define K3_LPM_WAKE_SOURCE_MCU_IO 0x81
@@ -161,6 +164,30 @@ bool j7xx_board_is_resuming(void)
if (ret)
printf("Failed to clean magic value for suspend detection in PMIC\n");
+
+ /*
+ * Ensure that NSLEEP triggers bits are set to prevent a
+ * suspend/resume transition when accessing PMIC interrupt
+ * registers.
+ */
+ if (IS_ENABLED(CONFIG_SOC_K3_J722S)) {
+ ret = dm_i2c_reg_write(pmic, K3_LPM_NSLEEP_TRIGGER_REG, 0x3);
+ } else {
+ struct udevice *pmic_b;
+
+ /* Some boards may have more than one pmic */
+ ret = uclass_get_device_by_name(UCLASS_PMIC, "pmic@4c", &pmic_b);
+ if (ret == 0) {
+ ret = pmic_reg_write(pmic_b, K3_LPM_NSLEEP_TRIGGER_REG, 0x03);
+ if (ret)
+ printf("Failed to set NSLEEP triggers bits on PMIC-B\n");
+ }
+
+ ret = pmic_reg_write(pmic, K3_LPM_NSLEEP_TRIGGER_REG, 0x3);
+ }
+ if (ret)
+ printf("Failed to set PMIC NSLEEP triggers. Spurious suspend/resume may happen.\n");
+
/*
* For robustness, the DM should also clean the magic value at
* startup.
next prev parent reply other threads:[~2026-08-28 13:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 13:57 [PATCH v5 00/21] Introduce resume for J7xx SoCs Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 01/21] ram: k3-ddrss: Add support for DDR in self-refresh Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 02/21] firmware: ti_sci: Add TI_SCI_MSG_MIN_CONTEXT_RESTORE Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 03/21] firmware: ti_sci: add low power mode operations Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 04/21] mach-k3: r5: common: add helper functions needed in LPM resume sequence Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 05/21] global: k3: use gd to store the resume state Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 06/21] mach-k3: r5: common: introduce j7xx_board_is_resuming() Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 07/21] mach-k3: r5: common: introduce k3_deassert_ddr_ret() Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 08/21] board: mach-k3: r5: common: enable GTC after core_resume Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 09/21] board: evm: Enable de-isolation of IOs at resume for j7200 and j784s4 Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 10/21] board: mach-k3: r5: common: Store wakeup reason on scratchpad memory Richard Genoud (TI)
2026-08-28 13:57 ` Richard Genoud (TI) [this message]
2026-08-28 13:57 ` [PATCH v5 12/21] ram: k3-ddrss: Add exit retention support Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 13/21] ram: k3-ddrss: Add j722s DDR resume sequence Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 14/21] ram: k3-ddrss: support j784s4/j721e/j721s2 DDR resume Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 15/21] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 16/21] arm: mach-k3: j784s4: Enable LPM resume flow for J784s4/J742s2 SOCs Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 17/21] arm: mach-k3: j722s: Enable LPM resume flow Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 18/21] arm: mach-k3: j721s2: " Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 19/21] arm: mach-k3: Update pm-boardcfg for all k3 platforms Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 20/21] arm: dts: k3-j7200: Remove background firewall on DDR Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 21/21] arm: dts: k3-j7200: Extend firewall for ATF region to TIFS Richard Genoud (TI)
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