From: "Richard Genoud (TI)" <richard.genoud@bootlin.com>
To: Tom Rini <trini@konsulko.com>,
Manorit Chawdhry <m-chawdhry@ti.com>,
Apurva Nandan <a-nandan@ti.com>, "Andrew F . Davis" <afd@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>, Bryan Brattlof <bb@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
Jayesh Choudhary <j-choudhary@ti.com>,
Simon Glass <sjg@chromium.org>,
Alper Nebi Yasak <alpernebiyasak@gmail.com>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>,
Kendall Willis <k-willis@ti.com>, Udit Kumar <u-kumar1@ti.com>,
Abhash Kumar <a-kumar2@ti.com>,
Thomas Richard <thomas.richard@bootlin.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Richard Genoud <richard.genoud@bootlin.com>,
u-boot@lists.u-boot-project.org
Subject: [PATCH v5 07/21] mach-k3: r5: common: introduce k3_deassert_ddr_ret()
Date: Fri, 28 Aug 2026 15:57:16 +0200 [thread overview]
Message-ID: <20260828135730.1565643-8-richard.genoud@bootlin.com> (raw)
In-Reply-To: <20260828135730.1565643-1-richard.genoud@bootlin.com>
Deasserting DDR retention pin is quite similar from J7200, J784s4,
J721e, and j721s2 SoCs.
Instead of duplicating almost the same code, add it in lpm-common.c.
NB: On J7200, there's a latch, so the clock needs to be toggled.
Signed-off-by: Richard Genoud (TI) <richard.genoud@bootlin.com>
---
arch/arm/mach-k3/lpm-common.h | 2 ++
arch/arm/mach-k3/r5/lpm-common.c | 27 +++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/arm/mach-k3/lpm-common.h b/arch/arm/mach-k3/lpm-common.h
index 83e0fdcca6ca..7dbe72ce129e 100644
--- a/arch/arm/mach-k3/lpm-common.h
+++ b/arch/arm/mach-k3/lpm-common.h
@@ -11,6 +11,8 @@
void __noreturn do_resume(void);
void lpm_process(void);
+void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val,
+ unsigned int ddr_ret_clk, bool toggle);
void k3_set_lpm_core_bus_node_path(const char *node_path);
void k3_set_lpm_core_compatible(const char *compatible);
diff --git a/arch/arm/mach-k3/r5/lpm-common.c b/arch/arm/mach-k3/r5/lpm-common.c
index c1a8c8e940de..ab39ea0cd67d 100644
--- a/arch/arm/mach-k3/r5/lpm-common.c
+++ b/arch/arm/mach-k3/r5/lpm-common.c
@@ -41,6 +41,33 @@ struct lpm_addr_info {
/* This is used by J722s */
__weak void ctrl_mmr_unlock(void) { }
+#define GPIO_OUT_1 0x3D
+void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val,
+ unsigned int ddr_ret_clk, bool toggle)
+{
+ struct udevice *pmic;
+ int regval;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_PMIC, pmic_name, &pmic);
+ if (err) {
+ printf("Getting %s init failed: %d\n", pmic_name, err);
+ return;
+ }
+
+ /* Set DDR_RET Signal Low on PMIC */
+ regval = pmic_reg_read(pmic, GPIO_OUT_1) & ~ddr_ret_val;
+ pmic_reg_write(pmic, GPIO_OUT_1, regval);
+
+ if (toggle) {
+ /* Now toggle the CLK of the latch for DDR retention */
+ pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk);
+ pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk);
+ pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk);
+ pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk);
+ }
+}
+
/* in board_init_f(), there's no BSS, so we can't use global/static variables */
bool j7xx_board_is_resuming(void)
{
next prev parent reply other threads:[~2026-08-28 13:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 13:57 [PATCH v5 00/21] Introduce resume for J7xx SoCs Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 01/21] ram: k3-ddrss: Add support for DDR in self-refresh Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 02/21] firmware: ti_sci: Add TI_SCI_MSG_MIN_CONTEXT_RESTORE Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 03/21] firmware: ti_sci: add low power mode operations Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 04/21] mach-k3: r5: common: add helper functions needed in LPM resume sequence Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 05/21] global: k3: use gd to store the resume state Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 06/21] mach-k3: r5: common: introduce j7xx_board_is_resuming() Richard Genoud (TI)
2026-08-28 13:57 ` Richard Genoud (TI) [this message]
2026-08-28 13:57 ` [PATCH v5 08/21] board: mach-k3: r5: common: enable GTC after core_resume Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 09/21] board: evm: Enable de-isolation of IOs at resume for j7200 and j784s4 Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 10/21] board: mach-k3: r5: common: Store wakeup reason on scratchpad memory Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 11/21] board: mach-k3: r5: common: Set PMIC NSLEEP triggers bits at resume Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 12/21] ram: k3-ddrss: Add exit retention support Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 13/21] ram: k3-ddrss: Add j722s DDR resume sequence Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 14/21] ram: k3-ddrss: support j784s4/j721e/j721s2 DDR resume Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 15/21] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 16/21] arm: mach-k3: j784s4: Enable LPM resume flow for J784s4/J742s2 SOCs Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 17/21] arm: mach-k3: j722s: Enable LPM resume flow Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 18/21] arm: mach-k3: j721s2: " Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 19/21] arm: mach-k3: Update pm-boardcfg for all k3 platforms Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 20/21] arm: dts: k3-j7200: Remove background firewall on DDR Richard Genoud (TI)
2026-08-28 13:57 ` [PATCH v5 21/21] arm: dts: k3-j7200: Extend firewall for ATF region to TIFS Richard Genoud (TI)
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