From: sashiko-bot@kernel.org
To: "Michal Wilczynski" <m.wilczynski@samsung.com>
Cc: mfd@lists.linux.dev, lee@kernel.org, vkoul@kernel.org,
neil.armstrong@linaro.org, devicetree@vger.kernel.org,
conor+dt@kernel.org, olteanv@gmail.com, robh@kernel.org,
dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 11/15] phy: Add common Innosilicon HDMI PHY helpers
Date: Fri, 28 Aug 2026 14:00:40 +0000 [thread overview]
Message-ID: <20260828140041.3B9041F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260828-jh7110-clean-send-v2-11-331680c8b9d1@samsung.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [High] Possible use of uninitialized stack memory in `inno_read()` if `regmap_read()` fails.
- [High] Kernel panic from division by zero in clock rate recalculation if PHY registers are uninitialized.
--
commit 5b3daa1c79370030c365a1cbd710f38d30ab2630
Author: Michal Wilczynski <m.wilczynski@samsung.com>
phy: Add common Innosilicon HDMI PHY helpers
The Innosilicon HDMI PHY IP is used by several SoCs. They differ in
where the PHY register block sits in the register space and in which
pixel clocks they support, but the pre-PLL programming sequence and the
layout of its registers are the same.
Add a small library holding that shared part: the pre-PLL configuration
table format, a lookup, clk_ops determine_rate and recalc_rate helpers,
and the pre-PLL register programming. Callers pass a regmap, a register
offset for the PHY block, and their own pixel clock table.
> diff --git a/drivers/phy/phy-inno-hdmi.c b/drivers/phy/phy-inno-hdmi.c
> new file mode 100644
> index 0000000000000..deb2b73a86f5d
> --- /dev/null
> +++ b/drivers/phy/phy-inno-hdmi.c
[ ... ]
> +static u8 inno_read(const struct inno_hdmi_phy_pre_pll *pll, unsigned int reg)
> +{
> + unsigned int val;
> +
> + regmap_read(pll->regmap, inno_reg(pll, reg), &val);
> +
> + return val;
> +}
[Severity: High]
This isn't a bug introduced by this patch, as it was inherited from
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c, but is it possible for
regmap_read() to fail here?
If regmap_read() returns an error code, it leaves the stack variable val
uninitialized, which is then returned to the caller.
Could we check the return value of regmap_read() to avoid leaking
uninitialized memory?
[ ... ]
> +unsigned long
> +inno_hdmi_phy_pre_pll_recalc_rate(const struct inno_hdmi_phy_pre_pll *pll,
> + unsigned long parent_rate)
> +{
> + u8 nd, no_a, no_b, no_d;
> + unsigned long frac;
> + u64 vco;
> + u16 nf;
> +
> + nd = inno_read(pll, INNO_PRE_PLL_DIV_1) & INNO_PRE_PLL_PRE_DIV_MASK;
[ ... ]
> + if (inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PCLK_VCO_DIV_5_MASK) {
> + do_div(vco, nd * 5);
[Severity: High]
This is also a pre-existing issue from the original driver, but if the PHY
registers are uninitialized (containing default 0s) or if inno_read() fails
and returns an uninitialized 0, the nd variable will be 0.
Doesn't passing a 0 divisor to do_div() cause a divide-by-zero exception
leading to a kernel panic?
> + } else {
> + no_a = inno_read(pll, INNO_PCLK_DIV_AB) & INNO_PCLK_DIV_A_MASK;
> + no_b = FIELD_GET(INNO_PCLK_DIV_B_MASK,
> + inno_read(pll, INNO_PCLK_DIV_AB)) + 2;
> + no_d = inno_read(pll, INNO_PCLK_DIV_CD) & INNO_PCLK_DIV_D_MASK;
> +
> + do_div(vco, nd * (no_a == 1 ? no_b : no_a) * no_d * 2);
[Severity: High]
Similarly, if nd, no_a, or no_d evaluate to 0 due to register read failures
or uninitialized hardware, can this do_div() call also trigger a division by
zero panic during boot when the common clock framework calls recalc_rate()?
> + }
> +
> + return DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com?part=11
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Michal Wilczynski" <m.wilczynski@samsung.com>
Cc: mfd@lists.linux.dev, lee@kernel.org, vkoul@kernel.org,
neil.armstrong@linaro.org, devicetree@vger.kernel.org,
conor+dt@kernel.org, olteanv@gmail.com, robh@kernel.org,
dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 11/15] phy: Add common Innosilicon HDMI PHY helpers
Date: Fri, 28 Aug 2026 14:00:40 +0000 [thread overview]
Message-ID: <20260828140041.3B9041F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260828-jh7110-clean-send-v2-11-331680c8b9d1@samsung.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [High] Possible use of uninitialized stack memory in `inno_read()` if `regmap_read()` fails.
- [High] Kernel panic from division by zero in clock rate recalculation if PHY registers are uninitialized.
--
commit 5b3daa1c79370030c365a1cbd710f38d30ab2630
Author: Michal Wilczynski <m.wilczynski@samsung.com>
phy: Add common Innosilicon HDMI PHY helpers
The Innosilicon HDMI PHY IP is used by several SoCs. They differ in
where the PHY register block sits in the register space and in which
pixel clocks they support, but the pre-PLL programming sequence and the
layout of its registers are the same.
Add a small library holding that shared part: the pre-PLL configuration
table format, a lookup, clk_ops determine_rate and recalc_rate helpers,
and the pre-PLL register programming. Callers pass a regmap, a register
offset for the PHY block, and their own pixel clock table.
> diff --git a/drivers/phy/phy-inno-hdmi.c b/drivers/phy/phy-inno-hdmi.c
> new file mode 100644
> index 0000000000000..deb2b73a86f5d
> --- /dev/null
> +++ b/drivers/phy/phy-inno-hdmi.c
[ ... ]
> +static u8 inno_read(const struct inno_hdmi_phy_pre_pll *pll, unsigned int reg)
> +{
> + unsigned int val;
> +
> + regmap_read(pll->regmap, inno_reg(pll, reg), &val);
> +
> + return val;
> +}
[Severity: High]
This isn't a bug introduced by this patch, as it was inherited from
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c, but is it possible for
regmap_read() to fail here?
If regmap_read() returns an error code, it leaves the stack variable val
uninitialized, which is then returned to the caller.
Could we check the return value of regmap_read() to avoid leaking
uninitialized memory?
[ ... ]
> +unsigned long
> +inno_hdmi_phy_pre_pll_recalc_rate(const struct inno_hdmi_phy_pre_pll *pll,
> + unsigned long parent_rate)
> +{
> + u8 nd, no_a, no_b, no_d;
> + unsigned long frac;
> + u64 vco;
> + u16 nf;
> +
> + nd = inno_read(pll, INNO_PRE_PLL_DIV_1) & INNO_PRE_PLL_PRE_DIV_MASK;
[ ... ]
> + if (inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PCLK_VCO_DIV_5_MASK) {
> + do_div(vco, nd * 5);
[Severity: High]
This is also a pre-existing issue from the original driver, but if the PHY
registers are uninitialized (containing default 0s) or if inno_read() fails
and returns an uninitialized 0, the nd variable will be 0.
Doesn't passing a 0 divisor to do_div() cause a divide-by-zero exception
leading to a kernel panic?
> + } else {
> + no_a = inno_read(pll, INNO_PCLK_DIV_AB) & INNO_PCLK_DIV_A_MASK;
> + no_b = FIELD_GET(INNO_PCLK_DIV_B_MASK,
> + inno_read(pll, INNO_PCLK_DIV_AB)) + 2;
> + no_d = inno_read(pll, INNO_PCLK_DIV_CD) & INNO_PCLK_DIV_D_MASK;
> +
> + do_div(vco, nd * (no_a == 1 ? no_b : no_a) * no_d * 2);
[Severity: High]
Similarly, if nd, no_a, or no_d evaluate to 0 due to register read failures
or uninitialized hardware, can this do_div() call also trigger a division by
zero panic during boot when the common clock framework calls recalc_rate()?
> + }
> +
> + return DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com?part=11
next prev parent reply other threads:[~2026-08-28 14:00 UTC|newest]
Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20260828134813eucas1p1bd003a66706ed251017185fc14f13cc9@eucas1p1.samsung.com>
2026-08-28 13:47 ` [PATCH v2 00/15] drm: starfive: jh7110: Enable display subsystem Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` [PATCH v2 01/15] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:54 ` sashiko-bot
2026-08-28 13:54 ` sashiko-bot
2026-08-28 16:43 ` Conor Dooley
2026-08-28 16:43 ` Conor Dooley
2026-08-28 16:43 ` Conor Dooley
2026-08-28 16:43 ` Conor Dooley
2026-08-28 13:47 ` [PATCH v2 02/15] dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:54 ` sashiko-bot
2026-08-28 13:54 ` sashiko-bot
2026-08-28 14:04 ` Icenowy Zheng
2026-08-28 14:04 ` Icenowy Zheng
2026-08-28 14:04 ` Icenowy Zheng
2026-08-28 14:04 ` Icenowy Zheng
2026-08-28 16:47 ` Conor Dooley
2026-08-28 16:47 ` Conor Dooley
2026-08-28 16:47 ` Conor Dooley
2026-08-28 16:47 ` Conor Dooley
2026-08-28 13:47 ` [PATCH v2 03/15] dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:54 ` sashiko-bot
2026-08-28 13:54 ` sashiko-bot
2026-08-28 16:50 ` Conor Dooley
2026-08-28 16:50 ` Conor Dooley
2026-08-28 16:50 ` Conor Dooley
2026-08-28 16:50 ` Conor Dooley
2026-08-28 13:47 ` [PATCH v2 04/15] drm/bridge: inno-hdmi: Split probe out of bind Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:01 ` sashiko-bot
2026-08-28 14:01 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 05/15] drm/bridge: inno-hdmi: Allow the register map to come from a parent Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:54 ` sashiko-bot
2026-08-28 13:54 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 06/15] drm/bridge: inno-hdmi: Add .disable platform operation Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:57 ` sashiko-bot
2026-08-28 13:57 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 07/15] drm/bridge: inno-hdmi: Add .mode_valid " Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:52 ` sashiko-bot
2026-08-28 13:52 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 08/15] soc: starfive: Add jh7110-hdmi-subsystem driver Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:59 ` sashiko-bot
2026-08-28 13:59 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 09/15] clk: starfive: jh7110-vout: Allow pixel clock rate propagation Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:01 ` sashiko-bot
2026-08-28 14:01 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 10/15] drm/bridge: starfive: Add JH7110 HDMI controller driver Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:59 ` sashiko-bot
2026-08-28 13:59 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 11/15] phy: Add common Innosilicon HDMI PHY helpers Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:00 ` sashiko-bot [this message]
2026-08-28 14:00 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 12/15] phy: rockchip: inno-hdmi: Use the common Innosilicon " Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:12 ` sashiko-bot
2026-08-28 14:12 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 13/15] phy: starfive: Add jh7110-inno-hdmi-phy driver Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:04 ` sashiko-bot
2026-08-28 14:04 ` sashiko-bot
2026-08-28 13:47 ` [PATCH v2 14/15] riscv: dts: starfive: jh7110: Update DT for display subsystem Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:06 ` sashiko-bot
2026-08-28 14:06 ` sashiko-bot
2026-08-28 14:06 ` Icenowy Zheng
2026-08-28 14:06 ` Icenowy Zheng
2026-08-28 14:06 ` Icenowy Zheng
2026-08-28 14:06 ` Icenowy Zheng
2026-08-28 13:47 ` [PATCH v2 15/15] MAINTAINERS: Add StarFive JH7110 display subsystem entry Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 13:47 ` Michal Wilczynski
2026-08-28 14:01 ` Icenowy Zheng
2026-08-28 14:01 ` Icenowy Zheng
2026-08-28 14:01 ` Icenowy Zheng
2026-08-28 14:01 ` Icenowy Zheng
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