From: Jiaxing Hu <gahing@gahingwoo.com>
To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org,
will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org,
p.zabel@pengutronix.de, ogabbay@kernel.org,
zhangqing@rock-chips.com
Cc: royalnet026@gmail.com, u.kleine-koenig@baylibre.com,
chaoyi.chen@rock-chips.com, diederik@cknow-tech.com,
alchark@flipper.net, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Jiaxing Hu <gahing@gahingwoo.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v10 07/13] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU
Date: Mon, 31 Aug 2026 16:07:58 +1200 [thread overview]
Message-ID: <20260831040804.24111-8-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260831040804.24111-1-gahing@gahingwoo.com>
The RK3576 NPU MMUs are rk3568-iommu compatible but take five clocks
where every other Rockchip MMU takes two, the extra three being the
compute clock and the two convolution buffer clocks.
Give them a compatible of their own and pin both sides with an allOf, so
that an rk3568-iommu cannot carry five clocks and an NPU MMU cannot
carry two. Describing the extra clocks as belonging to one SoC without
saying so in the schema, which is what a comment on a description does,
leaves both of those spellings valid.
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/iommu/rockchip,iommu.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
index 6ce41d11f..83d7e7c8e 100644
--- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
- rockchip,rk3576-iommu
+ - rockchip,rk3576-npu-iommu
- rockchip,rk3588-iommu
- const: rockchip,rk3568-iommu
@@ -42,14 +43,22 @@ properties:
minItems: 1
clocks:
+ minItems: 2
items:
- description: Core clock
- description: Interface clock
+ - description: Compute clock
+ - description: Convolution buffer core clock
+ - description: Convolution buffer interface clock
clock-names:
+ minItems: 2
items:
- const: aclk
- const: iface
+ - const: npu
+ - const: aclk_cbuf
+ - const: hclk_cbuf
"#iommu-cells":
const: 0
@@ -72,6 +81,25 @@ required:
- clock-names
- "#iommu-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3576-npu-iommu
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ clock-names:
+ minItems: 5
+ else:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Jiaxing Hu <gahing@gahingwoo.com>
To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org,
will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org,
p.zabel@pengutronix.de, ogabbay@kernel.org,
zhangqing@rock-chips.com
Cc: royalnet026@gmail.com, u.kleine-koenig@baylibre.com,
chaoyi.chen@rock-chips.com, diederik@cknow-tech.com,
alchark@flipper.net, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Jiaxing Hu <gahing@gahingwoo.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v10 07/13] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU
Date: Mon, 31 Aug 2026 16:07:58 +1200 [thread overview]
Message-ID: <20260831040804.24111-8-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260831040804.24111-1-gahing@gahingwoo.com>
The RK3576 NPU MMUs are rk3568-iommu compatible but take five clocks
where every other Rockchip MMU takes two, the extra three being the
compute clock and the two convolution buffer clocks.
Give them a compatible of their own and pin both sides with an allOf, so
that an rk3568-iommu cannot carry five clocks and an NPU MMU cannot
carry two. Describing the extra clocks as belonging to one SoC without
saying so in the schema, which is what a comment on a description does,
leaves both of those spellings valid.
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/iommu/rockchip,iommu.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
index 6ce41d11f..83d7e7c8e 100644
--- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
- rockchip,rk3576-iommu
+ - rockchip,rk3576-npu-iommu
- rockchip,rk3588-iommu
- const: rockchip,rk3568-iommu
@@ -42,14 +43,22 @@ properties:
minItems: 1
clocks:
+ minItems: 2
items:
- description: Core clock
- description: Interface clock
+ - description: Compute clock
+ - description: Convolution buffer core clock
+ - description: Convolution buffer interface clock
clock-names:
+ minItems: 2
items:
- const: aclk
- const: iface
+ - const: npu
+ - const: aclk_cbuf
+ - const: hclk_cbuf
"#iommu-cells":
const: 0
@@ -72,6 +81,25 @@ required:
- clock-names
- "#iommu-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3576-npu-iommu
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ clock-names:
+ minItems: 5
+ else:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.43.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2026-08-31 4:09 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-31 4:07 [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 01/13] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 02/13] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 03/13] accel/rocket: let the core suspend after a reset Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 04/13] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 05/13] dt-bindings: npu: rockchip: add rockchip, rk3576-rknn-core Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 05/13] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 06/13] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu [this message]
2026-08-31 4:07 ` [PATCH v10 07/13] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-08-31 4:07 ` [PATCH v10 08/13] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-31 4:07 ` Jiaxing Hu
2026-08-31 4:08 ` [PATCH v10 09/13] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-31 4:08 ` Jiaxing Hu
2026-08-31 4:08 ` [PATCH v10 10/13] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-31 4:08 ` Jiaxing Hu
2026-08-31 4:08 ` [PATCH v10 11/13] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-31 4:08 ` Jiaxing Hu
2026-08-31 4:08 ` [PATCH v10 12/13] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-31 4:08 ` Jiaxing Hu
2026-08-31 4:08 ` [PATCH v10 13/13] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-31 4:08 ` Jiaxing Hu
2026-08-31 7:20 ` [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement Tomeu Vizoso
2026-08-31 7:20 ` Tomeu Vizoso
2026-09-11 12:28 ` Jiaxing Hu
2026-09-11 12:28 ` Jiaxing Hu
2026-09-11 19:28 ` Igor Paunovic
2026-09-11 19:28 ` Igor Paunovic
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