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From: Jiaxing Hu <gahing@gahingwoo.com>
To: royalnet026@gmail.com
Cc: tomeu@tomeuvizoso.net, linux-rockchip@lists.infradead.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement
Date: Sat, 12 Sep 2026 00:28:32 +1200	[thread overview]
Message-ID: <20260911122832.1364839-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260831040804.24111-1-gahing@gahingwoo.com>

Hi Igor,

A correction to what this cover said about your differential run, and to
what I said to you about it on 27 August.

The cover said a job had signalled completion with its output buffer
never written, all 48 channels 0x80, and that across 102 induced resets
in nine runs it appeared only on the arm without 1/13 and 2/13. None of
that is what you reported.

Your table is 12 + 8 + 12 + 13 = 45 resets, two passes per kernel, and
you wrote that the race did not manifest in the 45 on either kernel,
with the oracle 48/48 on both arms. The 0x80 is ours: on RK3576 a fresh
shmem BO is zeroed and teflon's readback adds 0x80, so an output buffer
that was never written reads back as a uniform 128. I carried our own
signature onto your RK3588 run, which never reported it.

The patch text is the part that was right, and it is the only form of
your result I will use: 45 induced resets across three cores, the domain
dropping every time with no MMU message on either kernel, so this is not
rocket-wide. You were careful to say your protocol could not settle
whether a genuinely hung block behaves differently. I turned a bounding
result into a reproduction.

Jiaxing

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Jiaxing Hu <gahing@gahingwoo.com>
To: royalnet026@gmail.com
Cc: tomeu@tomeuvizoso.net, linux-rockchip@lists.infradead.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement
Date: Sat, 12 Sep 2026 00:28:32 +1200	[thread overview]
Message-ID: <20260911122832.1364839-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260831040804.24111-1-gahing@gahingwoo.com>

Hi Igor,

A correction to what this cover said about your differential run, and to
what I said to you about it on 27 August.

The cover said a job had signalled completion with its output buffer
never written, all 48 channels 0x80, and that across 102 induced resets
in nine runs it appeared only on the arm without 1/13 and 2/13. None of
that is what you reported.

Your table is 12 + 8 + 12 + 13 = 45 resets, two passes per kernel, and
you wrote that the race did not manifest in the 45 on either kernel,
with the oracle 48/48 on both arms. The 0x80 is ours: on RK3576 a fresh
shmem BO is zeroed and teflon's readback adds 0x80, so an output buffer
that was never written reads back as a uniform 128. I carried our own
signature onto your RK3588 run, which never reported it.

The patch text is the part that was right, and it is the only form of
your result I will use: 45 induced resets across three cores, the domain
dropping every time with no MMU message on either kernel, so this is not
rocket-wide. You were careful to say your protocol could not settle
whether a genuinely hung block behaves differently. I turned a bounding
result into a reproduction.

Jiaxing

  parent reply	other threads:[~2026-09-11 12:28 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-31  4:07 [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-31  4:07 ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 01/13] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 02/13] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 03/13] accel/rocket: let the core suspend after a reset Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 04/13] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 05/13] dt-bindings: npu: rockchip: add rockchip, rk3576-rknn-core Jiaxing Hu
2026-08-31  4:07   ` [PATCH v10 05/13] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 06/13] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 07/13] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:07 ` [PATCH v10 08/13] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-31  4:07   ` Jiaxing Hu
2026-08-31  4:08 ` [PATCH v10 09/13] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-31  4:08   ` Jiaxing Hu
2026-08-31  4:08 ` [PATCH v10 10/13] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-31  4:08   ` Jiaxing Hu
2026-08-31  4:08 ` [PATCH v10 11/13] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-31  4:08   ` Jiaxing Hu
2026-08-31  4:08 ` [PATCH v10 12/13] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-31  4:08   ` Jiaxing Hu
2026-08-31  4:08 ` [PATCH v10 13/13] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-31  4:08   ` Jiaxing Hu
2026-08-31  7:20 ` [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement Tomeu Vizoso
2026-08-31  7:20   ` Tomeu Vizoso
2026-09-11 12:28 ` Jiaxing Hu [this message]
2026-09-11 12:28   ` Jiaxing Hu
2026-09-11 19:28   ` Igor Paunovic
2026-09-11 19:28     ` Igor Paunovic

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