* [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX
@ 2026-08-31 4:44 ` Aurelien Jarno
0 siblings, 0 replies; 24+ messages in thread
From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw)
To: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Yixun Lan
Cc: Aurelien Jarno, open list:RISC-V ARCHITECTURE:Keyword:riscv,
open list:RISC-V SPACEMIT SoC Support:Keyword:spacemit
This patchset enables Bluetooth through USB on the K3 Pico ITX board and
adds the rfkill nodes for Bluetooth and WLAN so that the devices can be
activated.
Note that WLAN support also require the following patch series, but both
can be applied independently:
- https://lore.kernel.org/spacemit/20260709040027.958400-1-inochiama@gmail.com/
Changes v3 -> v4
- fully move the phy definition and the board level
- rebase on 7.3-rc1
Aurelien Jarno (5):
riscv: dts: spacemit: k3: move USB3 phy to board level
riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX
board
riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX
board
riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX
board
riscv64: defconfig: Enable BT and WLAN support for SpacemiT K3
Pico-ITX board
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++++++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 63 +++++++++++++++++++-
arch/riscv/configs/defconfig | 8 +++
3 files changed, 106 insertions(+), 3 deletions(-)
--
2.53.0
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX @ 2026-08-31 4:44 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan Cc: Aurelien Jarno, open list:RISC-V ARCHITECTURE:Keyword:riscv, open list:RISC-V SPACEMIT SoC Support:Keyword:spacemit This patchset enables Bluetooth through USB on the K3 Pico ITX board and adds the rfkill nodes for Bluetooth and WLAN so that the devices can be activated. Note that WLAN support also require the following patch series, but both can be applied independently: - https://lore.kernel.org/spacemit/20260709040027.958400-1-inochiama@gmail.com/ Changes v3 -> v4 - fully move the phy definition and the board level - rebase on 7.3-rc1 Aurelien Jarno (5): riscv: dts: spacemit: k3: move USB3 phy to board level riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX board riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX board riscv64: defconfig: Enable BT and WLAN support for SpacemiT K3 Pico-ITX board arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 63 +++++++++++++++++++- arch/riscv/configs/defconfig | 8 +++ 3 files changed, 106 insertions(+), 3 deletions(-) -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-31 4:44 ` Aurelien Jarno @ 2026-08-31 4:44 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the SpacemiT K3 SoC, the combo phy provides 8 lines that can either be used for PCIe or USB3, depending on its configuration (spacemit,apmu). This configuration is defined at the board level, and assigning a phy line to a USB3 controller while it is configured as PCIe results in an "Invalid PHY mode" error. Move the USB phy definitions at the board level, as it is done for the submitted PCIe controller [1]. [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ Fixes: 46380e4b1534 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") Cc: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ arch/riscv/boot/dts/spacemit/k3.dtsi | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b084a35aa00e3..0a6f669d509a9 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -328,5 +328,7 @@ &usb3d_u2phy { }; &usb3d { + phys = <&usb3d_u2phy>, <&combophy 4 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index c3f2dce0969c0..6f8d55eae6f6b 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -452,9 +452,6 @@ usb3d: usb@81a00000 { <&syscon_apmu RESET_APMU_USB3_D_VCC>, <&syscon_apmu RESET_APMU_USB3_D_PHY>; reset-names = "ahb", "vcc", "phy"; - phys = <&usb3d_u2phy>, - <&combophy 4 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi"; snps,dis_enblslpm_quirk; snps,dis_u2_susphy_quirk; -- 2.53.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-31 4:44 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the SpacemiT K3 SoC, the combo phy provides 8 lines that can either be used for PCIe or USB3, depending on its configuration (spacemit,apmu). This configuration is defined at the board level, and assigning a phy line to a USB3 controller while it is configured as PCIe results in an "Invalid PHY mode" error. Move the USB phy definitions at the board level, as it is done for the submitted PCIe controller [1]. [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ Fixes: 46380e4b1534 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") Cc: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ arch/riscv/boot/dts/spacemit/k3.dtsi | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b084a35aa00e3..0a6f669d509a9 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -328,5 +328,7 @@ &usb3d_u2phy { }; &usb3d { + phys = <&usb3d_u2phy>, <&combophy 4 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index c3f2dce0969c0..6f8d55eae6f6b 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -452,9 +452,6 @@ usb3d: usb@81a00000 { <&syscon_apmu RESET_APMU_USB3_D_VCC>, <&syscon_apmu RESET_APMU_USB3_D_PHY>; reset-names = "ahb", "vcc", "phy"; - phys = <&usb3d_u2phy>, - <&combophy 4 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi"; snps,dis_enblslpm_quirk; snps,dis_u2_susphy_quirk; -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-31 4:44 ` Aurelien Jarno (?) @ 2026-08-31 4:54 ` sashiko-bot 2026-09-27 21:18 ` Aurelien Jarno -1 siblings, 1 reply; 24+ messages in thread From: sashiko-bot @ 2026-08-31 4:54 UTC (permalink / raw) To: Aurelien Jarno; +Cc: conor+dt, robh, devicetree Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Removing 'phys' and 'phy-names' from the base k3.dtsi breaks DT schema validation (dtbs_check) for disabled nodes and improperly delegates fixed SoC routing to board files. -- commit e9dc7ad92d5f4a805cf362fdd51c6ae160da1934 Author: Aurelien Jarno <aurelien@aurel32.net> riscv: dts: spacemit: k3: move USB3 phy to board level This commit moves the USB3 phy definitions from the SoC dtsi to the board level dts files for the SpacemiT K3 SoC. It aims to prevent PHY mode configuration errors when the combo PHY lines are used for PCIe rather than USB3. [ ... ] > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > index c3f2dce0969c0..6f8d55eae6f6b 100644 > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > @@ -452,9 +452,6 @@ usb3d: usb@81a00000 { > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > reset-names = "ahb", "vcc", "phy"; > - phys = <&usb3d_u2phy>, > - <&combophy 4 PHY_TYPE_USB3>; > - phy-names = "usb2-phy", "usb3-phy"; [Severity: Low] Does removing phys and phy-names from the base k3.dtsi break DT schema validation (dtbs_check) for disabled nodes? To satisfy the schema's minItems: 1 requirement while supporting board-level combo PHY configuration, should the dedicated internal SoC PHY (usb3d_u2phy) have been retained in the base file? The dtbs_check validation will fail for any board DT that includes k3.dtsi but does not override the usb3d node to provide the phys and phy-names properties (e.g., k3-com260-ifx.dts and k3-deepcomputing-fml13v05.dts). This happens because the schema spacemit,k1-dwc3.yaml unconditionally requires these properties, and dt-schema evaluates all nodes, even disabled ones. > phy_type = "utmi"; > snps,dis_enblslpm_quirk; > snps,dis_u2_susphy_quirk; -- Sashiko AI review · https://sashiko.dev/#/patchset/20260831044540.3304350-1-aurelien@aurel32.net?part=1 ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-31 4:54 ` sashiko-bot @ 2026-09-27 21:18 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-09-27 21:18 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support Hi, On 2026-08-31 04:54, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Low] Removing 'phys' and 'phy-names' from the base k3.dtsi breaks DT schema validation (dtbs_check) for disabled nodes and improperly delegates fixed SoC routing to board files. > -- > > commit e9dc7ad92d5f4a805cf362fdd51c6ae160da1934 > Author: Aurelien Jarno <aurelien@aurel32.net> > > riscv: dts: spacemit: k3: move USB3 phy to board level > > This commit moves the USB3 phy definitions from the SoC dtsi to the board > level dts files for the SpacemiT K3 SoC. It aims to prevent PHY mode > configuration errors when the combo PHY lines are used for PCIe rather than > USB3. > > [ ... ] > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > index c3f2dce0969c0..6f8d55eae6f6b 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > @@ -452,9 +452,6 @@ usb3d: usb@81a00000 { > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > reset-names = "ahb", "vcc", "phy"; > > - phys = <&usb3d_u2phy>, > > - <&combophy 4 PHY_TYPE_USB3>; > > - phy-names = "usb2-phy", "usb3-phy"; > > [Severity: Low] > Does removing phys and phy-names from the base k3.dtsi break DT schema > validation (dtbs_check) for disabled nodes? No it doesn't. dtbs_check seems to ignore disabled nodes. > To satisfy the schema's minItems: 1 requirement while supporting board-level > combo PHY configuration, should the dedicated internal SoC PHY (usb3d_u2phy) > have been retained in the base file? > > The dtbs_check validation will fail for any board DT that includes k3.dtsi > but does not override the usb3d node to provide the phys and phy-names > properties (e.g., k3-com260-ifx.dts and k3-deepcomputing-fml13v05.dts). I have just tried, in practice it doesn't. I'll send a new version mentioning that. > This happens because the schema spacemit,k1-dwc3.yaml unconditionally > requires these properties, and dt-schema evaluates all nodes, even disabled > ones. > > > phy_type = "utmi"; > > snps,dis_enblslpm_quirk; > > snps,dis_u2_susphy_quirk; > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260831044540.3304350-1-aurelien@aurel32.net?part=1 > -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-09-27 21:18 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-09-27 21:18 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support Hi, On 2026-08-31 04:54, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Low] Removing 'phys' and 'phy-names' from the base k3.dtsi breaks DT schema validation (dtbs_check) for disabled nodes and improperly delegates fixed SoC routing to board files. > -- > > commit e9dc7ad92d5f4a805cf362fdd51c6ae160da1934 > Author: Aurelien Jarno <aurelien@aurel32.net> > > riscv: dts: spacemit: k3: move USB3 phy to board level > > This commit moves the USB3 phy definitions from the SoC dtsi to the board > level dts files for the SpacemiT K3 SoC. It aims to prevent PHY mode > configuration errors when the combo PHY lines are used for PCIe rather than > USB3. > > [ ... ] > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > index c3f2dce0969c0..6f8d55eae6f6b 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > @@ -452,9 +452,6 @@ usb3d: usb@81a00000 { > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > reset-names = "ahb", "vcc", "phy"; > > - phys = <&usb3d_u2phy>, > > - <&combophy 4 PHY_TYPE_USB3>; > > - phy-names = "usb2-phy", "usb3-phy"; > > [Severity: Low] > Does removing phys and phy-names from the base k3.dtsi break DT schema > validation (dtbs_check) for disabled nodes? No it doesn't. dtbs_check seems to ignore disabled nodes. > To satisfy the schema's minItems: 1 requirement while supporting board-level > combo PHY configuration, should the dedicated internal SoC PHY (usb3d_u2phy) > have been retained in the base file? > > The dtbs_check validation will fail for any board DT that includes k3.dtsi > but does not override the usb3d node to provide the phys and phy-names > properties (e.g., k3-com260-ifx.dts and k3-deepcomputing-fml13v05.dts). I have just tried, in practice it doesn't. I'll send a new version mentioning that. > This happens because the schema spacemit,k1-dwc3.yaml unconditionally > requires these properties, and dt-schema evaluates all nodes, even disabled > ones. > > > phy_type = "utmi"; > > snps,dis_enblslpm_quirk; > > snps,dis_u2_susphy_quirk; > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260831044540.3304350-1-aurelien@aurel32.net?part=1 > -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board 2026-08-31 4:44 ` Aurelien Jarno @ 2026-08-31 4:44 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V ARCHITECTURE, open list:RISC-V SPACEMIT SoC Support The SpacemiT K3 has 4 USB3 controllers labelled A to D. On the K3 Pico-ITX board, the controllers B and C are used in USB2 mode only respectively for the M.2 B-Key slot and for the RTL8852BE Bluetooth controller. Add the two controller nodes. On the K3 Pico-ITX board, enable the controllers nodes and add the two corresponding USB2 PHY nodes. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 22 +++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 60 ++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 0a6f669d509a9..5aa6fa89cab58 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -323,6 +323,28 @@ &usb2_phy { status = "okay"; }; +&usb3b { + phys = <&usb3b_u2phy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb3b_u2phy { + status = "okay"; +}; + +&usb3c { + phys = <&usb3c_u2phy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb3c_u2phy { + status = "okay"; +}; + &usb3d_u2phy { status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 6f8d55eae6f6b..55b00c0f429f7 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -441,6 +441,66 @@ soc: soc { dma-noncoherent; ranges; + usb3b: usb@81400000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81400000 0x0 0x10000>; + interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB3_B_AHB>, + <&syscon_apmu RESET_APMU_USB3_B_VCC>, + <&syscon_apmu RESET_APMU_USB3_B_PHY>; + reset-names = "ahb", "vcc", "phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + usb3b_u2phy: phy@81500000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0x81500000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3c: usb@81700000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81700000 0x0 0x10000>; + interrupts = <148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB3_C_AHB>, + <&syscon_apmu RESET_APMU_USB3_C_VCC>, + <&syscon_apmu RESET_APMU_USB3_C_PHY>; + reset-names = "ahb", "vcc", "phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + usb3c_u2phy: phy@81800000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0x81800000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + usb3d: usb@81a00000 { compatible = "spacemit,k3-dwc3"; reg = <0x0 0x81a00000 0x0 0x10000>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board @ 2026-08-31 4:44 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V ARCHITECTURE, open list:RISC-V SPACEMIT SoC Support The SpacemiT K3 has 4 USB3 controllers labelled A to D. On the K3 Pico-ITX board, the controllers B and C are used in USB2 mode only respectively for the M.2 B-Key slot and for the RTL8852BE Bluetooth controller. Add the two controller nodes. On the K3 Pico-ITX board, enable the controllers nodes and add the two corresponding USB2 PHY nodes. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 22 +++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 60 ++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 0a6f669d509a9..5aa6fa89cab58 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -323,6 +323,28 @@ &usb2_phy { status = "okay"; }; +&usb3b { + phys = <&usb3b_u2phy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb3b_u2phy { + status = "okay"; +}; + +&usb3c { + phys = <&usb3c_u2phy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb3c_u2phy { + status = "okay"; +}; + &usb3d_u2phy { status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 6f8d55eae6f6b..55b00c0f429f7 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -441,6 +441,66 @@ soc: soc { dma-noncoherent; ranges; + usb3b: usb@81400000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81400000 0x0 0x10000>; + interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB3_B_AHB>, + <&syscon_apmu RESET_APMU_USB3_B_VCC>, + <&syscon_apmu RESET_APMU_USB3_B_PHY>; + reset-names = "ahb", "vcc", "phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + usb3b_u2phy: phy@81500000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0x81500000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3c: usb@81700000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81700000 0x0 0x10000>; + interrupts = <148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB3_C_AHB>, + <&syscon_apmu RESET_APMU_USB3_C_VCC>, + <&syscon_apmu RESET_APMU_USB3_C_PHY>; + reset-names = "ahb", "vcc", "phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + usb3c_u2phy: phy@81800000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0x81800000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + usb3d: usb@81a00000 { compatible = "spacemit,k3-dwc3"; reg = <0x0 0x81a00000 0x0 0x10000>; -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 3/5] riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX board 2026-08-31 4:44 ` Aurelien Jarno @ 2026-08-31 4:44 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the K3 Pico-ITX board, by default the GPIO pin that connects to the RTL8852BE Bluetooth enable signal is driven low, resulting in impossibility to use Bluetooth. Add a DT node to expose it as an RFKILL device, which lets the Bluetooth driver or userspace toggle it as required. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 5aa6fa89cab58..d3f256dffb4fd 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -43,6 +43,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { regulator-max-microvolt = <5000000>; regulator-always-on; }; + + rfkill-usb-bt { + compatible = "rfkill-gpio"; + label = "rfkill-usb-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio 0 30 GPIO_ACTIVE_HIGH>; + }; }; &i2c2 { -- 2.53.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 3/5] riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX board @ 2026-08-31 4:44 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the K3 Pico-ITX board, by default the GPIO pin that connects to the RTL8852BE Bluetooth enable signal is driven low, resulting in impossibility to use Bluetooth. Add a DT node to expose it as an RFKILL device, which lets the Bluetooth driver or userspace toggle it as required. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 5aa6fa89cab58..d3f256dffb4fd 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -43,6 +43,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { regulator-max-microvolt = <5000000>; regulator-always-on; }; + + rfkill-usb-bt { + compatible = "rfkill-gpio"; + label = "rfkill-usb-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio 0 30 GPIO_ACTIVE_HIGH>; + }; }; &i2c2 { -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 4/5] riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX board 2026-08-31 4:44 ` Aurelien Jarno @ 2026-08-31 4:44 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the K3 Pico-ITX board, by default the GPIO pin that connects to the RTL8852BE WLAN enable signal is driven low, resulting in impossibility to connect to any network. Add a DT node to expose it as an RFKILL device, which lets the WLAN driver or userspace toggle it as required. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index d3f256dffb4fd..dda420900aa2c 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -44,6 +44,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { regulator-always-on; }; + rfkill-pcie-wlan { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio 1 3 GPIO_ACTIVE_HIGH>; + }; + rfkill-usb-bt { compatible = "rfkill-gpio"; label = "rfkill-usb-bt"; -- 2.53.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 4/5] riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX board @ 2026-08-31 4:44 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: Aurelien Jarno, Anirudh Srinivasan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the K3 Pico-ITX board, by default the GPIO pin that connects to the RTL8852BE WLAN enable signal is driven low, resulting in impossibility to connect to any network. Add a DT node to expose it as an RFKILL device, which lets the WLAN driver or userspace toggle it as required. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index d3f256dffb4fd..dda420900aa2c 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -44,6 +44,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { regulator-always-on; }; + rfkill-pcie-wlan { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio 1 3 GPIO_ACTIVE_HIGH>; + }; + rfkill-usb-bt { compatible = "rfkill-gpio"; label = "rfkill-usb-bt"; -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 5/5] riscv64: defconfig: Enable BT and WLAN support for SpacemiT K3 Pico-ITX board 2026-08-31 4:44 ` Aurelien Jarno ` (4 preceding siblings ...) (?) @ 2026-08-31 4:44 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-31 4:44 UTC (permalink / raw) To: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: Aurelien Jarno, open list:RISC-V ARCHITECTURE The SpacemiT K3 Pico-ITX board has a RTL8852BE Bluetooth and WLAN controller connected through PCIe and USB. For the WLAN part, enable CFG80211, MAC80211, RTW89 and RTW89_8852BE as modules. For the Bluetooth, enable CONFIG_BT and CONFIG_BT_HCIBTUSB as modules. Both also require RFKILL and RFKILL_GPIO. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/configs/defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 04ae305d5511b..1bc79ba2ee649 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -100,6 +100,12 @@ CONFIG_NET_CLS_CGROUP=m CONFIG_NETLINK_DIAG=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CAN=m +CONFIG_BT=m +CONFIG_BT_HCIBTUSB=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y CONFIG_PCI=y @@ -143,6 +149,8 @@ CONFIG_DWMAC_THEAD=m CONFIG_MICREL_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_MOTORCOMM_PHY=y +CONFIG_RTW89=m +CONFIG_RTW89_8852BE=m CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX
@ 2026-08-19 16:15 Aurelien Jarno
2026-08-19 16:15 ` Aurelien Jarno
0 siblings, 1 reply; 24+ messages in thread
From: Aurelien Jarno @ 2026-08-19 16:15 UTC (permalink / raw)
To: linux-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Yixun Lan
Cc: Aurelien Jarno, open list:RISC-V ARCHITECTURE:Keyword:riscv,
open list:RISC-V SPACEMIT SoC Support:Keyword:spacemit
This patchset enables Bluetooth through USB on the K3 Pico ITX board and
adds the rfkill nodes for Bluetooth and WLAN so that the devices can be
activated.
Note that WLAN support also require the following patch series, but
both series can be applied independently:
- https://lore.kernel.org/spacemit/20260709040027.958400-1-inochiama@gmail.com/
Changes v2 -> v3
- reorder patches in a more logical order
- rebase on current linus/master
- add patch 1 to move phy definition to the board level for the "usb3d" controller
- remove link to USB3 phys, they can't be added if the combo phy is not configured accordingly
- enable Bluetooth and WLAN drivers in defconfig
Aurelien Jarno (5):
riscv: dts: spacemit: k3: move USB3 phy to board level
riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX
board
riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX
board
riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX
board
riscv64: defconfig: Enable BT and WLAN support for SpacemiT K3
Pico-ITX board
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 35 ++++++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 69 +++++++++++++++++++-
arch/riscv/configs/defconfig | 8 +++
3 files changed, 109 insertions(+), 3 deletions(-)
--
2.53.0
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-19 16:15 [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX Aurelien Jarno @ 2026-08-19 16:15 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-19 16:15 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the SpacemiT K3 SoC, the combo phy provides 8 lines that can either be used for PCIe or USB3, depending on its configuration (spacemit,apmu). This configuration is defined at the board level, and assigning a phy line to a USB3 controller while it is configured as PCIe results in an "Invalid PHY mode" error. Move the USB3 phy at the board level, the as it is done for the submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as there is one phy per USB controller. [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") Cc: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b084a35aa00e..171bd2f40aa6 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -328,5 +328,8 @@ &usb3d_u2phy { }; &usb3d { + phys = <&usb3d_u2phy>, + <&combophy 4 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index c3f2dce0969c..3e24054d2084 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { <&syscon_apmu RESET_APMU_USB3_D_VCC>, <&syscon_apmu RESET_APMU_USB3_D_PHY>; reset-names = "ahb", "vcc", "phy"; - phys = <&usb3d_u2phy>, - <&combophy 4 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb3d_u2phy>; + phy-names = "usb2-phy"; phy_type = "utmi"; snps,dis_enblslpm_quirk; snps,dis_u2_susphy_quirk; -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-19 16:15 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-19 16:15 UTC (permalink / raw) To: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: Aurelien Jarno, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On the SpacemiT K3 SoC, the combo phy provides 8 lines that can either be used for PCIe or USB3, depending on its configuration (spacemit,apmu). This configuration is defined at the board level, and assigning a phy line to a USB3 controller while it is configured as PCIe results in an "Invalid PHY mode" error. Move the USB3 phy at the board level, the as it is done for the submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as there is one phy per USB controller. [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") Cc: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b084a35aa00e..171bd2f40aa6 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -328,5 +328,8 @@ &usb3d_u2phy { }; &usb3d { + phys = <&usb3d_u2phy>, + <&combophy 4 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index c3f2dce0969c..3e24054d2084 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { <&syscon_apmu RESET_APMU_USB3_D_VCC>, <&syscon_apmu RESET_APMU_USB3_D_PHY>; reset-names = "ahb", "vcc", "phy"; - phys = <&usb3d_u2phy>, - <&combophy 4 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb3d_u2phy>; + phy-names = "usb2-phy"; phy_type = "utmi"; snps,dis_enblslpm_quirk; snps,dis_u2_susphy_quirk; -- 2.53.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-19 16:15 ` Aurelien Jarno @ 2026-08-22 2:17 ` Inochi Amaoto -1 siblings, 0 replies; 24+ messages in thread From: Inochi Amaoto @ 2026-08-22 2:17 UTC (permalink / raw) To: Aurelien Jarno, linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > either be used for PCIe or USB3, depending on its configuration > (spacemit,apmu). This configuration is defined at the board level, and > assigning a phy line to a USB3 controller while it is configured as PCIe > results in an "Invalid PHY mode" error. > > Move the USB3 phy at the board level, the as it is done for the > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > there is one phy per USB controller. > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > Cc: Inochi Amaoto <inochiama@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > index b084a35aa00e..171bd2f40aa6 100644 > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > @@ -328,5 +328,8 @@ &usb3d_u2phy { > }; > > &usb3d { > + phys = <&usb3d_u2phy>, > + <&combophy 4 PHY_TYPE_USB3>; > + phy-names = "usb2-phy", "usb3-phy"; > status = "okay"; > }; > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > index c3f2dce0969c..3e24054d2084 100644 > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > reset-names = "ahb", "vcc", "phy"; > - phys = <&usb3d_u2phy>, > - <&combophy 4 PHY_TYPE_USB3>; > - phy-names = "usb2-phy", "usb3-phy"; > + phys = <&usb3d_u2phy>; > + phy-names = "usb2-phy"; I suggest removing this completely as we can not determine the phy we used. I think it is suitable for setting this in board file only Regards, Inochi > phy_type = "utmi"; > snps,dis_enblslpm_quirk; > snps,dis_u2_susphy_quirk; > -- > 2.53.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-22 2:17 ` Inochi Amaoto 0 siblings, 0 replies; 24+ messages in thread From: Inochi Amaoto @ 2026-08-22 2:17 UTC (permalink / raw) To: Aurelien Jarno, linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Inochi Amaoto Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > either be used for PCIe or USB3, depending on its configuration > (spacemit,apmu). This configuration is defined at the board level, and > assigning a phy line to a USB3 controller while it is configured as PCIe > results in an "Invalid PHY mode" error. > > Move the USB3 phy at the board level, the as it is done for the > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > there is one phy per USB controller. > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > Cc: Inochi Amaoto <inochiama@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > index b084a35aa00e..171bd2f40aa6 100644 > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > @@ -328,5 +328,8 @@ &usb3d_u2phy { > }; > > &usb3d { > + phys = <&usb3d_u2phy>, > + <&combophy 4 PHY_TYPE_USB3>; > + phy-names = "usb2-phy", "usb3-phy"; > status = "okay"; > }; > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > index c3f2dce0969c..3e24054d2084 100644 > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > reset-names = "ahb", "vcc", "phy"; > - phys = <&usb3d_u2phy>, > - <&combophy 4 PHY_TYPE_USB3>; > - phy-names = "usb2-phy", "usb3-phy"; > + phys = <&usb3d_u2phy>; > + phy-names = "usb2-phy"; I suggest removing this completely as we can not determine the phy we used. I think it is suitable for setting this in board file only Regards, Inochi > phy_type = "utmi"; > snps,dis_enblslpm_quirk; > snps,dis_u2_susphy_quirk; > -- > 2.53.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-22 2:17 ` Inochi Amaoto @ 2026-08-22 9:37 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-22 9:37 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On 2026-08-22 10:17, Inochi Amaoto wrote: > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > either be used for PCIe or USB3, depending on its configuration > > (spacemit,apmu). This configuration is defined at the board level, and > > assigning a phy line to a USB3 controller while it is configured as PCIe > > results in an "Invalid PHY mode" error. > > > > Move the USB3 phy at the board level, the as it is done for the > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > there is one phy per USB controller. > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > Cc: Inochi Amaoto <inochiama@gmail.com> > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > --- > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > index b084a35aa00e..171bd2f40aa6 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > }; > > > > &usb3d { > > + phys = <&usb3d_u2phy>, > > + <&combophy 4 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > status = "okay"; > > }; > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > index c3f2dce0969c..3e24054d2084 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > reset-names = "ahb", "vcc", "phy"; > > > - phys = <&usb3d_u2phy>, > > - <&combophy 4 PHY_TYPE_USB3>; > > - phy-names = "usb2-phy", "usb3-phy"; > > + phys = <&usb3d_u2phy>; > > + phy-names = "usb2-phy"; > > I suggest removing this completely as we can not determine the > phy we used. I think it is suitable for setting this in board > file only Yes, moving all the phy definition to the board level is an option. I decided to keep the USB2 phy at the SoC level, because contrary to the USB3 phys, there is a one to one mapping between the controller and the phy. Do you think it is a wrong assumption? Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-22 9:37 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-22 9:37 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On 2026-08-22 10:17, Inochi Amaoto wrote: > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > either be used for PCIe or USB3, depending on its configuration > > (spacemit,apmu). This configuration is defined at the board level, and > > assigning a phy line to a USB3 controller while it is configured as PCIe > > results in an "Invalid PHY mode" error. > > > > Move the USB3 phy at the board level, the as it is done for the > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > there is one phy per USB controller. > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > Cc: Inochi Amaoto <inochiama@gmail.com> > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > --- > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > index b084a35aa00e..171bd2f40aa6 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > }; > > > > &usb3d { > > + phys = <&usb3d_u2phy>, > > + <&combophy 4 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > status = "okay"; > > }; > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > index c3f2dce0969c..3e24054d2084 100644 > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > reset-names = "ahb", "vcc", "phy"; > > > - phys = <&usb3d_u2phy>, > > - <&combophy 4 PHY_TYPE_USB3>; > > - phy-names = "usb2-phy", "usb3-phy"; > > + phys = <&usb3d_u2phy>; > > + phy-names = "usb2-phy"; > > I suggest removing this completely as we can not determine the > phy we used. I think it is suitable for setting this in board > file only Yes, moving all the phy definition to the board level is an option. I decided to keep the USB2 phy at the SoC level, because contrary to the USB3 phys, there is a one to one mapping between the controller and the phy. Do you think it is a wrong assumption? Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-22 9:37 ` Aurelien Jarno @ 2026-08-22 12:33 ` Inochi Amaoto -1 siblings, 0 replies; 24+ messages in thread From: Inochi Amaoto @ 2026-08-22 12:33 UTC (permalink / raw) To: Inochi Amaoto, linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On Sat, Aug 22, 2026 at 11:37:44AM +0200, Aurelien Jarno wrote: > On 2026-08-22 10:17, Inochi Amaoto wrote: > > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > > either be used for PCIe or USB3, depending on its configuration > > > (spacemit,apmu). This configuration is defined at the board level, and > > > assigning a phy line to a USB3 controller while it is configured as PCIe > > > results in an "Invalid PHY mode" error. > > > > > > Move the USB3 phy at the board level, the as it is done for the > > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > > there is one phy per USB controller. > > > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > > Cc: Inochi Amaoto <inochiama@gmail.com> > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > --- > > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > index b084a35aa00e..171bd2f40aa6 100644 > > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > > }; > > > > > > &usb3d { > > > + phys = <&usb3d_u2phy>, > > > + <&combophy 4 PHY_TYPE_USB3>; > > > + phy-names = "usb2-phy", "usb3-phy"; > > > status = "okay"; > > > }; > > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > index c3f2dce0969c..3e24054d2084 100644 > > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > > reset-names = "ahb", "vcc", "phy"; > > > > > - phys = <&usb3d_u2phy>, > > > - <&combophy 4 PHY_TYPE_USB3>; > > > - phy-names = "usb2-phy", "usb3-phy"; > > > + phys = <&usb3d_u2phy>; > > > + phy-names = "usb2-phy"; > > > > I suggest removing this completely as we can not determine the > > phy we used. I think it is suitable for setting this in board > > file only > > Yes, moving all the phy definition to the board level is an option. I > decided to keep the USB2 phy at the SoC level, because contrary to the > USB3 phys, there is a one to one mapping between the controller and the > phy. Do you think it is a wrong assumption? > By default, I prefer to make the forgotten thing as an error in validation for any flexible field. If you leave the default value, the forgotten field will lead to a downgrade hardware (or maybe broken hardware). So I prefer to remove this rather than give a default value. Regards, Inochi ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-22 12:33 ` Inochi Amaoto 0 siblings, 0 replies; 24+ messages in thread From: Inochi Amaoto @ 2026-08-22 12:33 UTC (permalink / raw) To: Inochi Amaoto, linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On Sat, Aug 22, 2026 at 11:37:44AM +0200, Aurelien Jarno wrote: > On 2026-08-22 10:17, Inochi Amaoto wrote: > > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > > either be used for PCIe or USB3, depending on its configuration > > > (spacemit,apmu). This configuration is defined at the board level, and > > > assigning a phy line to a USB3 controller while it is configured as PCIe > > > results in an "Invalid PHY mode" error. > > > > > > Move the USB3 phy at the board level, the as it is done for the > > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > > there is one phy per USB controller. > > > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > > Cc: Inochi Amaoto <inochiama@gmail.com> > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > --- > > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > index b084a35aa00e..171bd2f40aa6 100644 > > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > > }; > > > > > > &usb3d { > > > + phys = <&usb3d_u2phy>, > > > + <&combophy 4 PHY_TYPE_USB3>; > > > + phy-names = "usb2-phy", "usb3-phy"; > > > status = "okay"; > > > }; > > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > index c3f2dce0969c..3e24054d2084 100644 > > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > > reset-names = "ahb", "vcc", "phy"; > > > > > - phys = <&usb3d_u2phy>, > > > - <&combophy 4 PHY_TYPE_USB3>; > > > - phy-names = "usb2-phy", "usb3-phy"; > > > + phys = <&usb3d_u2phy>; > > > + phy-names = "usb2-phy"; > > > > I suggest removing this completely as we can not determine the > > phy we used. I think it is suitable for setting this in board > > file only > > Yes, moving all the phy definition to the board level is an option. I > decided to keep the USB2 phy at the SoC level, because contrary to the > USB3 phys, there is a one to one mapping between the controller and the > phy. Do you think it is a wrong assumption? > By default, I prefer to make the forgotten thing as an error in validation for any flexible field. If you leave the default value, the forgotten field will lead to a downgrade hardware (or maybe broken hardware). So I prefer to remove this rather than give a default value. Regards, Inochi _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level 2026-08-22 12:33 ` Inochi Amaoto @ 2026-08-22 13:37 ` Aurelien Jarno -1 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-22 13:37 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On 2026-08-22 20:33, Inochi Amaoto wrote: > On Sat, Aug 22, 2026 at 11:37:44AM +0200, Aurelien Jarno wrote: > > On 2026-08-22 10:17, Inochi Amaoto wrote: > > > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > > > either be used for PCIe or USB3, depending on its configuration > > > > (spacemit,apmu). This configuration is defined at the board level, and > > > > assigning a phy line to a USB3 controller while it is configured as PCIe > > > > results in an "Invalid PHY mode" error. > > > > > > > > Move the USB3 phy at the board level, the as it is done for the > > > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > > > there is one phy per USB controller. > > > > > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > > > Cc: Inochi Amaoto <inochiama@gmail.com> > > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > > --- > > > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > index b084a35aa00e..171bd2f40aa6 100644 > > > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > > > }; > > > > > > > > &usb3d { > > > > + phys = <&usb3d_u2phy>, > > > > + <&combophy 4 PHY_TYPE_USB3>; > > > > + phy-names = "usb2-phy", "usb3-phy"; > > > > status = "okay"; > > > > }; > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > index c3f2dce0969c..3e24054d2084 100644 > > > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > > > reset-names = "ahb", "vcc", "phy"; > > > > > > > - phys = <&usb3d_u2phy>, > > > > - <&combophy 4 PHY_TYPE_USB3>; > > > > - phy-names = "usb2-phy", "usb3-phy"; > > > > + phys = <&usb3d_u2phy>; > > > > + phy-names = "usb2-phy"; > > > > > > I suggest removing this completely as we can not determine the > > > phy we used. I think it is suitable for setting this in board > > > file only > > > > Yes, moving all the phy definition to the board level is an option. I > > decided to keep the USB2 phy at the SoC level, because contrary to the > > USB3 phys, there is a one to one mapping between the controller and the > > phy. Do you think it is a wrong assumption? > > > > By default, I prefer to make the forgotten thing as an error in > validation for any flexible field. If you leave the default value, > the forgotten field will lead to a downgrade hardware (or maybe > broken hardware). So I prefer to remove this rather than give a > default value. Ok, thanks for the feedback, i'll fix that in the v4. Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level @ 2026-08-22 13:37 ` Aurelien Jarno 0 siblings, 0 replies; 24+ messages in thread From: Aurelien Jarno @ 2026-08-22 13:37 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:RISC-V SPACEMIT SoC Support, open list:RISC-V SPACEMIT SoC Support On 2026-08-22 20:33, Inochi Amaoto wrote: > On Sat, Aug 22, 2026 at 11:37:44AM +0200, Aurelien Jarno wrote: > > On 2026-08-22 10:17, Inochi Amaoto wrote: > > > On Wed, Aug 19, 2026 at 06:15:42PM +0200, Aurelien Jarno wrote: > > > > On the SpacemiT K3 SoC, the combo phy provides 8 lines that can > > > > either be used for PCIe or USB3, depending on its configuration > > > > (spacemit,apmu). This configuration is defined at the board level, and > > > > assigning a phy line to a USB3 controller while it is configured as PCIe > > > > results in an "Invalid PHY mode" error. > > > > > > > > Move the USB3 phy at the board level, the as it is done for the > > > > submitted PCIe controller [1]. Keep the USB2 phy at the SoC level as > > > > there is one phy per USB controller. > > > > > > > > [1] https://lore.kernel.org/20260727094726.890179-3-inochiama@gmail.com/ > > > > > > > > Fixes: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 ("riscv: dts: spacemit: k3: add USB controller and USB phy support") > > > > Cc: Inochi Amaoto <inochiama@gmail.com> > > > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > > > > --- > > > > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 +++ > > > > arch/riscv/boot/dts/spacemit/k3.dtsi | 5 ++--- > > > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > index b084a35aa00e..171bd2f40aa6 100644 > > > > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > > > > @@ -328,5 +328,8 @@ &usb3d_u2phy { > > > > }; > > > > > > > > &usb3d { > > > > + phys = <&usb3d_u2phy>, > > > > + <&combophy 4 PHY_TYPE_USB3>; > > > > + phy-names = "usb2-phy", "usb3-phy"; > > > > status = "okay"; > > > > }; > > > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > index c3f2dce0969c..3e24054d2084 100644 > > > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > > > > @@ -452,9 +452,8 @@ usb3d: usb@81a00000 { > > > > <&syscon_apmu RESET_APMU_USB3_D_VCC>, > > > > <&syscon_apmu RESET_APMU_USB3_D_PHY>; > > > > reset-names = "ahb", "vcc", "phy"; > > > > > > > - phys = <&usb3d_u2phy>, > > > > - <&combophy 4 PHY_TYPE_USB3>; > > > > - phy-names = "usb2-phy", "usb3-phy"; > > > > + phys = <&usb3d_u2phy>; > > > > + phy-names = "usb2-phy"; > > > > > > I suggest removing this completely as we can not determine the > > > phy we used. I think it is suitable for setting this in board > > > file only > > > > Yes, moving all the phy definition to the board level is an option. I > > decided to keep the USB2 phy at the SoC level, because contrary to the > > USB3 phys, there is a one to one mapping between the controller and the > > phy. Do you think it is a wrong assumption? > > > > By default, I prefer to make the forgotten thing as an error in > validation for any flexible field. If you leave the default value, > the forgotten field will lead to a downgrade hardware (or maybe > broken hardware). So I prefer to remove this rather than give a > default value. Ok, thanks for the feedback, i'll fix that in the v4. Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2026-09-27 21:18 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-08-31 4:44 [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX Aurelien Jarno 2026-08-31 4:44 ` Aurelien Jarno 2026-08-31 4:44 ` [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level Aurelien Jarno 2026-08-31 4:44 ` Aurelien Jarno 2026-08-31 4:54 ` sashiko-bot 2026-09-27 21:18 ` Aurelien Jarno 2026-09-27 21:18 ` Aurelien Jarno 2026-08-31 4:44 ` [PATCH v3 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board Aurelien Jarno 2026-08-31 4:44 ` Aurelien Jarno 2026-08-31 4:44 ` [PATCH v3 3/5] riscv: dts: spacemit: k3: add rfkill node for Bluetooth on " Aurelien Jarno 2026-08-31 4:44 ` Aurelien Jarno 2026-08-31 4:44 ` [PATCH v3 4/5] riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 " Aurelien Jarno 2026-08-31 4:44 ` Aurelien Jarno 2026-08-31 4:44 ` [PATCH v3 5/5] riscv64: defconfig: Enable BT and WLAN support for SpacemiT " Aurelien Jarno -- strict thread matches above, loose matches on Subject: below -- 2026-08-19 16:15 [PATCH v3 0/5] Enable Bluetooth and WiFi on K3 Pico ITX Aurelien Jarno 2026-08-19 16:15 ` [PATCH v3 1/5] riscv: dts: spacemit: k3: move USB3 phy to board level Aurelien Jarno 2026-08-19 16:15 ` Aurelien Jarno 2026-08-22 2:17 ` Inochi Amaoto 2026-08-22 2:17 ` Inochi Amaoto 2026-08-22 9:37 ` Aurelien Jarno 2026-08-22 9:37 ` Aurelien Jarno 2026-08-22 12:33 ` Inochi Amaoto 2026-08-22 12:33 ` Inochi Amaoto 2026-08-22 13:37 ` Aurelien Jarno 2026-08-22 13:37 ` Aurelien Jarno
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