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From: Chen Pei <cp0613@linux.alibaba.com>
To: Drew Fustini <fustini@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, devicetree@vger.kernel.org,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Atish Patra <atish.patra@linux.dev>,
	Reinette Chatre <reinette.chatre@intel.com>,
	Tony Luck <tony.luck@intel.com>, Babu Moger <babu.moger@amd.com>,
	Peter Newman <peternewman@google.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Ved Shanbhogue <ved@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh@kernel.org>,
	Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v6 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Mon, 31 Aug 2026 10:16:16 +0800	[thread overview]
Message-ID: <20260831100216.reply.cp0613@linux.alibaba.com> (raw)
In-Reply-To: <20260729-dfustini-atl-sc-cbqri-dt-v6-5-7c22b05d461b@kernel.org>

Hi Drew,

Thanks for keeping this series alive. While testing v6 on a RISC-V
platform with a CBQRI capacity controller (8 capacity blocks backing
one L3, Ssqosid + CBQRI exposed via DT), I hit a problem that traces
back to this patch; findings and a suggested fix below.

Symptom
-------
With the series applied, the resctrl interface reports an empty
capacity mask everywhere:

  # cat /sys/fs/resctrl/info/L3/cbm_mask
  0
  # cat /sys/fs/resctrl/schemata
  L3:0=0
  # cat /sys/fs/resctrl/size
  L3:0=0

while the hardware reports NCBLKS=8 in the CC capabilities register
(bits[23:8] of cc_capabilities, per CBQRI v1.0 §3.5), i.e. the
expected values are cbm_mask=ff / L3:0=ff.

Root cause
----------
cbqri_resctrl_control_init() fills cbm_len/shareable_bits/min_cbm_bits
but never initializes res->default_ctrl, which therefore stays 0
(static storage):

> +static int cbqri_resctrl_control_init(struct cbqri_cache *ctrl,
> +				      struct rdt_resource *res)
> +{
> +	res->name = kasprintf(...);
> +	res->cache.cbm_len = ctrl->cc.ncblks;
> +	res->cache.shareable_bits = 0;
> +	...

Two visible consequences, both matching the symptom exactly:

1. info/L3/cbm_mask is a direct view of r->default_ctrl
   (rdt_default_ctrl_show()), hence 0.
2. cbqri_init_domain_ctrlval() seeds every RCID's CONFIG_LIMIT from
   resctrl_get_default_ctrl(), i.e. it programs a zero capacity mask
   for all RCIDs (including RCID 0 used by all harts by default); the
   hardware then reads back 0, hence schemata/size show L3:0=0.

For comparison, the x86 resctrl code initializes the default to the
full mask (arch/x86/kernel/cpu/resctrl/core.c: r->default_ctrl =
max_cbm), and an earlier out-of-tree RISC-V CBQRI implementation did
the equivalent (res->default_ctrl = BIT_MASK(ncblks) - 1). It looks
like that initialization was lost in the rework.

Suggested fix
-------------
Initialize the default control to the full capacity mask in
cbqri_resctrl_control_init(), e.g.:

	res->default_ctrl = BIT_MASK(ctrl->cc.ncblks) - 1;

right after res->cache.cbm_len is set. With this one line, cbm_mask
shows ff, schemata/size show L3:0=ff, and writing schemata round-trips
correctly.

Best regards,
Pei

WARNING: multiple messages have this Message-ID (diff)
From: Chen Pei <cp0613@linux.alibaba.com>
To: Drew Fustini <fustini@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, devicetree@vger.kernel.org,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Atish Patra <atish.patra@linux.dev>,
	Reinette Chatre <reinette.chatre@intel.com>,
	Tony Luck <tony.luck@intel.com>, Babu Moger <babu.moger@amd.com>,
	Peter Newman <peternewman@google.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Ved Shanbhogue <ved@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh@kernel.org>,
	Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v6 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Mon, 31 Aug 2026 10:16:16 +0800	[thread overview]
Message-ID: <20260831100216.reply.cp0613@linux.alibaba.com> (raw)
In-Reply-To: <20260729-dfustini-atl-sc-cbqri-dt-v6-5-7c22b05d461b@kernel.org>

Hi Drew,

Thanks for keeping this series alive. While testing v6 on a RISC-V
platform with a CBQRI capacity controller (8 capacity blocks backing
one L3, Ssqosid + CBQRI exposed via DT), I hit a problem that traces
back to this patch; findings and a suggested fix below.

Symptom
-------
With the series applied, the resctrl interface reports an empty
capacity mask everywhere:

  # cat /sys/fs/resctrl/info/L3/cbm_mask
  0
  # cat /sys/fs/resctrl/schemata
  L3:0=0
  # cat /sys/fs/resctrl/size
  L3:0=0

while the hardware reports NCBLKS=8 in the CC capabilities register
(bits[23:8] of cc_capabilities, per CBQRI v1.0 §3.5), i.e. the
expected values are cbm_mask=ff / L3:0=ff.

Root cause
----------
cbqri_resctrl_control_init() fills cbm_len/shareable_bits/min_cbm_bits
but never initializes res->default_ctrl, which therefore stays 0
(static storage):

> +static int cbqri_resctrl_control_init(struct cbqri_cache *ctrl,
> +				      struct rdt_resource *res)
> +{
> +	res->name = kasprintf(...);
> +	res->cache.cbm_len = ctrl->cc.ncblks;
> +	res->cache.shareable_bits = 0;
> +	...

Two visible consequences, both matching the symptom exactly:

1. info/L3/cbm_mask is a direct view of r->default_ctrl
   (rdt_default_ctrl_show()), hence 0.
2. cbqri_init_domain_ctrlval() seeds every RCID's CONFIG_LIMIT from
   resctrl_get_default_ctrl(), i.e. it programs a zero capacity mask
   for all RCIDs (including RCID 0 used by all harts by default); the
   hardware then reads back 0, hence schemata/size show L3:0=0.

For comparison, the x86 resctrl code initializes the default to the
full mask (arch/x86/kernel/cpu/resctrl/core.c: r->default_ctrl =
max_cbm), and an earlier out-of-tree RISC-V CBQRI implementation did
the equivalent (res->default_ctrl = BIT_MASK(ncblks) - 1). It looks
like that initialization was lost in the rework.

Suggested fix
-------------
Initialize the default control to the full capacity mask in
cbqri_resctrl_control_init(), e.g.:

	res->default_ctrl = BIT_MASK(ctrl->cc.ncblks) - 1;

right after res->cache.cbm_len is set. With this one line, cbm_mask
shows ff, schemata/size show L3:0=ff, and writing schemata round-trips
correctly.

Best regards,
Pei

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-08-31  2:16 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-30  1:11 [PATCH v6 0/8] riscv: Add Ssqosid and initial CBQRI resctrl support Drew Fustini
2026-07-30  1:11 ` Drew Fustini
2026-07-30  1:11 ` [PATCH v6 1/8] dt-bindings: riscv: Add Ssqosid extension description Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-08-05  2:46   ` Paul Walmsley
2026-08-05  2:46     ` Paul Walmsley
2026-07-30  1:11 ` [PATCH v6 2/8] riscv: Detect the Ssqosid extension Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-08-05  2:47   ` Paul Walmsley
2026-08-05  2:47     ` Paul Walmsley
2026-08-05  3:40     ` Drew Fustini
2026-08-05  3:40       ` Drew Fustini
2026-07-30  1:11 ` [PATCH v6 3/8] riscv: Add support for srmcfg CSR from " Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:22   ` sashiko-bot
2026-07-30  2:04     ` Drew Fustini
2026-07-30  2:04       ` Drew Fustini
2026-08-05 18:54   ` Paul Walmsley
2026-08-05 18:54     ` Paul Walmsley
2026-08-05 20:50     ` Drew Fustini
2026-08-05 20:50       ` Drew Fustini
2026-08-06  1:21       ` Paul Walmsley
2026-08-06  1:21         ` Paul Walmsley
2026-07-30  1:11 ` [PATCH v6 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:11 ` [PATCH v6 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:27   ` sashiko-bot
2026-07-30  2:09     ` Drew Fustini
2026-07-30  2:09       ` Drew Fustini
2026-08-31  2:16   ` Chen Pei [this message]
2026-08-31  2:16     ` Chen Pei
2026-09-01 22:07     ` Drew Fustini
2026-09-01 22:07       ` Drew Fustini
2026-09-02  2:05       ` Chen Pei
2026-07-30  1:11 ` [PATCH v6 6/8] riscv: Enable resctrl filesystem for Ssqosid Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:11 ` [PATCH v6 7/8] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:11 ` [PATCH v6 8/8] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
2026-07-30  1:11   ` Drew Fustini
2026-07-30  1:21   ` sashiko-bot
2026-07-30  2:11     ` Drew Fustini
2026-07-30  2:11       ` Drew Fustini
2026-08-05  3:00 ` [PATCH v6 0/8] riscv: Add Ssqosid and initial CBQRI resctrl support patchwork-bot+linux-riscv
2026-08-05  3:00   ` patchwork-bot+linux-riscv
2026-08-05 19:00 ` patchwork-bot+linux-riscv
2026-08-05 19:00   ` patchwork-bot+linux-riscv

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