From: Ray Wu <ray.wu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Wenjing Liu <wenjing.liu@amd.com>,
Austin Zheng <austin.zheng@amd.com>, Ray Wu <ray.wu@amd.com>
Subject: [PATCH 35/40] drm/amd/display: Route DCN6 mode programming calcs through function pointer table
Date: Wed, 2 Sep 2026 12:58:57 +0800 [thread overview]
Message-ID: <20260902050411.3473916-36-ray.wu@amd.com> (raw)
In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com>
From: Wenjing Liu <wenjing.liu@amd.com>
[Why]
dml2_core_dcn6_funcs_mode_programming.c called DCN5 and DCN6
calcs functions directly by name, coupling the mode programming
flow to specific generations. Routing through the calcs table
lets a future core generation reuse this flow without editing it.
[How]
Add a static get_calcs(ctx) helper returning ctx->calcs->dcn6.
Replace every direct dcn5_*/dcn6_* calcs call with
get_calcs(ctx)->slot(...). dcn6_populate_mode_programming() did
not previously receive the mp context, so thread
calc_mp_ctx through it to reach get_calcs() for its three calcs
calls. Assign ctx->calcs from core->calcs in
dcn6_mp_build_calculate_mp_context(). Drop the now-unused
dml2_core_dcn5_calcs_dchub.h, dml2_core_dcn5_calcs_display_pipe.h,
and dml2_core_dcn6_calcs_dchub.h includes in favor of
dml2_core_dcn6_calcs.h.
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
---
.../dml2_core_dcn6_funcs_mode_programming.c | 38 +++++++++++--------
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c
index 00194c608f8b..9382745fc2a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c
@@ -2,11 +2,14 @@
//
// Copyright 2025 Advanced Micro Devices, Inc.
#include "dml2_core_dcn6_funcs_mode_programming.h"
-#include "dml2_core_dcn5_calcs_dchub.h"
-#include "dml2_core_dcn6_calcs_dchub.h"
-#include "dml2_core_dcn5_calcs_display_pipe.h"
+#include "dml2_core_dcn6_calcs.h"
#include "dml2_core_utils.h"
+static const struct dml2_core_dcn6_calcs *get_calcs(const struct dml2_core_calculate_mp_context *ctx)
+{
+ return ctx->calcs->dcn6;
+}
+
static void dcn6_mp_populate_odm_mode(const struct dml2_display_solution *solution,
struct dml2_core_internal_mode_program *outputs)
{
@@ -58,7 +61,7 @@ static void dcn6_mp_calculate_dcc_configurations(struct dml2_core_calculate_mp_c
for (k = 0; k < display_cfg->num_planes; ++k) {
DML_LOG_VERBOSE("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);
- dcn5_calculate_dcc_configuration(
+ get_calcs(ctx)->calculate_dcc_configuration(
display_cfg->plane_descriptors[k].surface.dcc.enable,
display_cfg->overrides.dcc_programming_assumes_scan_direction_unknown,
display_cfg->plane_descriptors[k].pixel_format,
@@ -96,7 +99,7 @@ static void dcn6_mp_calculate_pixel_delivery_times(struct dml2_core_calculate_mp
struct dml2_core_internal_mode_program *outputs = states;
//Display Pipeline Delivery Time in Prefetch, Groups
- dcn5_calculate_pixel_delivery_times(
+ get_calcs(ctx)->calculate_pixel_delivery_times(
display_cfg,
inputs->NoOfDPP,
display_cfg->num_planes,
@@ -185,7 +188,7 @@ static void dcn6_mp_calculate_meta_and_pte_times(struct dml2_core_calculate_mp_c
p->TimePerMetaChunkFlip = outputs->TimePerMetaChunkFlip;
p->TimePerChromaMetaChunkFlip = outputs->TimePerChromaMetaChunkFlip;
- dcn5_calculate_meta_and_pte_times(p);
+ get_calcs(ctx)->calculate_meta_and_pte_times(p);
}
static void dcn6_mp_calculate_vm_group_and_request_times(struct dml2_core_calculate_mp_context *ctx,
@@ -196,7 +199,7 @@ static void dcn6_mp_calculate_vm_group_and_request_times(struct dml2_core_calcul
struct dml2_core_internal_mode_program *inputs = states;
struct dml2_core_internal_mode_program *outputs = states;
- dcn5_calculate_vm_group_and_request_times(
+ get_calcs(ctx)->calculate_vm_group_and_request_times(
display_cfg,
display_cfg->num_planes,
inputs->BytePerPixelC,
@@ -431,7 +434,7 @@ static void dcn6_mp_calculate_stutter_efficiency(struct dml2_core_calculate_mp_c
p->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = &outputs->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
// Stutter Efficiency
- dcn6_calculate_stutter_efficiency(func_params, p);
+ get_calcs(ctx)->calculate_stutter_efficiency(func_params, p);
#ifdef __DML_VBA_ALLOW_DELTA__
// Calculate z8 stutter eff assuming 0 reserved space
@@ -444,7 +447,7 @@ static void dcn6_mp_calculate_stutter_efficiency(struct dml2_core_calculate_mp_c
p->StutterPeriod = &outputs->StutterPeriodBestCase;
// Stutter Efficiency
- dcn6_calculate_stutter_efficiency(func_params, p);
+ get_calcs(ctx)->calculate_stutter_efficiency(func_params, p);
#else
outputs->Z8StutterEfficiencyNotIncludingVBlankBestCase = outputs->Z8StutterEfficiencyNotIncludingVBlank;
outputs->Z8StutterEfficiencyBestCase = outputs->Z8StutterEfficiency;
@@ -506,7 +509,7 @@ static void dcn6_mp_calculate_pstate_keepout_dst_lines(struct dml2_core_calculat
struct dml2_core_internal_mode_program *inputs = states;
struct dml2_core_internal_mode_program *outputs = states;
- dcn5_calculate_pstate_keepout_dst_lines(display_cfg, &inputs->Watermark,
+ get_calcs(ctx)->calculate_pstate_keepout_dst_lines(display_cfg, &inputs->Watermark,
outputs->pstate_keepout_dst_lines);
}
@@ -958,7 +961,8 @@ static void dcn6_populate_qos_bound(struct dml2_display_cfg_programming *program
programming->qos_bound.lsdma_bandwidth_lb_kbps = solution->validation_result.mode_support.global.lsdma_bw_req_for_alt_kbps;
}
-static void dcn6_populate_mode_programming(struct dml2_display_cfg_programming *programming,
+static void dcn6_populate_mode_programming(struct dml2_core_calculate_mp_context *ctx,
+ struct dml2_display_cfg_programming *programming,
struct dml2_core_internal_scratch *s,
const struct dml2_core_internal_display_mode_lib *mode_lib,
const struct dml2_display_solution *solution,
@@ -976,9 +980,10 @@ static void dcn6_populate_mode_programming(struct dml2_display_cfg_programming *
memcpy(&programming->display_config, &solution->dispcfg, sizeof(struct dml2_display_cfg));
dcn6_populate_min_clocks(programming, solution, utm_soc_bb);
- dcn5_get_arb_params(&programming->display_config, mode_lib, utm_soc_bb, &programming->global_regs.arb_regs);
+ get_calcs(ctx)->get_arb_params(&programming->display_config, mode_lib, utm_soc_bb, &programming->global_regs.arb_regs);
programming->global_regs.num_watermark_sets = 1;
- dcn6_get_watermarks(&programming->display_config, mode_lib, utm_soc_bb, &programming->global_regs.wm_regs[0]);
+ get_calcs(ctx)->get_watermarks(&programming->display_config, mode_lib, utm_soc_bb,
+ &programming->global_regs.wm_regs[0]);
dcn6_populate_stutter_support(programming, mode_lib, solution, utm_soc_bb);
dcn6_populate_mcache_allocation(programming, solution);
dcn6_populate_qos_bound(programming, solution);
@@ -1023,7 +1028,9 @@ static void dcn6_populate_mode_programming(struct dml2_display_cfg_programming *
total_pipe_regs_copied++;
// Populate
- dcn6_get_pipe_regs(&programming->display_config, mode_lib, programming->plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_pipe_index, utm_soc_bb, s);
+ get_calcs(ctx)->get_pipe_regs(&programming->display_config, mode_lib,
+ programming->plane_programming[plane_index].pipe_regs[pipe_offset],
+ dml_internal_pipe_index, utm_soc_bb, s);
main_stream_index = programming->display_config.plane_descriptors[plane_index].stream_index;
@@ -1138,6 +1145,7 @@ static void dcn6_mp_build_calculate_mp_context(struct dml2_core_calculate_mp_con
ctx->ms = &mode_lib->ms;
ctx->dummies = &mode_lib->scratch.dml_core_mode_programming_locals;
ctx->func_params = &mode_lib->scratch;
+ ctx->calcs = &core->calcs;
}
static void dcn6_mp_initialize_from_ms(struct dml2_core_internal_mode_program *outputs,
@@ -1383,7 +1391,7 @@ enum dml2_status dml2_core_dcn6_funcs_populate_programming(struct dml2_core_inst
dcn6_mp_initialize_from_solution(&mode_lib->mp, solution, core->utm_soc_bb);
dcn6_mp_build_calculate_mp_context(calc_mp_ctx, core, solution);
dcn6_calculate_mode_programming(calc_mp_ctx, &mode_lib->mp);
- dcn6_populate_mode_programming(programming, &mode_lib->scratch, mode_lib, solution, core->utm_soc_bb);
+ dcn6_populate_mode_programming(calc_mp_ctx, programming, &mode_lib->scratch, mode_lib, solution, core->utm_soc_bb);
DML_LOG_DEBUG("%s exit\n", __func__);
DML_LOG_COMP_IF_EXIT();
--
2.43.0
next prev parent reply other threads:[~2026-09-02 5:09 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 4:58 [PATCH 00/40] DC Patches September 7, 2026 Ray Wu
2026-09-02 4:58 ` [PATCH 01/40] drm/amd/display: Ensure requested LSDMA BW is within the SOP bound Ray Wu
2026-09-02 4:58 ` [PATCH 02/40] drm/amd/display: Refactor DC_SEND_CURSOR_INFO_TO_DMU to drop pipe_ctx Ray Wu
2026-09-02 4:58 ` [PATCH 03/40] drm/amd/display: Test vblank IRQ handling Ray Wu
2026-09-02 4:58 ` [PATCH 04/40] drm/amd/display: Test self refresh entry Ray Wu
2026-09-02 4:58 ` [PATCH 05/40] drm/amd/display: Test GPU reset helpers Ray Wu
2026-09-02 4:58 ` [PATCH 06/40] drm/amd/display: Add override for LSDMA BW in QoS table Ray Wu
2026-09-02 4:58 ` [PATCH 07/40] drm/amd/display: Test plane update adapter Ray Wu
2026-09-02 4:58 ` [PATCH 08/40] drm/amd/display: Test MST resume guards Ray Wu
2026-09-02 4:58 ` [PATCH 09/40] drm/amd/display: Test cached suspend state Ray Wu
2026-09-02 4:58 ` [PATCH 10/40] drm/amd/display: Test writeback state transitions Ray Wu
2026-09-02 4:58 ` [PATCH 11/40] drm/amd/display: Test atomic validation guards Ray Wu
2026-09-02 4:58 ` [PATCH 12/40] drm/amd/display: Cover dm_restore_drm_connector_state Ray Wu
2026-09-02 4:58 ` [PATCH 13/40] drm/amd/display: Cover EDID CEA parsing helpers Ray Wu
2026-09-02 4:58 ` [PATCH 14/40] drm/amd/display: Make sure streamclk gating is off when enabling streamclk Ray Wu
2026-09-02 4:58 ` [PATCH 15/40] drm/amd/display: Remove unnecessary includes Ray Wu
2026-09-02 4:58 ` [PATCH 16/40] drm/amd/display: Set mpc_tree_params->opp_id during OPP resource construct Ray Wu
2026-09-02 4:58 ` [PATCH 17/40] drm/amd/display: Add override capability for UTM table params Ray Wu
2026-09-02 4:58 ` [PATCH 18/40] drm/amd/display: Add immediate restore to FAMS2 for DRR Ray Wu
2026-09-02 4:58 ` [PATCH 19/40] drm/amd/display: Fix missing APG regs for DCN60 HDMI Ray Wu
2026-09-02 4:58 ` [PATCH 20/40] drm/amd/display: Exit IPS before connector detection on resume Ray Wu
2026-09-02 4:58 ` [PATCH 21/40] drm/amd/display: Fix HF-VSDB DSC bpc detection to be cumulative Ray Wu
2026-09-02 4:58 ` [PATCH 22/40] drm/amd/display: Fix unused params in flip sched Ray Wu
2026-09-02 4:58 ` [PATCH 23/40] drm/amd/display: Enable FW locality check in DCN6 Ray Wu
2026-09-02 4:58 ` [PATCH 24/40] drm/amd/display: Fix DC Hub reference frequency assert range Ray Wu
2026-09-02 4:58 ` [PATCH 25/40] drm/amd/display: Dump clock registers in HW init instead of SW init Ray Wu
2026-09-02 4:58 ` [PATCH 26/40] drm/amd/display: Validate irq source in DM IRQ handler Ray Wu
2026-09-02 4:58 ` [PATCH 27/40] drm/amd/display: Test DM IRQ handler source guard Ray Wu
2026-09-02 4:58 ` [PATCH 28/40] Revert "drm/amd/display: Fix CalculateFlipSchedule Calculation" Ray Wu
2026-09-02 4:58 ` [PATCH 29/40] drm/amd/display: Set DISPCLK per surface in DML Ray Wu
2026-09-02 4:58 ` [PATCH 30/40] drm/amd/display: Update Urgent Burst Calculation To Account For Unbounded Requests Ray Wu
2026-09-02 4:58 ` [PATCH 31/40] drm/amd/display: Add stressed peak bandwidth probe with DMA contention Ray Wu
2026-09-02 4:58 ` [PATCH 32/40] Revert "drm/amd/display: Unify CalculateFlipSchedule Logic" Ray Wu
2026-09-02 4:58 ` [PATCH 33/40] drm/amd/display: Add dml2_core_dcn6_calcs function pointer table Ray Wu
2026-09-02 4:58 ` [PATCH 34/40] drm/amd/display: Route DCN6 mode support calcs through " Ray Wu
2026-09-02 4:58 ` Ray Wu [this message]
2026-09-02 4:58 ` [PATCH 36/40] drm/amd/display: Update DML fields used for mode support Ray Wu
2026-09-02 4:58 ` [PATCH 37/40] drm/amd/display: Fix NULL deref of new_stream->sink in VTEM guard Ray Wu
2026-09-02 4:59 ` [PATCH 38/40] drm/amd/display: Fix signedness mismatches in cm3 Ray Wu
2026-09-02 4:59 ` [PATCH 39/40] drm/amd/display: [FW Promotion] Release 0.1.74.0 Ray Wu
2026-09-02 4:59 ` [PATCH 40/40] drm/amd/display: Promote DC to 3.2.397 Ray Wu
2026-09-09 13:17 ` [PATCH 00/40] DC Patches September 7, 2026 Wheeler, Daniel
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