From: Ray Wu <ray.wu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Alvin Lee <Alvin.Lee2@amd.com>, Wenjing Liu <wenjing.liu@amd.com>,
Ray Wu <ray.wu@amd.com>
Subject: [PATCH 17/40] drm/amd/display: Add override capability for UTM table params
Date: Wed, 2 Sep 2026 12:58:39 +0800 [thread overview]
Message-ID: <20260902050411.3473916-18-ray.wu@amd.com> (raw)
In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com>
From: Alvin Lee <Alvin.Lee2@amd.com>
[Why & How]
Add calls for overriding UTM table params from PMFW. This is for
debug and test purposes only when PMFW has not yet populated the table
values correctly.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h | 2 +-
.../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 70 +++++++++++++++++--
.../dc/clk_mgr/dcn60/dcn60_smu_driver_if.h | 44 ++++++------
3 files changed, 88 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
index 6954a54dad89..9b109959bd7f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
@@ -112,7 +112,7 @@ typedef struct {
* TABLE_DAL_INIT - Full TABLE_DAL_INIT payload transferred from SMU to DRAM.
*/
#define TABLE_DAL_INIT 0xD
-#define MAX_PPCLK_COUNT 20
+#define MAX_PPCLK_COUNT 22
#define DPM_CLOCK_OFFSET(Ppclk) \
(sizeof(DalInitHeader_t) + (Ppclk) * sizeof(DpmClock_t))
#define UTM_TABLE_OFFSET \
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 83989b4b1fdd..2b7740b82161 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -479,6 +479,39 @@ static int dcn60_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
return dtb_ref_clk_khz;
}
+/**
+ * dcn60_override_dc_mode_limit - Override DC mode limits from the clock table.
+ * @dc_limit: output DC mode limit to populate
+ * @clk_table: clock table already populated (and possibly overridden)
+ *
+ * Sets the DC mode max frequency for each clock to the highest populated DPM
+ * level in the clock table. Deriving the limit from the clock table (rather
+ * than the raw DAL init table) ensures any overrides applied to the clock
+ * levels are respected.
+ */
+static void dcn60_override_dc_mode_limit(
+ struct clk_limit_table_entry *dc_limit,
+ const struct clk_limit_table *clk_table)
+{
+ const struct clk_limit_table_entry *entries = clk_table->entries;
+ const struct clk_limit_num_entries *num_entries = &clk_table->num_entries_per_clk;
+
+ dc_limit->dcfclk_mhz = num_entries->num_dcfclk_levels ?
+ entries[num_entries->num_dcfclk_levels - 1].dcfclk_mhz : 0;
+ dc_limit->socclk_mhz = num_entries->num_socclk_levels ?
+ entries[num_entries->num_socclk_levels - 1].socclk_mhz : 0;
+ dc_limit->dtbclk_mhz = num_entries->num_dtbclk_levels ?
+ entries[num_entries->num_dtbclk_levels - 1].dtbclk_mhz : 0;
+ dc_limit->dispclk_mhz = num_entries->num_dispclk_levels ?
+ entries[num_entries->num_dispclk_levels - 1].dispclk_mhz : 0;
+ dc_limit->dppclk_mhz = num_entries->num_dppclk_levels ?
+ entries[num_entries->num_dppclk_levels - 1].dppclk_mhz : 0;
+ dc_limit->memclk_mhz = num_entries->num_memclk_levels ?
+ entries[num_entries->num_memclk_levels - 1].memclk_mhz : 0;
+ dc_limit->fclk_mhz = num_entries->num_fclk_levels ?
+ entries[num_entries->num_fclk_levels - 1].fclk_mhz : 0;
+}
+
static unsigned int dcn60_get_dc_mode_limit_mhz(const DpmClock_t *dpm_clk)
{
if (dpm_clk->NumClocks
@@ -495,8 +528,10 @@ static unsigned int dcn60_get_dc_mode_limit_mhz(const DpmClock_t *dpm_clk)
*
* Sets the DC mode max frequency for each clock. If DcMaxClock equals the
* highest DPM level, the limit is set to 0 (no DC-specific cap).
+ *
+ * Temporarily unused.
*/
-static void dcn60_populate_dc_mode_limit(
+static void __maybe_unused dcn60_populate_dc_mode_limit(
struct clk_limit_table_entry *dc_limit,
const DalInitTable_t *init_table)
{
@@ -578,6 +613,20 @@ static void dcn60_populate_clk_table(struct clk_mgr_internal *clk_mgr,
clk_table->num_entries = 1;
}
+/**
+ * dcn60_override_clk_table - Override the clock table with hardcoded values.
+ * @clk_table: clock table to override
+ *
+ * Temporary debug/bring-up override that replaces the DPM clock levels
+ * populated from the DAL init table (see dcn60_populate_clk_table) with a
+ * fixed set of hardcoded values. Implement any override as needed.
+ */
+static void dcn60_override_clk_table(struct clk_limit_table *clk_table)
+{
+ /* Override as needed */
+ (void)clk_table;
+}
+
static void dcn60_override_bw_params(struct clk_mgr_internal *clk_mgr,
struct clk_bw_params *bw_params)
{
@@ -605,12 +654,17 @@ static void dcn60_override_bw_params(struct clk_mgr_internal *clk_mgr,
bw_params->dc_mode_softmax_memclk = bw_params->dc_mode_limit.memclk_mhz;
- /* The qos model stores dchub_v3 as a const view of a mutable table, so
- * cast away const to apply the override.
- */
- if (bw_params->utm_qos_model && bw_params->utm_qos_model->dchub_v3)
+ /* Override as needed - temporary for debug only. */
+ if (bw_params->utm_qos_model && bw_params->utm_qos_model->dchub_v3) {
+ dcn6_test_initialize_utm_qos_model_v3(
+ (struct utm_qos_model *)bw_params->utm_qos_model,
+ (struct utm_qos_model_dchub_v3 *)bw_params->utm_qos_model->dchub_v3);
+
+ // Override for lsdma here is redundant with the above call, but this may need to outlive
+ // the test_initialize call for debug purposes so keep it here for now.
dcn6_test_override_lsdma_bandwidth_v3(
(struct utm_qos_model_dchub_v3 *)bw_params->utm_qos_model->dchub_v3);
+ }
}
/**
@@ -685,7 +739,9 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr)
clk_mgr->smu_ver = init_table->Header.SmuVersion;
dcn60_populate_clk_table(clk_mgr, &bw_params->clk_table, init_table);
- dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table);
+ // Comment out for now - DC mode limit is not yet used in DCN6 and the current
+ // population from init table will cause undefined behaviors.
+ //dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table);
bw_params->num_channels = init_table->MemoryConfig.NumUmcChannels;
bw_params->dram_channel_width_bytes =
@@ -694,6 +750,8 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr)
dcn60_populate_utm_qos_model(clk_mgr, &bw_params->utm_qos_model, init_table);
dcn60_override_bw_params(clk_mgr, bw_params);
+ dcn60_override_clk_table(&bw_params->clk_table);
+ dcn60_override_dc_mode_limit(&bw_params->dc_mode_limit, &bw_params->clk_table);
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h
index 3e101fa87cfd..ca23518d88b9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h
@@ -9,27 +9,29 @@
//Only Clks that have DPM descriptors are listed here
// This should be the same order as DPM_e
typedef enum {
- PPCLK_GFXCLK = 0,
- PPCLK_BTNCLK = 1,
- PPCLK_LCLK = 2,
- PPCLK_UCLK = 3,
- PPCLK_FCLK = 4,
- PPCLK_G7FCLK = 5,
- PPCLK_SOCCLK = 6,
- PPCLK_ACLK = 7,
- PPCLK_DCFCLK = 8,
- PPCLK_VPECLK = 9,
- PPCLK_DISPCLK = 10,
- PPCLK_DPPCLK = 11,
- PPCLK_DPREFCLK = 12,
- PPCLK_CFPUCLK = 13,
- PPCLK_LOGANCLK = 14,
- PPCLK_MSPCLK = 15,
- PPCLK_MOVADCLK = 16,
- PPCLK_DTBCLK = 17,
- PPCLK_DCLK_0 = 18,
- PPCLK_VCLK_0 = 19,
- PPCLK_COUNT = 20,
+ PPCLK_GFXCLK = 0,
+ PPCLK_NVECLK1,
+ PPCLK_NVECLK2,
+ PPCLK_NVECLK3,
+ PPCLK_LCLK,
+ PPCLK_UCLK,
+ PPCLK_FCLK,
+ PPCLK_G7FCLK,
+ PPCLK_SOCCLK,
+ PPCLK_ACLK,
+ PPCLK_DCFCLK,
+ PPCLK_VPECLK,
+ PPCLK_DISPCLK,
+ PPCLK_DPPCLK,
+ PPCLK_DPREFCLK,
+ PPCLK_CFPUCLK,
+ PPCLK_LOGANCLK,
+ PPCLK_MSPHCLK,
+ PPCLK_MSPLCLK,
+ PPCLK_MSPEDECLK,
+ PPCLK_MOVADCLK,
+ PPCLK_DTBCLK,
+ PPCLK_COUNT,
} PPCLK_e;
typedef struct {
--
2.43.0
next prev parent reply other threads:[~2026-09-02 5:07 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 4:58 [PATCH 00/40] DC Patches September 7, 2026 Ray Wu
2026-09-02 4:58 ` [PATCH 01/40] drm/amd/display: Ensure requested LSDMA BW is within the SOP bound Ray Wu
2026-09-02 4:58 ` [PATCH 02/40] drm/amd/display: Refactor DC_SEND_CURSOR_INFO_TO_DMU to drop pipe_ctx Ray Wu
2026-09-02 4:58 ` [PATCH 03/40] drm/amd/display: Test vblank IRQ handling Ray Wu
2026-09-02 4:58 ` [PATCH 04/40] drm/amd/display: Test self refresh entry Ray Wu
2026-09-02 4:58 ` [PATCH 05/40] drm/amd/display: Test GPU reset helpers Ray Wu
2026-09-02 4:58 ` [PATCH 06/40] drm/amd/display: Add override for LSDMA BW in QoS table Ray Wu
2026-09-02 4:58 ` [PATCH 07/40] drm/amd/display: Test plane update adapter Ray Wu
2026-09-02 4:58 ` [PATCH 08/40] drm/amd/display: Test MST resume guards Ray Wu
2026-09-02 4:58 ` [PATCH 09/40] drm/amd/display: Test cached suspend state Ray Wu
2026-09-02 4:58 ` [PATCH 10/40] drm/amd/display: Test writeback state transitions Ray Wu
2026-09-02 4:58 ` [PATCH 11/40] drm/amd/display: Test atomic validation guards Ray Wu
2026-09-02 4:58 ` [PATCH 12/40] drm/amd/display: Cover dm_restore_drm_connector_state Ray Wu
2026-09-02 4:58 ` [PATCH 13/40] drm/amd/display: Cover EDID CEA parsing helpers Ray Wu
2026-09-02 4:58 ` [PATCH 14/40] drm/amd/display: Make sure streamclk gating is off when enabling streamclk Ray Wu
2026-09-02 4:58 ` [PATCH 15/40] drm/amd/display: Remove unnecessary includes Ray Wu
2026-09-02 4:58 ` [PATCH 16/40] drm/amd/display: Set mpc_tree_params->opp_id during OPP resource construct Ray Wu
2026-09-02 4:58 ` Ray Wu [this message]
2026-09-02 4:58 ` [PATCH 18/40] drm/amd/display: Add immediate restore to FAMS2 for DRR Ray Wu
2026-09-02 4:58 ` [PATCH 19/40] drm/amd/display: Fix missing APG regs for DCN60 HDMI Ray Wu
2026-09-02 4:58 ` [PATCH 20/40] drm/amd/display: Exit IPS before connector detection on resume Ray Wu
2026-09-02 4:58 ` [PATCH 21/40] drm/amd/display: Fix HF-VSDB DSC bpc detection to be cumulative Ray Wu
2026-09-02 4:58 ` [PATCH 22/40] drm/amd/display: Fix unused params in flip sched Ray Wu
2026-09-02 4:58 ` [PATCH 23/40] drm/amd/display: Enable FW locality check in DCN6 Ray Wu
2026-09-02 4:58 ` [PATCH 24/40] drm/amd/display: Fix DC Hub reference frequency assert range Ray Wu
2026-09-02 4:58 ` [PATCH 25/40] drm/amd/display: Dump clock registers in HW init instead of SW init Ray Wu
2026-09-02 4:58 ` [PATCH 26/40] drm/amd/display: Validate irq source in DM IRQ handler Ray Wu
2026-09-02 4:58 ` [PATCH 27/40] drm/amd/display: Test DM IRQ handler source guard Ray Wu
2026-09-02 4:58 ` [PATCH 28/40] Revert "drm/amd/display: Fix CalculateFlipSchedule Calculation" Ray Wu
2026-09-02 4:58 ` [PATCH 29/40] drm/amd/display: Set DISPCLK per surface in DML Ray Wu
2026-09-02 4:58 ` [PATCH 30/40] drm/amd/display: Update Urgent Burst Calculation To Account For Unbounded Requests Ray Wu
2026-09-02 4:58 ` [PATCH 31/40] drm/amd/display: Add stressed peak bandwidth probe with DMA contention Ray Wu
2026-09-02 4:58 ` [PATCH 32/40] Revert "drm/amd/display: Unify CalculateFlipSchedule Logic" Ray Wu
2026-09-02 4:58 ` [PATCH 33/40] drm/amd/display: Add dml2_core_dcn6_calcs function pointer table Ray Wu
2026-09-02 4:58 ` [PATCH 34/40] drm/amd/display: Route DCN6 mode support calcs through " Ray Wu
2026-09-02 4:58 ` [PATCH 35/40] drm/amd/display: Route DCN6 mode programming " Ray Wu
2026-09-02 4:58 ` [PATCH 36/40] drm/amd/display: Update DML fields used for mode support Ray Wu
2026-09-02 4:58 ` [PATCH 37/40] drm/amd/display: Fix NULL deref of new_stream->sink in VTEM guard Ray Wu
2026-09-02 4:59 ` [PATCH 38/40] drm/amd/display: Fix signedness mismatches in cm3 Ray Wu
2026-09-02 4:59 ` [PATCH 39/40] drm/amd/display: [FW Promotion] Release 0.1.74.0 Ray Wu
2026-09-02 4:59 ` [PATCH 40/40] drm/amd/display: Promote DC to 3.2.397 Ray Wu
2026-09-09 13:17 ` [PATCH 00/40] DC Patches September 7, 2026 Wheeler, Daniel
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