From: Joel Stanley <joel@jms.id.au>
To: Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: "Weiwei Li" <liwei1518@gmail.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Chao Liu" <chao.liu@processmission.com>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
"Michael Ellerman" <mpe@kernel.org>,
"Portia Stephens" <portias@oss.tenstorrent.com>,
"Cédric Le Goater" <clg@kaod.org>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
Subject: [PATCH v3 12/16] hw/riscv/atlantis: Decouple RAM size from MachineState
Date: Thu, 3 Sep 2026 15:21:26 +0930 [thread overview]
Message-ID: <20260903055131.257903-13-joel@jms.id.au> (raw)
In-Reply-To: <20260903055131.257903-1-joel@jms.id.au>
Keep a reference to the machine's RAM MemoryRegion in TTAtlantisState,
and get the MemoryRegion's size where the configured RAM size is
required.
This allows reading the RAM size without needing a pointer to
MachineState, decoupling the memory layout setup from the machine.
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
include/hw/riscv/tt_atlantis.h | 1 +
hw/riscv/tt_atlantis.c | 20 ++++++++++++--------
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h
index a29c67c1cfcf..2ec283d0fd7b 100644
--- a/include/hw/riscv/tt_atlantis.h
+++ b/include/hw/riscv/tt_atlantis.h
@@ -30,6 +30,7 @@ struct TTAtlantisState {
const MemMapEntry *memmap;
MemoryRegion *memory;
+ MemoryRegion *dram;
RISCVHartArrayState cpus;
DeviceState *irqchip;
DesignWareI2CState i2c[TT_ATL_NUM_I2C];
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 2a70119c2c6b..90b8e1bc904a 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -82,12 +82,13 @@ static uint32_t next_phandle(void)
static void create_fdt_memory(void *fdt, TTAtlantisState *s)
{
- hwaddr size_lo = MACHINE(s)->ram_size;
+ hwaddr ram_size = memory_region_size(s->dram);
+ hwaddr size_lo = ram_size;
hwaddr size_hi = 0;
if (size_lo > s->memmap[TT_ATL_DDR_LO].size) {
size_lo = s->memmap[TT_ATL_DDR_LO].size;
- size_hi = MACHINE(s)->ram_size - size_lo;
+ size_hi = ram_size - size_lo;
}
riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base,
@@ -486,11 +487,14 @@ static void tt_atlantis_machine_init(MachineState *machine)
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *bootrom = g_new(MemoryRegion, 1);
- ram_addr_t lo_ram_size;
+ ram_addr_t lo_ram_size, ram_size;
int hart_count = machine->smp.cpus;
s->memory = get_system_memory();
+ s->dram = machine->ram;
+ ram_size = memory_region_size(s->dram);
+
s->memmap = tt_atlantis_memmap;
object_initialize_child(OBJECT(machine), "soc", &s->cpus,
@@ -533,20 +537,20 @@ static void tt_atlantis_machine_init(MachineState *machine)
* The high address is where RAM lives. It is always present and may be
* up to 64GB. The low address is an alias of the first 2GB of that RAM.
*/
- if (machine->ram_size > s->memmap[TT_ATL_DDR_HI].size) {
+ if (ram_size > s->memmap[TT_ATL_DDR_HI].size) {
char *sz = size_to_str(s->memmap[TT_ATL_DDR_HI].size);
error_report("RAM size is too large, maximum is %s", sz);
g_free(sz);
exit(EXIT_FAILURE);
}
- memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine->ram,
- 0, machine->ram_size);
+ memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram,
+ 0, ram_size);
memory_region_add_subregion(s->memory,
s->memmap[TT_ATL_DDR_HI].base, ram_hi);
- lo_ram_size = MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size);
- memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->ram,
+ lo_ram_size = MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size);
+ memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram,
0, lo_ram_size);
memory_region_add_subregion(s->memory,
s->memmap[TT_ATL_DDR_LO].base, ram_lo);
--
2.47.3
next prev parent reply other threads:[~2026-09-03 5:54 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 5:51 [PATCH v3 00/16] hw/riscv: Socify Atlantis Joel Stanley
2026-09-03 5:51 ` [PATCH v3 01/16] hw/riscv/aia: Take a MemoryRegion for the created devices Joel Stanley
2026-09-03 6:06 ` Chao Liu via
2026-09-03 6:06 ` Chao Liu via qemu development
2026-09-03 5:51 ` [PATCH v3 02/16] hw/intc/riscv_aclint: " Joel Stanley
2026-09-03 5:51 ` [PATCH v3 03/16] hw/intc/riscv_imsic: Take a MemoryRegion for the created device Joel Stanley
2026-09-03 5:51 ` [PATCH v3 04/16] hw/intc/riscv_aplic: " Joel Stanley
2026-09-03 5:51 ` [PATCH v3 05/16] hw/intc/sifive_plic: " Joel Stanley
2026-09-03 6:07 ` Chao Liu via qemu development
2026-09-03 6:07 ` Chao Liu via
2026-09-03 5:51 ` [PATCH v3 06/16] hw/riscv/cps: Map interrupt controllers in SoC container Joel Stanley
2026-09-03 5:51 ` [PATCH v3 07/16] hw/riscv/atlantis: Make UART unimp region a SoC device Joel Stanley
2026-09-03 5:51 ` [PATCH v3 08/16] hw/riscv/atlantis: Remove unused fdt_size Joel Stanley
2026-09-03 5:51 ` [PATCH v3 09/16] hw/riscv/atlantis: Rename hart array 'soc' to 'cpus' Joel Stanley
2026-09-03 5:51 ` [PATCH v3 10/16] hw/riscv/atlantis: Rework device tree creation Joel Stanley
2026-09-03 5:51 ` [PATCH v3 11/16] hw/riscv/atlantis: Use local reference for system memory Joel Stanley
2026-09-03 5:51 ` Joel Stanley [this message]
2026-09-03 5:51 ` [PATCH v3 13/16] hw/riscv/atlantis: Make TTAtlantisState own memory containers Joel Stanley
2026-09-03 5:51 ` [PATCH v3 14/16] hw/riscv: Add property to hart array to allow private memory Joel Stanley
2026-09-04 10:42 ` Philippe Mathieu-Daudé
2026-09-07 7:27 ` Joel Stanley
2026-09-03 5:51 ` [PATCH v3 15/16] hw/riscv/atlantis: Extract an Atlantis SoC device Joel Stanley
2026-09-04 10:47 ` Philippe Mathieu-Daudé
2026-09-04 10:48 ` Philippe Mathieu-Daudé
2026-09-07 7:16 ` Joel Stanley
2026-09-03 5:51 ` [PATCH v3 16/16] hw/riscv/atlantis: Map the SoC through a memory container Joel Stanley
2026-09-03 23:35 ` [PATCH v3 00/16] hw/riscv: Socify Atlantis Alistair Francis
2026-09-04 10:49 ` Philippe Mathieu-Daudé
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