From: Joel Stanley <joel@jms.id.au>
To: Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: "Weiwei Li" <liwei1518@gmail.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Chao Liu" <chao.liu@processmission.com>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
"Michael Ellerman" <mpe@kernel.org>,
"Portia Stephens" <portias@oss.tenstorrent.com>,
"Cédric Le Goater" <clg@kaod.org>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
Subject: [PATCH v3 05/16] hw/intc/sifive_plic: Take a MemoryRegion for the created device
Date: Thu, 3 Sep 2026 15:21:19 +0930 [thread overview]
Message-ID: <20260903055131.257903-6-joel@jms.id.au> (raw)
In-Reply-To: <20260903055131.257903-1-joel@jms.id.au>
sifive_plic_create() maps the device it creates into system_memory,
which prevents its use by SoCs that map devices into their own memory
container.
Add a MemoryRegion parameter and map the device into it instead of
calling sysbus_mmio_map(). All callers pass system_memory, so there is
no change in behaviour.
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
include/hw/intc/sifive_plic.h | 4 ++--
hw/intc/sifive_plic.c | 7 ++++---
hw/riscv/k230.c | 3 ++-
hw/riscv/microchip_pfsoc.c | 3 ++-
hw/riscv/shakti_c.c | 3 ++-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 3 ++-
hw/riscv/virt.c | 1 +
8 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index 32973dbf281e..064754c3f628 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -76,8 +76,8 @@ struct SiFivePLICState {
qemu_irq *s_external_irqs;
};
-DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
- uint32_t num_harts,
+DeviceState *sifive_plic_create(MemoryRegion *container,
+ hwaddr addr, char *hart_config, uint32_t num_harts,
uint32_t hartid_base, uint32_t num_sources,
uint32_t num_priorities, uint32_t priority_base,
uint32_t pending_base, uint32_t enable_base,
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9c84ff06a9fd..90f17e6ee724 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -473,8 +473,8 @@ type_init(sifive_plic_register_types)
/*
* Create PLIC device.
*/
-DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
- uint32_t num_harts,
+DeviceState *sifive_plic_create(MemoryRegion *container,
+ hwaddr addr, char *hart_config, uint32_t num_harts,
uint32_t hartid_base, uint32_t num_sources,
uint32_t num_priorities, uint32_t priority_base,
uint32_t pending_base, uint32_t enable_base,
@@ -499,7 +499,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
qdev_prop_set_uint32(dev, "context-stride", context_stride);
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+ memory_region_add_subregion(container, addr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
plic = SIFIVE_PLIC(dev);
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 1ef4260c5391..6b0f0453c80b 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -134,7 +134,8 @@ static DeviceState *k230_create_plic(int base_hartid, int hartid_count)
plic_hart_config = riscv_plic_hart_config_string(hartid_count);
/* Per-socket PLIC */
- return sifive_plic_create(memmap[K230_DEV_PLIC].base,
+ return sifive_plic_create(get_system_memory(),
+ memmap[K230_DEV_PLIC].base,
plic_hart_config, hartid_count, base_hartid,
K230_PLIC_NUM_SOURCES,
K230_PLIC_NUM_PRIORITIES,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index a6026776d4de..1f6d9f5ae1ed 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -282,7 +282,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* PLIC */
- s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
+ s->plic = sifive_plic_create(system_memory,
+ memmap[MICROCHIP_PFSOC_PLIC].base,
plic_hart_config, ms->smp.cpus, 0,
MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 86ff8f8fcaab..62052bf7c61e 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -115,7 +115,8 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
- sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+ sss->plic = sifive_plic_create(system_memory,
+ shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
SHAKTI_C_PLIC_NUM_SOURCES,
SHAKTI_C_PLIC_NUM_PRIORITIES,
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 0ea444f43bc5..81d7995ddcfb 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -214,7 +214,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
+ s->plic = sifive_plic_create(sys_mem, memmap[SIFIVE_E_DEV_PLIC].base,
(char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
SIFIVE_E_PLIC_NUM_SOURCES,
SIFIVE_E_PLIC_NUM_PRIORITIES,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6bbf2c4504d8..632194a06ea1 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -774,7 +774,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
+ s->plic = sifive_plic_create(system_memory,
+ memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config, ms->smp.cpus, 0,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 8fd742181e28..a7b5af4e4c88 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -561,6 +561,7 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
/* Per-socket PLIC */
return sifive_plic_create(
+ get_system_memory(),
memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
plic_hart_config, hart_count, base_hartid,
VIRT_IRQCHIP_NUM_SOURCES,
--
2.47.3
next prev parent reply other threads:[~2026-09-03 5:53 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 5:51 [PATCH v3 00/16] hw/riscv: Socify Atlantis Joel Stanley
2026-09-03 5:51 ` [PATCH v3 01/16] hw/riscv/aia: Take a MemoryRegion for the created devices Joel Stanley
2026-09-03 6:06 ` Chao Liu via
2026-09-03 6:06 ` Chao Liu via qemu development
2026-09-03 5:51 ` [PATCH v3 02/16] hw/intc/riscv_aclint: " Joel Stanley
2026-09-03 5:51 ` [PATCH v3 03/16] hw/intc/riscv_imsic: Take a MemoryRegion for the created device Joel Stanley
2026-09-03 5:51 ` [PATCH v3 04/16] hw/intc/riscv_aplic: " Joel Stanley
2026-09-03 5:51 ` Joel Stanley [this message]
2026-09-03 6:07 ` [PATCH v3 05/16] hw/intc/sifive_plic: " Chao Liu via qemu development
2026-09-03 6:07 ` Chao Liu via
2026-09-03 5:51 ` [PATCH v3 06/16] hw/riscv/cps: Map interrupt controllers in SoC container Joel Stanley
2026-09-03 5:51 ` [PATCH v3 07/16] hw/riscv/atlantis: Make UART unimp region a SoC device Joel Stanley
2026-09-03 5:51 ` [PATCH v3 08/16] hw/riscv/atlantis: Remove unused fdt_size Joel Stanley
2026-09-03 5:51 ` [PATCH v3 09/16] hw/riscv/atlantis: Rename hart array 'soc' to 'cpus' Joel Stanley
2026-09-03 5:51 ` [PATCH v3 10/16] hw/riscv/atlantis: Rework device tree creation Joel Stanley
2026-09-03 5:51 ` [PATCH v3 11/16] hw/riscv/atlantis: Use local reference for system memory Joel Stanley
2026-09-03 5:51 ` [PATCH v3 12/16] hw/riscv/atlantis: Decouple RAM size from MachineState Joel Stanley
2026-09-03 5:51 ` [PATCH v3 13/16] hw/riscv/atlantis: Make TTAtlantisState own memory containers Joel Stanley
2026-09-03 5:51 ` [PATCH v3 14/16] hw/riscv: Add property to hart array to allow private memory Joel Stanley
2026-09-04 10:42 ` Philippe Mathieu-Daudé
2026-09-07 7:27 ` Joel Stanley
2026-09-03 5:51 ` [PATCH v3 15/16] hw/riscv/atlantis: Extract an Atlantis SoC device Joel Stanley
2026-09-04 10:47 ` Philippe Mathieu-Daudé
2026-09-04 10:48 ` Philippe Mathieu-Daudé
2026-09-07 7:16 ` Joel Stanley
2026-09-03 5:51 ` [PATCH v3 16/16] hw/riscv/atlantis: Map the SoC through a memory container Joel Stanley
2026-09-03 23:35 ` [PATCH v3 00/16] hw/riscv: Socify Atlantis Alistair Francis
2026-09-04 10:49 ` Philippe Mathieu-Daudé
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