From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Brian Cain" <brian.cain@oss.qualcomm.com>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH 5/8] target/hexagon: assert guest register pair alignment
Date: Thu, 3 Sep 2026 11:56:19 -0700 [thread overview]
Message-ID: <20260903185622.3234171-6-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260903185622.3234171-1-brian.cain@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/f7f34a43-c1cc-4dd8-a859-9ab72e1b015f@oss.qualcomm.com/
Suggested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/op_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 5d64c5523bb..7ad99ced7ab 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -1927,6 +1927,8 @@ uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg)
uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
{
+ g_assert((reg & 1) == 0);
+
if (reg == HEX_GREG_G0 || reg == HEX_GREG_G2) {
return (uint64_t)(env->greg[reg]) |
(((uint64_t)(env->greg[reg + 1])) << 32);
--
2.34.1
next prev parent reply other threads:[~2026-09-03 18:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 18:56 [PATCH 0/8] hexagon: fixes for tlb, badva Brian Cain
2026-09-03 18:56 ` [PATCH 1/8] hw/hexagon: register the V68N_1024 machine Brian Cain
2026-09-03 19:36 ` Pierrick Bouvier
2026-09-03 18:56 ` [PATCH 2/8] target/hexagon: read BADVA as an alias of BADVA0/1 Brian Cain
2026-09-03 19:36 ` Pierrick Bouvier
2026-09-03 18:56 ` [PATCH 3/8] target/hexagon: kick vCPU when re-asserting interrupts Brian Cain
2026-09-03 19:36 ` Pierrick Bouvier
2026-09-04 13:30 ` Philippe Mathieu-Daudé
2026-09-03 18:56 ` [PATCH 4/8] hw/intc: name the L2VIC edge trigger check Brian Cain
2026-09-03 19:37 ` Pierrick Bouvier
2026-09-04 13:31 ` Philippe Mathieu-Daudé
2026-09-03 18:56 ` Brian Cain [this message]
2026-09-03 19:37 ` [PATCH 5/8] target/hexagon: assert guest register pair alignment Pierrick Bouvier
2026-09-04 13:32 ` Philippe Mathieu-Daudé
2026-09-03 18:56 ` [PATCH 6/8] hexagon: raise imprecise exception for multi-TLB matches Brian Cain
2026-09-03 19:37 ` Pierrick Bouvier
2026-09-03 18:56 ` [PATCH 7/8] tests/functional/hexagon: add tests, update to v0.2.14 Brian Cain
2026-09-03 19:38 ` Pierrick Bouvier
2026-09-03 18:56 ` [PATCH 8/8] tests/functional/hexagon: update arch tests " Brian Cain
2026-09-03 19:38 ` Pierrick Bouvier
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