Re: [PATCH 6/8] hexagon: raise imprecise exception for multi-TLB matches

[Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>]

On 9/3/2026 11:56 AM, Brian Cain wrote:
> The TLB walk stopped at the first matching entry, so instruction and data
> translations did not detect a second valid mapping for the same VA and ASID.
> 
> Scan the remaining entries after selecting the translation.  On a second
> match, retain the first entry for the access but record
> HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH as a pending imprecise exception.
> 
> Move that exception out of the synchronous TLB-fill result and check for it
> after every packet, rather than only packets containing tlbp.  This delivers
> the architectural imprecise exception after an ordinary memory access and
> avoids treating it as a precise permission fault.  Clear the pending state
> when starting a new translation and after delivering the exception.
> 
> The v0.2.14 mmu_multi_tlb systest uncovered this bug.
> 
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>  hw/hexagon/hexagon_tlb.c   | 10 ++++++++++
>  target/hexagon/hex_mmu.c   | 12 +++++++++---
>  target/hexagon/hexswi.c    |  1 +
>  target/hexagon/translate.c | 22 ++++++++--------------
>  4 files changed, 28 insertions(+), 17 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>