Re: [PATCH v6 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Missing Context Synchronization Event (isb) after writing to ICC_CR0_EL1 and other ICC_*_EL1 registers.
--

commit 361cdcbfff4bc37ad48869321f633c176369b8d6
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields

This commit adds the missing LINK and LINK_IDLE fields to the
ICC_CR0_EL1 register definition in the arm64 sysreg generator.

> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 94bf065c8ac71..e2d37ee221b84 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -3761,7 +3761,9 @@ Sysreg	ICC_CR0_EL1	3	1	12	0	1
>  Res0	63:39
>  Field	38	PID
>  Field	37:32	IPPT
> -Res0	31:1
> +Res0	31:3
> +Field	2	LINK_IDLE
> +Field	1	LINK
>  Field	0	EN
>  EndSysreg

[Severity: High]
This isn't a bug introduced by this patch, but while looking at
ICC_CR0_EL1, it appears there might be a pre-existing missing Context
Synchronization Event (isb) when writing to this register elsewhere in
the tree.

In drivers/irqchip/irq-gic-v5.c, gicv5_cpu_enable_interrupts() writes to
SYS_ICC_CR0_EL1 to enable interrupts but returns without an isb():

    cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 1);
    write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
}

The same pattern exists in the selftests
(tools/testing/selftests/kvm/include/arm64/gic_v5.h) for both enabling and
disabling:

gicv5_cpu_disable_interrupts()
...
    cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0);
    write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
}

Architectural guidelines mandate that writes to most ICC_*_EL1 registers
require an isb() to be visible to subsequent instructions. Without this,
could the CPU proceed under a stale interrupt configuration, potentially
missing interrupts?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904113404.4051341-1-sascha.bischoff@arm.com?part=6