From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: "Marc Zyngier" <maz@kernel.org>,
kvmarm@lists.linux.dev, kvm@vger.kernel.org,
"Oliver Upton" <oupton@kernel.org>
Subject: Re: [PATCH v6 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain
Date: Fri, 04 Sep 2026 12:26:15 +0000 [thread overview]
Message-ID: <20260904122616.4FC971F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904113404.4051341-9-sascha.bischoff@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [Critical] Concurrent VCPU creation during vGIC initialization causes under-allocation of resources leading to out-of-bounds access.
--
commit e10bd8258f90674edeba15cbc5bdb3a9de97b8ef
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
KVM: arm64: gic-v5: Add VPE doorbell domain
This commit adds support for a per-VM VPE doorbell irq domain for GICv5.
It creates one doorbell per VPE under the GICv5 LPI domain and populates
the doorbell IRQ number in the GICv5 CPU interface state.
> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index e75a66b3920aa..60bb39421ad08 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
[ ... ]
> @@ -125,6 +126,137 @@ int vgic_v5_probe(const struct gic_kvm_info *info)
[ ... ]
> +static int vgic_v5_create_per_vm_domain(struct kvm *kvm)
> +{
> + struct vgic_v5_vm *vm = &kvm->arch.vgic.gicv5_vm;
> + int nr_vcpus = atomic_read(&kvm->online_vcpus);
> + int id = task_pid_nr(current);
> + int ret, db_virq = 0;
> +
> + if (!gicv5_global_data.lpi_domain) {
> + kvm_err("LPI domain uninitialized, can't set up KVM Doorbells\n");
> + return -ENODEV;
> + }
> +
> + vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv5-vpe-db", id);
> + if (!vm->fwnode)
> + return -ENOMEM;
> +
> + /*
> + * KVM per-VM VPE DB domain; child of LPI domain; only ever handles
> + * doorbells. We know how many doorbells we have, and therefore we
> + * create a linear domain.
> + */
> + vm->domain = irq_domain_create_hierarchy(gicv5_global_data.lpi_domain,
> + 0, nr_vcpus, vm->fwnode,
> + &vgic_v5_irq_db_domain_ops, vm);
> + if (!vm->domain) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + db_virq = irq_domain_alloc_irqs(vm->domain, nr_vcpus, NUMA_NO_NODE, vm);
[Severity: Critical]
This is a pre-existing issue, but does this allocation race with concurrent
VCPU creation, leading to an under-sized doorbell domain and potential
out-of-bounds access?
Looking at vgic_init() in arch/arm64/kvm/vgic/vgic-init.c, it guards against
ongoing VCPU creation with a lockless check:
if (kvm->created_vcpus != atomic_read(&kvm->online_vcpus))
return -EBUSY;
If Thread 1 calls KVM_CREATE_VCPU and acquires kvm->lock, Thread 2 could
concurrently call KVM_DEV_ARM_VGIC_CTRL_INIT and acquire config_lock.
If Thread 2 evaluates the lockless check in vgic_init() before Thread 1
increments created_vcpus, Thread 2 proceeds to allocate resources sized to
the current online_vcpus count here in vgic_v5_create_per_vm_domain().
Once Thread 1 finishes creating its VCPU and increments online_vcpus, later
accesses by the new VCPU might exceed the allocated doorbell array bounds.
While this problem already affected GICv4 VPE allocation, this patch
introduces a new vulnerable allocation for GICv5 doorbell IRQs.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260904113404.4051341-1-sascha.bischoff@arm.com?part=8
next prev parent reply other threads:[~2026-09-04 12:26 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 11:34 [PATCH v6 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-09-04 11:34 ` [PATCH v6 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-09-04 12:07 ` sashiko-bot
2026-09-04 12:16 ` Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-09-04 12:14 ` sashiko-bot
2026-09-04 12:21 ` Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-09-04 12:25 ` sashiko-bot
2026-09-04 12:37 ` Sascha Bischoff
2026-09-04 11:38 ` [PATCH v6 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-09-04 12:26 ` sashiko-bot [this message]
2026-09-04 11:38 ` [PATCH v6 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-09-04 12:24 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-09-04 12:30 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-09-04 12:39 ` sashiko-bot
2026-09-04 11:40 ` [PATCH v6 12/49] KVM: arm64: vgic: Enforce model-specific vCPU limits Sascha Bischoff
2026-09-04 11:40 ` [PATCH v6 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-09-04 12:36 ` sashiko-bot
2026-09-04 11:41 ` [PATCH v6 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-09-04 12:50 ` sashiko-bot
2026-09-04 11:41 ` [PATCH v6 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-09-04 12:42 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-09-04 13:08 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-09-04 11:44 ` [PATCH v6 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-09-04 12:59 ` sashiko-bot
2026-09-04 11:44 ` [PATCH v6 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-09-04 13:00 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-09-04 13:10 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-09-04 13:05 ` sashiko-bot
2026-09-04 11:46 ` [PATCH v6 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-09-04 11:46 ` [PATCH v6 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-09-04 11:48 ` [PATCH v6 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-09-04 13:25 ` sashiko-bot
2026-09-04 11:49 ` [PATCH v6 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-09-04 11:49 ` [PATCH v6 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-09-04 11:50 ` [PATCH v6 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-09-04 13:27 ` sashiko-bot
2026-09-04 11:50 ` [PATCH v6 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-09-04 13:34 ` sashiko-bot
2026-09-04 11:51 ` [PATCH v6 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-09-04 11:51 ` [PATCH v6 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-09-04 11:52 ` [PATCH v6 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-09-04 13:45 ` sashiko-bot
2026-09-04 11:52 ` [PATCH v6 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-09-04 11:58 ` [PATCH v6 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-09-04 13:56 ` sashiko-bot
2026-09-04 11:58 ` [PATCH v6 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-09-04 13:58 ` sashiko-bot
2026-09-04 11:59 ` [PATCH v6 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
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