From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org, richard.henderson@linaro.org,
peter.maydell@linaro.org
Cc: brian.cain@oss.qualcomm.com
Subject: [PULL 0/9] hex queue
Date: Sat, 5 Sep 2026 13:05:41 -0700 [thread overview]
Message-ID: <20260905200550.2009799-1-brian.cain@oss.qualcomm.com> (raw)
The following changes since commit ff1d2d19d7e24893e2012d879f8e73077e17b9bd:
Merge tag 'pull-11.1-check-tcg-meson-040926-2' of https://gitlab.com/stsquad/qemu into staging (2026-09-04 16:52:58 +0100)
are available in the Git repository at:
https://github.com/qualcomm/qemu tags/pull-hex-20260905
for you to fetch changes up to dfad6f9ff1a4600893ef6b3c21382225e604535e:
target/hexagon: decode the DMA insts as unimp (2026-09-05 12:04:01 -0700)
----------------------------------------------------------------
hexagon: TLB, badva fixes + DMA
Add fixes for TLB, badva behavior and an unimp placeholder for the
DMA instruction set.
----------------------------------------------------------------
Brian Cain (9):
hw/hexagon: register the V68N_1024 machine
target/hexagon: read BADVA as an alias of BADVA0/1
target/hexagon: kick vCPU when re-asserting interrupts
hw/intc: name the L2VIC edge trigger check
target/hexagon: assert guest register pair alignment
hexagon: raise imprecise exception for multi-TLB matches
tests/functional/hexagon: add tests, update to v0.2.14
tests/functional/hexagon: update arch tests to v0.2.14
target/hexagon: decode the DMA insts as unimp
target/hexagon/gen_tcg.h | 28 ++++++++++++++++++++++++++++
hw/hexagon/hexagon_dsp.c | 23 +++++++++++++++++++++++
hw/hexagon/hexagon_tlb.c | 10 ++++++++++
hw/intc/hex-l2vic.c | 13 +++++++++----
target/hexagon/genptr.c | 1 +
target/hexagon/hex_interrupts.c | 2 +-
target/hexagon/hex_mmu.c | 12 +++++++++---
target/hexagon/hexswi.c | 1 +
target/hexagon/op_helper.c | 9 +++++++++
target/hexagon/translate.c | 22 ++++++++--------------
target/hexagon/tag_rev_info.c.inc | 10 ++++++++++
target/hexagon/imported/encode_pp.def | 11 +++++++++++
target/hexagon/imported/system.idef | 11 +++++++++++
tests/functional/hexagon/test_arch_tests.py | 6 +++---
tests/functional/hexagon/test_systests.py | 17 +++++++++++++----
15 files changed, 147 insertions(+), 29 deletions(-)
next reply other threads:[~2026-09-05 20:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-05 20:05 Brian Cain [this message]
2026-09-05 20:05 ` [PULL 1/9] hw/hexagon: register the V68N_1024 machine Brian Cain
2026-09-05 20:05 ` [PULL 2/9] target/hexagon: read BADVA as an alias of BADVA0/1 Brian Cain
2026-09-05 20:05 ` [PULL 3/9] target/hexagon: kick vCPU when re-asserting interrupts Brian Cain
2026-09-05 20:05 ` [PULL 4/9] hw/intc: name the L2VIC edge trigger check Brian Cain
2026-09-05 20:05 ` [PULL 5/9] target/hexagon: assert guest register pair alignment Brian Cain
2026-09-05 20:05 ` [PULL 6/9] hexagon: raise imprecise exception for multi-TLB matches Brian Cain
2026-09-05 20:05 ` [PULL 7/9] tests/functional/hexagon: add tests, update to v0.2.14 Brian Cain
2026-09-05 20:05 ` [PULL 8/9] tests/functional/hexagon: update arch tests " Brian Cain
2026-09-05 20:05 ` [PULL 9/9] target/hexagon: decode the DMA insts as unimp Brian Cain
2026-09-07 12:32 ` [PULL 0/9] hex queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2026-04-24 2:35 Brian Cain
2026-04-25 16:59 ` Stefan Hajnoczi
2026-01-02 20:11 Brian Cain
2026-01-04 21:54 ` Richard Henderson
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