From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org, richard.henderson@linaro.org,
peter.maydell@linaro.org
Cc: brian.cain@oss.qualcomm.com,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PULL 7/9] tests/functional/hexagon: add tests, update to v0.2.14
Date: Sat, 5 Sep 2026 13:05:48 -0700 [thread overview]
Message-ID: <20260905200550.2009799-8-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260905200550.2009799-1-brian.cain@oss.qualcomm.com>
Add tests for direct-to-guest interrupts, multi-TLB match case, {u,}timer
registers.
Update to the v0.2.14 tests and switch to the new 'sim' machine name.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
tests/functional/hexagon/test_systests.py | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/tests/functional/hexagon/test_systests.py b/tests/functional/hexagon/test_systests.py
index f36e015f502..983ee1672ce 100755
--- a/tests/functional/hexagon/test_systests.py
+++ b/tests/functional/hexagon/test_systests.py
@@ -21,8 +21,8 @@ class SysTestsStandaloneTests(QemuSystemTest):
SYSTEST_TIMEOUT_SEC = 30
ASSET_TARBALL = Asset(
- "https://github.com/qualcomm/qemu-hexagon-testing/releases/download/v0.2.11/systests_standalone.tar.gz",
- "b5777aa65245de7710a7a08d717953c1362be7c8b60d9014c9fee8b17610ad1c",
+ "https://github.com/qualcomm/qemu-hexagon-testing/releases/download/v0.2.14/systests_standalone.tar.gz",
+ "f0c535d746384126954757b6ce54452c5fe82624618c79862495eec24718a6ff",
)
def setUp(self):
@@ -34,7 +34,7 @@ def binary(self, name):
self.assertTrue(os.path.exists(path))
return path
- def run_exit_zero(self, binary_name, *extra_args, machine="V66G_1024"):
+ def run_exit_zero(self, binary_name, *extra_args, machine="sim"):
self.set_machine(machine)
self.set_vm_arg("-display", "none")
self.set_vm_arg("-kernel", self.binary(binary_name))
@@ -47,7 +47,7 @@ def run_exit_zero(self, binary_name, *extra_args, machine="V66G_1024"):
f"code {self.vm.exitcode()}, expected 0")
def run_console_pattern(self, binary_name, pattern, *extra_args,
- machine="V66G_1024"):
+ machine="sim"):
self.set_machine(machine)
self.set_vm_arg("-display", "none")
self.set_vm_arg("-kernel", self.binary(binary_name))
@@ -90,5 +90,14 @@ def test_access(self):
def test_semihost(self):
self.run_console_pattern("semihost", "PASS", "-append", "arg1", "arg2")
+ def test_dtg_interrupt(self):
+ self.run_exit_zero("dtg_interrupt")
+
+ def test_mmu_multi_tlb(self):
+ self.run_exit_zero("mmu_multi_tlb")
+
+ def test_timer_reg(self):
+ self.run_exit_zero("timer_reg")
+
if __name__ == "__main__":
QemuSystemTest.main()
--
2.34.1
next prev parent reply other threads:[~2026-09-05 20:06 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-05 20:05 [PULL 0/9] hex queue Brian Cain
2026-09-05 20:05 ` [PULL 1/9] hw/hexagon: register the V68N_1024 machine Brian Cain
2026-09-05 20:05 ` [PULL 2/9] target/hexagon: read BADVA as an alias of BADVA0/1 Brian Cain
2026-09-05 20:05 ` [PULL 3/9] target/hexagon: kick vCPU when re-asserting interrupts Brian Cain
2026-09-05 20:05 ` [PULL 4/9] hw/intc: name the L2VIC edge trigger check Brian Cain
2026-09-05 20:05 ` [PULL 5/9] target/hexagon: assert guest register pair alignment Brian Cain
2026-09-05 20:05 ` [PULL 6/9] hexagon: raise imprecise exception for multi-TLB matches Brian Cain
2026-09-05 20:05 ` Brian Cain [this message]
2026-09-05 20:05 ` [PULL 8/9] tests/functional/hexagon: update arch tests to v0.2.14 Brian Cain
2026-09-05 20:05 ` [PULL 9/9] target/hexagon: decode the DMA insts as unimp Brian Cain
2026-09-07 12:32 ` [PULL 0/9] hex queue Peter Maydell
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