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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org, richard.henderson@linaro.org,
	peter.maydell@linaro.org
Cc: brian.cain@oss.qualcomm.com,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PULL 3/9] target/hexagon: kick vCPU when re-asserting interrupts
Date: Sat,  5 Sep 2026 13:05:44 -0700	[thread overview]
Message-ID: <20260905200550.2009799-4-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260905200550.2009799-1-brian.cain@oss.qualcomm.com>

hex_interrupt_update() used cpu_resume() to make a halted vCPU notice a
newly pending interrupt.  cpu_resume() is meant for a vCPU stopped by the
vm-state machinery: besides kicking the thread it clears cpu->stop and
cpu->stopped, and resets exception_index to -1.  Clearing the stop flags
can undo a pause requested via the monitor or by migration, and resetting
exception_index discards an exception the vCPU had already latched.

Only the kick is wanted here, so call qemu_cpu_kick() directly.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/hex_interrupts.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupts.c
index 7dde1294b2e..2b2834af95f 100644
--- a/target/hexagon/hex_interrupts.c
+++ b/target/hexagon/hex_interrupts.c
@@ -441,7 +441,7 @@ void hex_interrupt_update(CPUHexagonState *env)
             const int exe_mode = get_exe_mode(hex_env);
             if (exe_mode != HEX_EXE_MODE_OFF) {
                 cpu_interrupt(cs, CPU_INTERRUPT_SWI);
-                cpu_resume(cs);
+                qemu_cpu_kick(cs);
             }
         }
     }
-- 
2.34.1


  parent reply	other threads:[~2026-09-05 20:07 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-05 20:05 [PULL 0/9] hex queue Brian Cain
2026-09-05 20:05 ` [PULL 1/9] hw/hexagon: register the V68N_1024 machine Brian Cain
2026-09-05 20:05 ` [PULL 2/9] target/hexagon: read BADVA as an alias of BADVA0/1 Brian Cain
2026-09-05 20:05 ` Brian Cain [this message]
2026-09-05 20:05 ` [PULL 4/9] hw/intc: name the L2VIC edge trigger check Brian Cain
2026-09-05 20:05 ` [PULL 5/9] target/hexagon: assert guest register pair alignment Brian Cain
2026-09-05 20:05 ` [PULL 6/9] hexagon: raise imprecise exception for multi-TLB matches Brian Cain
2026-09-05 20:05 ` [PULL 7/9] tests/functional/hexagon: add tests, update to v0.2.14 Brian Cain
2026-09-05 20:05 ` [PULL 8/9] tests/functional/hexagon: update arch tests " Brian Cain
2026-09-05 20:05 ` [PULL 9/9] target/hexagon: decode the DMA insts as unimp Brian Cain
2026-09-07 12:32 ` [PULL 0/9] hex queue Peter Maydell

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