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From: Inochi Amaoto <inochiama@gmail.com>
To: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Yixun Lan" <dlan@kernel.org>, "Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>, "Frank Li" <Frank.Li@nxp.com>,
	"Niklas Cassel" <cassel@kernel.org>,
	"Sherry Sun" <sherry.sun@nxp.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Christian Bruel" <christian.bruel@foss.st.com>,
	"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Senchuan Zhang" <zhangsenchuan@eswincomputing.com>,
	"Inochi Amaoto" <inochiama@gmail.com>,
	"Alex Elder" <elder@riscstar.com>,
	"Xincheng Zhang" <zhangxincheng@ultrarisc.com>,
	"Randolph Lin" <randolph@andestech.com>,
	"Siddharth Vadapalli" <s-vadapalli@ti.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Vidya Sagar" <vidyas@nvidia.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Danilo Krummrich" <dakr@kernel.org>,
	"Uwe Kleine-König (The Capable Hub)"
	<u.kleine-koenig@baylibre.com>,
	"Pengpeng Hou" <pengpeng@iscas.ac.cn>,
	"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, Yixun Lan <dlan@gentoo.org>,
	Longbin Li <looong.bin@gmail.com>
Subject: [PATCH v5 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller
Date: Mon,  7 Sep 2026 19:26:04 +0800	[thread overview]
Message-ID: <20260907112606.465778-6-inochiama@gmail.com> (raw)
In-Reply-To: <20260907112606.465778-1-inochiama@gmail.com>

Add binding support for the PCIe controller on the SpacemiT K3 SoC.
This controller is almost a standard Synopsys DesignWare PCIe IP,
with some extra link and reset state control.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 .../bindings/pci/spacemit,k1-pcie-host.yaml   | 50 ++++++++++++++++---
 1 file changed, 43 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
index c4c00b5fcdc0..54817d6fd9af 100644
--- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
@@ -14,26 +14,29 @@ description: >
   PCIe IP.  The controller uses the DesignWare built-in MSI interrupt
   controller, and supports 256 MSIs.
 
-allOf:
-  - $ref: /schemas/pci/snps,dw-pcie.yaml#
-
 properties:
   compatible:
-    const: spacemit,k1-pcie
+    enum:
+      - spacemit,k1-pcie
+      - spacemit,k3-pcie
 
   reg:
+    minItems: 4
     items:
       - description: DesignWare PCIe registers
       - description: ATU address space
       - description: PCIe configuration space
       - description: Link control registers
+      - description: Data Bus Interface (DBI) shadow registers.
 
   reg-names:
+    minItems: 4
     items:
       - const: dbi
       - const: atu
       - const: config
       - const: link
+      - const: dbi2
 
   clocks:
     items:
@@ -66,6 +69,8 @@ properties:
   interrupt-names:
     const: msi
 
+  msi-parent: true
+
   spacemit,apmu:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     description:
@@ -84,7 +89,8 @@ patternProperties:
 
     properties:
       phys:
-        maxItems: 1
+        minItems: 1
+        maxItems: 6
 
       vpcie3v3-supply:
         description:
@@ -96,13 +102,43 @@ patternProperties:
 
     unevaluatedProperties: false
 
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: spacemit,k1-pcie
+    then:
+      properties:
+        reg:
+          maxItems: 4
+
+        reg-names:
+          maxItems: 4
+
+      patternProperties:
+        '^pcie@':
+          properties:
+            phys:
+              maxItems: 1
+
+      required:
+        - interrupts
+        - interrupt-names
+    else:
+      properties:
+        reg:
+          minItems: 5
+
+        reg-names:
+          minItems: 5
+
 required:
   - clocks
   - clock-names
   - resets
   - reset-names
-  - interrupts
-  - interrupt-names
   - spacemit,apmu
 
 unevaluatedProperties: false
-- 
2.55.0


WARNING: multiple messages have this Message-ID (diff)
From: Inochi Amaoto <inochiama@gmail.com>
To: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Yixun Lan" <dlan@kernel.org>, "Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>, "Frank Li" <Frank.Li@nxp.com>,
	"Niklas Cassel" <cassel@kernel.org>,
	"Sherry Sun" <sherry.sun@nxp.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Christian Bruel" <christian.bruel@foss.st.com>,
	"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Senchuan Zhang" <zhangsenchuan@eswincomputing.com>,
	"Inochi Amaoto" <inochiama@gmail.com>,
	"Alex Elder" <elder@riscstar.com>,
	"Xincheng Zhang" <zhangxincheng@ultrarisc.com>,
	"Randolph Lin" <randolph@andestech.com>,
	"Siddharth Vadapalli" <s-vadapalli@ti.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Vidya Sagar" <vidyas@nvidia.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Danilo Krummrich" <dakr@kernel.org>,
	"Uwe Kleine-König (The Capable Hub)"
	<u.kleine-koenig@baylibre.com>,
	"Pengpeng Hou" <pengpeng@iscas.ac.cn>,
	"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, Yixun Lan <dlan@gentoo.org>,
	Longbin Li <looong.bin@gmail.com>
Subject: [PATCH v5 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller
Date: Mon,  7 Sep 2026 19:26:04 +0800	[thread overview]
Message-ID: <20260907112606.465778-6-inochiama@gmail.com> (raw)
In-Reply-To: <20260907112606.465778-1-inochiama@gmail.com>

Add binding support for the PCIe controller on the SpacemiT K3 SoC.
This controller is almost a standard Synopsys DesignWare PCIe IP,
with some extra link and reset state control.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 .../bindings/pci/spacemit,k1-pcie-host.yaml   | 50 ++++++++++++++++---
 1 file changed, 43 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
index c4c00b5fcdc0..54817d6fd9af 100644
--- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
@@ -14,26 +14,29 @@ description: >
   PCIe IP.  The controller uses the DesignWare built-in MSI interrupt
   controller, and supports 256 MSIs.
 
-allOf:
-  - $ref: /schemas/pci/snps,dw-pcie.yaml#
-
 properties:
   compatible:
-    const: spacemit,k1-pcie
+    enum:
+      - spacemit,k1-pcie
+      - spacemit,k3-pcie
 
   reg:
+    minItems: 4
     items:
       - description: DesignWare PCIe registers
       - description: ATU address space
       - description: PCIe configuration space
       - description: Link control registers
+      - description: Data Bus Interface (DBI) shadow registers.
 
   reg-names:
+    minItems: 4
     items:
       - const: dbi
       - const: atu
       - const: config
       - const: link
+      - const: dbi2
 
   clocks:
     items:
@@ -66,6 +69,8 @@ properties:
   interrupt-names:
     const: msi
 
+  msi-parent: true
+
   spacemit,apmu:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     description:
@@ -84,7 +89,8 @@ patternProperties:
 
     properties:
       phys:
-        maxItems: 1
+        minItems: 1
+        maxItems: 6
 
       vpcie3v3-supply:
         description:
@@ -96,13 +102,43 @@ patternProperties:
 
     unevaluatedProperties: false
 
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: spacemit,k1-pcie
+    then:
+      properties:
+        reg:
+          maxItems: 4
+
+        reg-names:
+          maxItems: 4
+
+      patternProperties:
+        '^pcie@':
+          properties:
+            phys:
+              maxItems: 1
+
+      required:
+        - interrupts
+        - interrupt-names
+    else:
+      properties:
+        reg:
+          minItems: 5
+
+        reg-names:
+          minItems: 5
+
 required:
   - clocks
   - clock-names
   - resets
   - reset-names
-  - interrupts
-  - interrupt-names
   - spacemit,apmu
 
 unevaluatedProperties: false
-- 
2.55.0


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-09-07 11:26 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-07 11:25 [PATCH v5 0/6] riscv: spacemit: Add PCIe RC controller support for K3 Inochi Amaoto
2026-09-07 11:25 ` Inochi Amaoto
2026-09-07 11:26 ` [PATCH v5 1/6] PCI: spacemit-k1: Add device data support Inochi Amaoto
2026-09-07 11:26   ` Inochi Amaoto
2026-09-07 11:31   ` sashiko-bot
2026-09-08 10:26   ` Andy Shevchenko
2026-09-08 10:26     ` Andy Shevchenko
2026-09-09  8:00     ` Inochi Amaoto
2026-09-09  8:00       ` Inochi Amaoto
2026-09-10  5:44       ` Yao Zi
2026-09-10  5:44         ` Yao Zi
2026-09-10  6:42         ` Andy Shevchenko
2026-09-10  6:42           ` Andy Shevchenko
2026-09-10 12:15           ` Yao Zi
2026-09-10 12:15             ` Yao Zi
2026-09-07 11:26 ` [PATCH v5 2/6] PCI: spacemit-k1: Add multiple PHY handles support Inochi Amaoto
2026-09-07 11:26   ` Inochi Amaoto
2026-09-07 11:37   ` sashiko-bot
2026-09-08 10:29   ` Andy Shevchenko
2026-09-08 10:29     ` Andy Shevchenko
2026-09-09  8:00     ` Inochi Amaoto
2026-09-09  8:00       ` Inochi Amaoto
2026-09-09 14:27       ` Andy Shevchenko
2026-09-09 14:27         ` Andy Shevchenko
2026-09-07 11:26 ` [PATCH v5 3/6] PCI: spacemit-k1: Add device id update helper Inochi Amaoto
2026-09-07 11:26   ` Inochi Amaoto
2026-09-07 11:31   ` sashiko-bot
2026-09-07 11:26 ` [PATCH v5 4/6] dt-bindings: PCI: snps,dw-pcie: Add msi-parent for MSI handle check Inochi Amaoto
2026-09-07 11:26   ` Inochi Amaoto
2026-09-07 11:35   ` sashiko-bot
2026-09-07 11:26 ` Inochi Amaoto [this message]
2026-09-07 11:26   ` [PATCH v5 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Inochi Amaoto
2026-09-07 11:38   ` sashiko-bot
2026-09-07 13:08   ` Troy Mitchell
2026-09-07 13:08     ` Troy Mitchell
2026-09-09  8:01     ` Inochi Amaoto
2026-09-09  8:01       ` Inochi Amaoto
2026-09-07 11:26 ` [PATCH v5 6/6] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support Inochi Amaoto
2026-09-07 11:26   ` Inochi Amaoto
2026-09-07 11:42   ` sashiko-bot
2026-09-07 13:14   ` Troy Mitchell
2026-09-07 13:14     ` Troy Mitchell
2026-09-09  7:51     ` Inochi Amaoto
2026-09-09  7:51       ` Inochi Amaoto
2026-09-10  9:51       ` Troy Mitchell
2026-09-10  9:51         ` Troy Mitchell

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