From: "Timur Kristóf" <timur.kristof@gmail.com>
To: amd-gfx@lists.freedesktop.org, "Marek Olšák" <maraeo@gmail.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Tvrtko Ursulin" <tursulin@ursulin.net>,
pierre-eric.pelloux-prayer@amd.com,
"Natalie Vock" <nat@pixelcluster.dev>,
"Lijo Lazar" <lijo.lazar@amd.com>,
"Felix Kuehling" <Felix.Kuehling@amd.com>
Cc: "Timur Kristóf" <timur.kristof@gmail.com>
Subject: [PATCH 09/12] drm/amdgpu/sdma: Refactor SDMA v3.0 golden registers to be per-instance
Date: Mon, 7 Sep 2026 22:33:13 +0200 [thread overview]
Message-ID: <20260907203316.159103-10-timur.kristof@gmail.com> (raw)
In-Reply-To: <20260907203316.159103-1-timur.kristof@gmail.com>
Refactor golden registers initialization to take the SDMA
engine instance ID as an argument and only program the
golden registers for one SDMA engine at once.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 182 +++++++++++++++++--------
1 file changed, 127 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 3d0f94372e04..4e6fa9db9948 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -76,13 +76,15 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
SDMA1_REGISTER_OFFSET
};
-static const u32 golden_settings_tonga_a11[] =
-{
+static const u32 golden_settings_tonga_a11_sdma0[] = {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+};
+
+static const u32 golden_settings_tonga_a11_sdma1[] = {
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
@@ -90,37 +92,45 @@ static const u32 golden_settings_tonga_a11[] =
mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
};
-static const u32 tonga_mgcg_cgcg_init[] =
-{
+static const u32 tonga_mgcg_cgcg_init_sdma0[] = {
mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
- mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
};
-static const u32 golden_settings_fiji_a10[] =
-{
+static const u32 tonga_mgcg_cgcg_init_sdma1[] = {
+ mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
+};
+
+static const u32 golden_settings_fiji_a10_sdma0[] = {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+};
+
+static const u32 golden_settings_fiji_a10_sdma1[] = {
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
};
-static const u32 fiji_mgcg_cgcg_init[] =
-{
+static const u32 fiji_mgcg_cgcg_init_sdma0[] = {
mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
- mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
};
-static const u32 golden_settings_polaris11_a11[] =
-{
+static const u32 fiji_mgcg_cgcg_init_sdma1[] = {
+ mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
+};
+
+static const u32 golden_settings_polaris11_a11_sdma0[] = {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+};
+
+static const u32 golden_settings_polaris11_a11_sdma1[] = {
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
@@ -128,13 +138,15 @@ static const u32 golden_settings_polaris11_a11[] =
mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
};
-static const u32 golden_settings_polaris10_a11[] =
-{
+static const u32 golden_settings_polaris10_a11_sdma0[] = {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
+};
+
+static const u32 golden_settings_polaris10_a11_sdma1[] = {
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
@@ -142,14 +154,16 @@ static const u32 golden_settings_polaris10_a11[] =
mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
};
-static const u32 cz_golden_settings_a11[] =
-{
+static const u32 cz_golden_settings_a11_sdma0[] = {
mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
+};
+
+static const u32 cz_golden_settings_a11_sdma1[] = {
mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
@@ -158,22 +172,22 @@ static const u32 cz_golden_settings_a11[] =
mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
};
-static const u32 cz_mgcg_cgcg_init[] =
-{
+static const u32 cz_mgcg_cgcg_init_sdma0[] = {
mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
- mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
};
-static const u32 stoney_golden_settings_a11[] =
-{
+static const u32 cz_mgcg_cgcg_init_sdma1[] = {
+ mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
+};
+
+static const u32 stoney_golden_settings_a11_sdma0[] = {
mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
};
-static const u32 stoney_mgcg_cgcg_init[] =
-{
+static const u32 stoney_mgcg_cgcg_init_sdma0[] = {
mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
};
@@ -194,52 +208,110 @@ static const u32 stoney_mgcg_cgcg_init[] =
* buffers.
*/
-static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
+static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev, const u32 instance_id)
{
+ ASSERT(instance_id < adev->sdma.num_instances);
+
switch (adev->asic_type) {
case CHIP_FIJI:
- amdgpu_device_program_register_sequence(adev,
- fiji_mgcg_cgcg_init,
- ARRAY_SIZE(fiji_mgcg_cgcg_init));
- amdgpu_device_program_register_sequence(adev,
- golden_settings_fiji_a10,
- ARRAY_SIZE(golden_settings_fiji_a10));
+ if (instance_id == 0) {
+ amdgpu_device_program_register_sequence(
+ adev,
+ fiji_mgcg_cgcg_init_sdma0,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init_sdma0));
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_fiji_a10_sdma0,
+ ARRAY_SIZE(golden_settings_fiji_a10_sdma0));
+ } else {
+ amdgpu_device_program_register_sequence(
+ adev,
+ fiji_mgcg_cgcg_init_sdma1,
+ ARRAY_SIZE(fiji_mgcg_cgcg_init_sdma1));
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_fiji_a10_sdma1,
+ ARRAY_SIZE(golden_settings_fiji_a10_sdma1));
+ }
break;
case CHIP_TONGA:
- amdgpu_device_program_register_sequence(adev,
- tonga_mgcg_cgcg_init,
- ARRAY_SIZE(tonga_mgcg_cgcg_init));
- amdgpu_device_program_register_sequence(adev,
- golden_settings_tonga_a11,
- ARRAY_SIZE(golden_settings_tonga_a11));
+ if (instance_id == 0) {
+ amdgpu_device_program_register_sequence(
+ adev,
+ tonga_mgcg_cgcg_init_sdma0,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init_sdma0));
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_tonga_a11_sdma0,
+ ARRAY_SIZE(golden_settings_tonga_a11_sdma0));
+ } else {
+ amdgpu_device_program_register_sequence(
+ adev,
+ tonga_mgcg_cgcg_init_sdma1,
+ ARRAY_SIZE(tonga_mgcg_cgcg_init_sdma1));
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_tonga_a11_sdma1,
+ ARRAY_SIZE(golden_settings_tonga_a11_sdma1));
+ }
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- amdgpu_device_program_register_sequence(adev,
- golden_settings_polaris11_a11,
- ARRAY_SIZE(golden_settings_polaris11_a11));
+ if (instance_id == 0) {
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_polaris11_a11_sdma0,
+ ARRAY_SIZE(golden_settings_polaris11_a11_sdma0));
+ } else {
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_polaris11_a11_sdma1,
+ ARRAY_SIZE(golden_settings_polaris11_a11_sdma1));
+ }
break;
case CHIP_POLARIS10:
- amdgpu_device_program_register_sequence(adev,
- golden_settings_polaris10_a11,
- ARRAY_SIZE(golden_settings_polaris10_a11));
+ if (instance_id == 0) {
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_polaris10_a11_sdma0,
+ ARRAY_SIZE(golden_settings_polaris10_a11_sdma0));
+ } else {
+ amdgpu_device_program_register_sequence(
+ adev,
+ golden_settings_polaris10_a11_sdma1,
+ ARRAY_SIZE(golden_settings_polaris10_a11_sdma1));
+ }
break;
case CHIP_CARRIZO:
- amdgpu_device_program_register_sequence(adev,
- cz_mgcg_cgcg_init,
- ARRAY_SIZE(cz_mgcg_cgcg_init));
- amdgpu_device_program_register_sequence(adev,
- cz_golden_settings_a11,
- ARRAY_SIZE(cz_golden_settings_a11));
+ if (instance_id == 0) {
+ amdgpu_device_program_register_sequence(
+ adev,
+ cz_mgcg_cgcg_init_sdma0,
+ ARRAY_SIZE(cz_mgcg_cgcg_init_sdma0));
+ amdgpu_device_program_register_sequence(
+ adev,
+ cz_golden_settings_a11_sdma0,
+ ARRAY_SIZE(cz_golden_settings_a11_sdma0));
+ } else {
+ amdgpu_device_program_register_sequence(
+ adev,
+ cz_mgcg_cgcg_init_sdma1,
+ ARRAY_SIZE(cz_mgcg_cgcg_init_sdma1));
+ amdgpu_device_program_register_sequence(
+ adev,
+ cz_golden_settings_a11_sdma1,
+ ARRAY_SIZE(cz_golden_settings_a11_sdma1));
+ }
break;
case CHIP_STONEY:
+ amdgpu_device_program_register_sequence(
+ adev,
+ stoney_mgcg_cgcg_init_sdma0,
+ ARRAY_SIZE(stoney_mgcg_cgcg_init_sdma0));
amdgpu_device_program_register_sequence(adev,
- stoney_mgcg_cgcg_init,
- ARRAY_SIZE(stoney_mgcg_cgcg_init));
- amdgpu_device_program_register_sequence(adev,
- stoney_golden_settings_a11,
- ARRAY_SIZE(stoney_golden_settings_a11));
+ stoney_golden_settings_a11_sdma0,
+ ARRAY_SIZE(stoney_golden_settings_a11_sdma0));
break;
default:
break;
@@ -745,6 +817,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev, const u32 instance_id)
{
int r;
+ sdma_v3_0_init_golden_registers(adev, instance_id);
+
/* disable sdma engine before programing it */
sdma_v3_0_ctx_switch_enable(adev, instance_id, false);
sdma_v3_0_enable(adev, instance_id, false);
@@ -1162,8 +1236,6 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int i, r;
- sdma_v3_0_init_golden_registers(adev);
-
for (i = 0; i < adev->sdma.num_instances; ++i) {
r = sdma_v3_0_start(adev, i);
if (r)
--
2.55.0
next prev parent reply other threads:[~2026-09-07 20:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 20:33 [PATCH 00/12] RFC: drm/amdgpu/sdma: Refactor SDMA v4 and older functions to be per-instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 01/12] drm/amdgpu/sdma: Refactor SI DMA functions to be per instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 02/12] drm/amdgpu/sdma: Refactor SI DMA clock gating functions to be per-instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 03/12] drm/amdgpu/sdma: Refactor CIK SDMA functions to be per instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 04/12] drm/amdgpu/sdma: Refactor CIK SDMA clock gating functions to be per-instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 05/12] drm/amdgpu/sdma: Refactor SDMA v2.4 functions to be per instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 06/12] drm/amdgpu/sdma: Refactor SDMA v2.4 golden registers to be per-instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 07/12] drm/amdgpu/sdma: Refactor SDMA v3.0 functions to be per instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 08/12] drm/amdgpu/sdma: Refactor SDMA v3.0 clock gating functions to be per-instance Timur Kristóf
2026-09-07 20:33 ` Timur Kristóf [this message]
2026-09-07 20:33 ` [PATCH 10/12] drm/amdgpu/sdma: Refactor SDMA v4.0 functions to be per instance Timur Kristóf
2026-09-08 7:41 ` Tvrtko Ursulin
2026-09-08 8:14 ` Timur Kristóf
2026-09-10 14:44 ` Tvrtko Ursulin
2026-09-07 20:33 ` [PATCH 11/12] drm/amdgpu/sdma: Refactor SDMA v4.0 clock gating functions to be per-instance Timur Kristóf
2026-09-07 20:33 ` [PATCH 12/12] drm/amdgpu/sdma: Refactor SDMA v4.0 golden registers " Timur Kristóf
2026-09-11 19:00 ` [PATCH 00/12] RFC: drm/amdgpu/sdma: Refactor SDMA v4 and older functions " Alex Deucher
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