[PATCH 11/12] drm/amdgpu/sdma: Refactor SDMA v4.0 clock gating functions to be per-instance

["Timur Kristóf" <timur.kristof@gmail.com>]

Refactor clock gating functions to take the SDMA engine
instance ID as an argument and only affect one SDMA engine
instance at once.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 89 ++++++++++++--------------
 1 file changed, 42 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 038e1ee8ff4c..259857596cfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2208,66 +2208,58 @@ static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
 
 static void sdma_v4_0_update_medium_grain_clock_gating(
 		struct amdgpu_device *adev,
-		bool enable)
+		const u32 instance_id,
+		const bool enable)
 {
 	uint32_t data, def;
-	int i;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
-		for (i = 0; i < adev->sdma.num_instances; i++) {
-			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
-			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-			if (def != data)
-				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
-		}
+		def = data = RREG32_SDMA(instance_id, mmSDMA0_CLK_CTRL);
+		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+		if (def != data)
+			WREG32_SDMA(instance_id, mmSDMA0_CLK_CTRL, data);
 	} else {
-		for (i = 0; i < adev->sdma.num_instances; i++) {
-			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
-			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-			if (def != data)
-				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
-		}
+		def = data = RREG32_SDMA(instance_id, mmSDMA0_CLK_CTRL);
+		data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+		if (def != data)
+			WREG32_SDMA(instance_id, mmSDMA0_CLK_CTRL, data);
 	}
 }
 
 
 static void sdma_v4_0_update_medium_grain_light_sleep(
 		struct amdgpu_device *adev,
-		bool enable)
+		const u32 instance_id,
+		const bool enable)
 {
 	uint32_t data, def;
-	int i;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
-		for (i = 0; i < adev->sdma.num_instances; i++) {
-			/* 1-not override: enable sdma mem light sleep */
-			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
-			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-			if (def != data)
-				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
-		}
+		/* 1-not override: enable sdma mem light sleep */
+		def = data = RREG32_SDMA(instance_id, mmSDMA0_POWER_CNTL);
+		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+		if (def != data)
+			WREG32_SDMA(instance_id, mmSDMA0_POWER_CNTL, data);
 	} else {
-		for (i = 0; i < adev->sdma.num_instances; i++) {
 		/* 0-override:disable sdma mem light sleep */
-			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
-			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-			if (def != data)
-				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
-		}
+		def = data = RREG32_SDMA(instance_id, mmSDMA0_POWER_CNTL);
+		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+		if (def != data)
+			WREG32_SDMA(instance_id, mmSDMA0_POWER_CNTL, data);
 	}
 }
 
@@ -2275,14 +2267,17 @@ static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 					  enum amd_clockgating_state state)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int i;
 
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
-	sdma_v4_0_update_medium_grain_clock_gating(adev,
-			state == AMD_CG_STATE_GATE);
-	sdma_v4_0_update_medium_grain_light_sleep(adev,
-			state == AMD_CG_STATE_GATE);
+	for (i = 0; i < adev->sdma.num_instances; i++) {
+		sdma_v4_0_update_medium_grain_clock_gating(
+			adev, i, state == AMD_CG_STATE_GATE);
+		sdma_v4_0_update_medium_grain_light_sleep(
+			adev, i, state == AMD_CG_STATE_GATE);
+	}
 	return 0;
 }
 
-- 
2.55.0