[PATCH 04/12] drm/amdgpu/sdma: Refactor CIK SDMA clock gating functions to be per-instance

["Timur Kristóf" <timur.kristof@gmail.com>]

Refactor clock gating functions to take the SDMA engine
instance ID as an argument and only affect one SDMA engine
instance at once.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 50 ++++++++++-----------------
 1 file changed, 19 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 78fea0621ed9..61ff76fb8fc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -854,51 +854,39 @@ static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 }
 
 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
-				 bool enable)
+				 const u32 instance_id,
+				 const bool enable)
 {
+	const u32 reg_offset = sdma_offsets[instance_id];
 	u32 orig, data;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
-		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
-		WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
+		WREG32(mmSDMA0_CLK_CTRL + reg_offset, 0x00000100);
 	} else {
-		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
-		data |= 0xff000000;
-		if (data != orig)
-			WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
-
-		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
+		orig = data = RREG32(mmSDMA0_CLK_CTRL + reg_offset);
 		data |= 0xff000000;
 		if (data != orig)
-			WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
+			WREG32(mmSDMA0_CLK_CTRL + reg_offset, data);
 	}
 }
 
 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
-				 bool enable)
+				 const u32 instance_id,
+				 const bool enable)
 {
+	const u32 reg_offset = sdma_offsets[instance_id];
 	u32 orig, data;
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
-		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
-		data |= 0x100;
-		if (orig != data)
-			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
-
-		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
+		orig = data = RREG32(mmSDMA0_POWER_CNTL + reg_offset);
 		data |= 0x100;
 		if (orig != data)
-			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
+			WREG32(mmSDMA0_POWER_CNTL + reg_offset, data);
 	} else {
-		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
+		orig = data = RREG32(mmSDMA0_POWER_CNTL + reg_offset);
 		data &= ~0x100;
 		if (orig != data)
-			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
-
-		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
-		data &= ~0x100;
-		if (orig != data)
-			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
+			WREG32(mmSDMA0_POWER_CNTL + reg_offset, data);
 	}
 }
 
@@ -1184,14 +1172,14 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
 static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 					  enum amd_clockgating_state state)
 {
-	bool gate = false;
+	const bool gate = state == AMD_CG_STATE_GATE;
 	struct amdgpu_device *adev = ip_block->adev;
+	int i;
 
-	if (state == AMD_CG_STATE_GATE)
-		gate = true;
-
-	cik_enable_sdma_mgcg(adev, gate);
-	cik_enable_sdma_mgls(adev, gate);
+	for (i = 0; i < adev->sdma.num_instances; i++) {
+		cik_enable_sdma_mgcg(adev, i, gate);
+		cik_enable_sdma_mgls(adev, i, gate);
+	}
 
 	return 0;
 }
-- 
2.55.0