From: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
To: platform-driver-x86@vger.kernel.org,
intel-xe@lists.freedesktop.org, hansg@kernel.org,
ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com,
rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com,
airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com,
anoop.c.vijay@intel.com, badal.nilawar@intel.com,
matthew.d.roper@intel.com, james.ausmus@intel.com,
karthik.poosa@intel.com
Subject: [PATCH v8 19/20] drm/xe/vsec: Update PMT internal access
Date: Fri, 11 Sep 2026 13:12:07 -0700 [thread overview]
Message-ID: <20260911201148.1610547-41-michael.j.ruhl@intel.com> (raw)
In-Reply-To: <20260911201148.1610547-22-michael.j.ruhl@intel.com>
Current PMT internal access assumes BMG devices.
Use the new PMT GUID API to read the device specific guid.
Minor cleanup for a newly unused parameter (mmio).
Reviewed-by: Karthik Poosa <karthik.poosa@intel.com>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
---
drivers/gpu/drm/xe/xe_debugfs.c | 26 ++++++++++++++------------
drivers/gpu/drm/xe/xe_hwmon.c | 10 ++++++++--
drivers/gpu/drm/xe/xe_pcode.c | 10 ++++++++--
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 958fb717640a..c56f0e4a9b90 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -5,6 +5,7 @@
#include "xe_debugfs.h"
+#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/debugfs.h>
#include <linux/fault-inject.h>
@@ -21,7 +22,6 @@
#include "xe_gt_printk.h"
#include "xe_guc_ads.h"
#include "xe_hw_engine.h"
-#include "xe_mmio.h"
#include "xe_pagefault.h"
#include "xe_pcode.h"
#include "xe_pm.h"
@@ -146,15 +146,20 @@ static void xe_fault_inject_debugfs_register(struct xe_device *xe,
}
}
-static void read_residency_counter(struct xe_device *xe, struct xe_mmio *mmio,
- u32 offset, const char *name, struct drm_printer *p)
+static void read_residency_counter(struct xe_device *xe, u32 offset, const char *name,
+ struct drm_printer *p)
{
u64 residency = 0;
+ u32 guid;
int ret;
- ret = xe_pmt_telem_read(xe->drm.dev,
- xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
- &residency, offset, sizeof(residency));
+ ret = xe_vsec_get_guid(xe, &guid);
+ if (ret) {
+ drm_warn(&xe->drm, "PMT device is not available: %d\n", ret);
+ return;
+ }
+
+ ret = xe_pmt_telem_read(xe->drm.dev, guid, &residency, offset, sizeof(residency));
if (ret != sizeof(residency)) {
drm_warn(&xe->drm, "%s counter failed to read, ret %d\n", name, ret);
return;
@@ -293,13 +298,12 @@ static int pcode_info(struct seq_file *m, void *data)
static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
{
struct xe_device *xe;
- struct xe_mmio *mmio;
struct drm_printer p;
xe = node_to_xe(m->private);
p = drm_seq_file_printer(m);
guard(xe_pm_runtime)(xe);
- mmio = xe_root_tile_mmio(xe);
+
static const struct {
u32 offset;
const char *name;
@@ -313,7 +317,7 @@ static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
};
for (int i = 0; i < ARRAY_SIZE(residencies); i++)
- read_residency_counter(xe, mmio, residencies[i].offset, residencies[i].name, &p);
+ read_residency_counter(xe, residencies[i].offset, residencies[i].name, &p);
return 0;
}
@@ -321,13 +325,11 @@ static int dgfx_pkg_residencies_show(struct seq_file *m, void *data)
static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data)
{
struct xe_device *xe;
- struct xe_mmio *mmio;
struct drm_printer p;
xe = node_to_xe(m->private);
p = drm_seq_file_printer(m);
guard(xe_pm_runtime)(xe);
- mmio = xe_root_tile_mmio(xe);
static const struct {
u32 offset;
@@ -339,7 +341,7 @@ static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data)
};
for (int i = 0; i < ARRAY_SIZE(residencies); i++)
- read_residency_counter(xe, mmio, residencies[i].offset, residencies[i].name, &p);
+ read_residency_counter(xe, residencies[i].offset, residencies[i].name, &p);
return 0;
}
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 2032066d5f49..57b2fbefa4c3 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -512,9 +512,15 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
if (hwmon->xe->info.platform == XE_BATTLEMAGE) {
u64 pmt_val;
+ u32 guid;
- ret = xe_pmt_telem_read(hwmon->xe->drm.dev,
- xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
+ ret = xe_vsec_get_guid(hwmon->xe, &guid);
+ if (ret) {
+ drm_warn(&hwmon->xe->drm, "PMT device is not available: %d\n", ret);
+ *energy = 0;
+ return;
+ }
+ ret = xe_pmt_telem_read(hwmon->xe->drm.dev, guid,
&pmt_val, BMG_ENERGY_STATUS_PMT_OFFSET, sizeof(pmt_val));
if (ret != sizeof(pmt_val)) {
drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret);
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 8c901e54f384..fa9f45d565cb 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -365,11 +365,17 @@ ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */
int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version)
{
int ret = 0;
+ u32 guid;
guard(xe_pm_runtime)(xe);
- ret = xe_pmt_telem_read(xe->drm.dev,
- xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PUNIT_TELEMETRY_GUID),
+ ret = xe_vsec_get_guid(xe, &guid);
+ if (ret) {
+ xe_warn(xe, "PMT device is not available: %d\n", ret);
+ return ret;
+ }
+
+ ret = xe_pmt_telem_read(xe->drm.dev, guid,
(u64 *)version, PUNIT_VERSION_OFFSET, sizeof(*version));
if (ret != sizeof(*version)) {
xe_warn(xe, "pcode version read from PMT failed, ret %pe\n", ERR_PTR(ret));
--
2.43.0
next prev parent reply other threads:[~2026-09-11 20:12 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 20:11 [PATCH v8 00/20] Crescent Island PMT support Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 01/20] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 02/20] platform/x86/intel/pmt: refactor rmw with a return value Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 03/20] platform/x86/intel/pmt: refactor rc " Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 04/20] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 05/20] platform/x86/intel/pmt: Do not remap when using callbacks Michael J. Ruhl
2026-09-11 20:26 ` sashiko-bot
2026-09-11 20:11 ` [PATCH v8 06/20] drm/xe/vsec: Do not register BMG PMT for VF Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 07/20] drm/xe/vsec: Correct locking order Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 08/20] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 09/20] drm/xe/vsec: Add DOC text for VSEC Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 10/20] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-09-11 20:11 ` [PATCH v8 11/20] drm/xe/vsec: Refactor BattleMage PMT defines Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 12/20] drm/xe/vsec: Update VSEC probe order Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 13/20] drm/xe/vsec: Add base_offset to allow for more flexibilty Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 14/20] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 15/20] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 16/20] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-09-11 20:12 ` [PATCH v8 17/20] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-09-11 20:31 ` sashiko-bot
2026-09-11 20:12 ` [PATCH v8 18/20] drm/xe/vsec: Add PMT GUID internal access Michael J. Ruhl
2026-09-11 20:12 ` Michael J. Ruhl [this message]
2026-09-11 20:12 ` [PATCH v8 20/20] drm/xe/vsec: Refactor platform check Michael J. Ruhl
2026-09-11 20:43 ` ✗ CI.checkpatch: warning for Crescent Island PMT support (rev10) Patchwork
2026-09-11 20:44 ` ✗ CI.KUnit: failure " Patchwork
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