From: Bruce Richardson <bruce.richardson@intel.com>
To: dev@dpdk.org
Cc: Bruce Richardson <bruce.richardson@intel.com>,
Ciara Loftus <ciara.loftus@intel.com>,
Vladimir Medvedkin <vladimir.medvedkin@intel.com>
Subject: [PATCH v2 10/15] net/intel: move vector Tx paths to common
Date: Tue, 15 Sep 2026 14:36:47 +0100 [thread overview]
Message-ID: <20260915133654.278780-11-bruce.richardson@intel.com> (raw)
In-Reply-To: <20260915133654.278780-1-bruce.richardson@intel.com>
The main loops for vector Tx, both avx2 and avx512 are almost identical
across a couple of drivers, so move the iavf copies to common for later
reuse by other drivers.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Ciara Loftus <ciara.loftus@intel.com>
---
drivers/net/intel/common/tx.h | 10 ++
drivers/net/intel/common/tx_vec_x86.h | 128 ++++++++++++++++++
drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c | 75 +---------
drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c | 77 +----------
4 files changed, 148 insertions(+), 142 deletions(-)
diff --git a/drivers/net/intel/common/tx.h b/drivers/net/intel/common/tx.h
index c8fadee712..630df8cb19 100644
--- a/drivers/net/intel/common/tx.h
+++ b/drivers/net/intel/common/tx.h
@@ -9,6 +9,8 @@
#include <rte_mbuf.h>
#include <rte_ethdev.h>
#include <rte_vect.h>
+#include <rte_io.h>
+#include <rte_byteorder.h>
/* Common TX Descriptor QW1 Field Definitions */
#define CI_TXD_QW1_DTYPE_S 0
@@ -273,6 +275,14 @@ ci_tx_backlog_entry_vec(struct ci_tx_entry_vec *txep, struct rte_mbuf **tx_pkts,
txep[i].mbuf = tx_pkts[i];
}
+
+/* Write the Tx tail register, byte-swapped for hardware regardless of host endianness. */
+static __rte_always_inline void
+ci_tx_qtx_tail_write(struct ci_tx_queue *txq, uint16_t tx_id)
+{
+ rte_write32_wc(rte_cpu_to_le_32((uint32_t)tx_id), txq->qtx_tail);
+}
+
#define IETH_VPMD_TX_MAX_FREE_BUF 64
typedef int (*ci_desc_done_fn)(struct ci_tx_queue *txq, uint16_t idx);
diff --git a/drivers/net/intel/common/tx_vec_x86.h b/drivers/net/intel/common/tx_vec_x86.h
index 56efe1d1ec..946dcc1f2e 100644
--- a/drivers/net/intel/common/tx_vec_x86.h
+++ b/drivers/net/intel/common/tx_vec_x86.h
@@ -345,6 +345,69 @@ ci_vtx_ctx_avx2(volatile struct ci_tx_desc *txdp,
single_vlan_pos, qinq_outer_pos, lldp_check);
}
+static __rte_always_inline uint16_t
+ci_xmit_fixed_burst_vec_avx2(struct ci_tx_queue *txq, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts, bool offload,
+ enum ci_l2tag_pos single_vlan_pos, enum ci_l2tag_pos qinq_outer_pos)
+{
+ volatile struct ci_tx_desc *txdp;
+ struct ci_tx_entry_vec *txep;
+ uint16_t n, nb_commit, tx_id;
+ uint64_t flags = CI_TX_DESC_CMD_DEFAULT;
+ uint64_t rs = CI_TX_DESC_CMD_RS | flags;
+
+ if (txq->nb_tx_free < txq->tx_free_thresh)
+ ci_tx_free_bufs_vec(txq, ci_tx_desc_done_simple, false);
+
+ nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
+ if (unlikely(nb_pkts == 0))
+ return 0;
+ nb_commit = nb_pkts;
+
+ tx_id = txq->tx_tail;
+ txdp = &txq->ci_tx_ring[tx_id];
+ txep = &txq->sw_ring_vec[tx_id];
+
+ txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
+
+ n = (uint16_t)(txq->nb_tx_desc - tx_id);
+ if (nb_commit >= n) {
+ ci_tx_backlog_entry_vec(txep, tx_pkts, n);
+
+ ci_vtx_avx2(txdp, tx_pkts, n - 1, flags, offload, single_vlan_pos, qinq_outer_pos);
+ tx_pkts += (n - 1);
+ txdp += (n - 1);
+
+ ci_vtx1(txdp, *tx_pkts++, rs, offload, single_vlan_pos, qinq_outer_pos);
+
+ nb_commit = (uint16_t)(nb_commit - n);
+
+ tx_id = 0;
+ txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
+
+ /* avoid reach the end of ring */
+ txdp = &txq->ci_tx_ring[tx_id];
+ txep = &txq->sw_ring_vec[tx_id];
+ }
+
+ ci_tx_backlog_entry_vec(txep, tx_pkts, nb_commit);
+
+ ci_vtx_avx2(txdp, tx_pkts, nb_commit, flags, offload, single_vlan_pos, qinq_outer_pos);
+
+ tx_id = (uint16_t)(tx_id + nb_commit);
+ if (tx_id > txq->tx_next_rs) {
+ txq->ci_tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
+ rte_cpu_to_le_64(((uint64_t)CI_TX_DESC_CMD_RS) << CI_TXD_QW1_CMD_S);
+ txq->tx_next_rs = (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
+ }
+
+ txq->tx_tail = tx_id;
+
+ ci_tx_qtx_tail_write(txq, tx_id);
+
+ return nb_pkts;
+}
+
#endif /* __AVX2__ */
#ifdef __AVX512VL__
@@ -512,6 +575,71 @@ ci_vtx_ctx_avx512(volatile struct ci_tx_desc *txdp,
single_vlan_pos, qinq_outer_pos, lldp_check);
}
+static __rte_always_inline uint16_t
+ci_xmit_fixed_burst_vec_avx512(struct ci_tx_queue *txq, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts, bool offload,
+ enum ci_l2tag_pos single_vlan_pos, enum ci_l2tag_pos qinq_outer_pos)
+{
+ volatile struct ci_tx_desc *txdp;
+ struct ci_tx_entry_vec *txep;
+ uint16_t n, nb_commit, tx_id;
+ /* bit2 is reserved and must be set to 1 according to Spec */
+ uint64_t flags = CI_TX_DESC_CMD_DEFAULT;
+ uint64_t rs = CI_TX_DESC_CMD_RS | flags;
+
+ if (txq->nb_tx_free < txq->tx_free_thresh)
+ ci_tx_free_bufs_vec(txq, ci_tx_desc_done_simple, false);
+
+ nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
+ if (unlikely(nb_pkts == 0))
+ return 0;
+ nb_commit = nb_pkts;
+
+ tx_id = txq->tx_tail;
+ txdp = &txq->ci_tx_ring[tx_id];
+ txep = &txq->sw_ring_vec[tx_id];
+
+ txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
+
+ n = (uint16_t)(txq->nb_tx_desc - tx_id);
+ if (nb_commit >= n) {
+ ci_tx_backlog_entry_vec(txep, tx_pkts, n);
+
+ ci_vtx_avx512(txdp, tx_pkts, n - 1, flags, offload,
+ single_vlan_pos, qinq_outer_pos);
+ tx_pkts += (n - 1);
+ txdp += (n - 1);
+
+ ci_vtx1(txdp, *tx_pkts++, rs, offload, single_vlan_pos, qinq_outer_pos);
+
+ nb_commit = (uint16_t)(nb_commit - n);
+
+ tx_id = 0;
+ txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
+
+ /* avoid reach the end of ring */
+ txdp = &txq->ci_tx_ring[tx_id];
+ txep = &txq->sw_ring_vec[tx_id];
+ }
+
+ ci_tx_backlog_entry_vec(txep, tx_pkts, nb_commit);
+
+ ci_vtx_avx512(txdp, tx_pkts, nb_commit, flags, offload, single_vlan_pos, qinq_outer_pos);
+
+ tx_id = (uint16_t)(tx_id + nb_commit);
+ if (tx_id > txq->tx_next_rs) {
+ txq->ci_tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
+ rte_cpu_to_le_64(((uint64_t)CI_TX_DESC_CMD_RS) << CI_TXD_QW1_CMD_S);
+ txq->tx_next_rs = (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
+ }
+
+ txq->tx_tail = tx_id;
+
+ ci_tx_qtx_tail_write(txq, tx_id);
+
+ return nb_pkts;
+}
+
#endif /* __AVX512VL__ */
#endif /* _COMMON_INTEL_TX_VEC_X86_H_ */
diff --git a/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
index 813611015d..1289581038 100644
--- a/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
+++ b/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
@@ -1617,74 +1617,6 @@ iavf_recv_scattered_pkts_vec_avx2_flex_rxd_offload(void *rx_queue,
}
-static __rte_always_inline uint16_t
-iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
- uint16_t nb_pkts, bool offload)
-{
- struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
- volatile struct ci_tx_desc *txdp;
- struct ci_tx_entry_vec *txep;
- uint16_t n, nb_commit, tx_id;
- /* bit2 is reserved and must be set to 1 according to Spec */
- uint64_t flags = CI_TX_DESC_CMD_EOP | CI_TX_DESC_CMD_ICRC;
- uint64_t rs = CI_TX_DESC_CMD_RS | flags;
- /* vlan_flag gives both the single-VLAN and the QinQ outer tag position */
- enum ci_l2tag_pos vlan_pos = (txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) ?
- CI_TAG_IN_DATA_DESC : CI_TAG_IN_CTX_DESC;
-
- if (txq->nb_tx_free < txq->tx_free_thresh)
- ci_tx_free_bufs_vec(txq, iavf_tx_desc_done, false);
-
- nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
- if (unlikely(nb_pkts == 0))
- return 0;
- nb_commit = nb_pkts;
-
- tx_id = txq->tx_tail;
- txdp = &txq->ci_tx_ring[tx_id];
- txep = &txq->sw_ring_vec[tx_id];
-
- txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
-
- n = (uint16_t)(txq->nb_tx_desc - tx_id);
- if (nb_commit >= n) {
- ci_tx_backlog_entry_vec(txep, tx_pkts, n);
-
- ci_vtx_avx2(txdp, tx_pkts, n - 1, flags, offload, vlan_pos, vlan_pos);
- tx_pkts += (n - 1);
- txdp += (n - 1);
-
- ci_vtx1(txdp, *tx_pkts++, rs, offload, vlan_pos, vlan_pos);
-
- nb_commit = (uint16_t)(nb_commit - n);
-
- tx_id = 0;
- txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
-
- /* avoid reach the end of ring */
- txdp = &txq->ci_tx_ring[tx_id];
- txep = &txq->sw_ring_vec[tx_id];
- }
-
- ci_tx_backlog_entry_vec(txep, tx_pkts, nb_commit);
-
- ci_vtx_avx2(txdp, tx_pkts, nb_commit, flags, offload, vlan_pos, vlan_pos);
-
- tx_id = (uint16_t)(tx_id + nb_commit);
- if (tx_id > txq->tx_next_rs) {
- txq->ci_tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
- rte_cpu_to_le_64(((uint64_t)CI_TX_DESC_CMD_RS) << CI_TXD_QW1_CMD_S);
- txq->tx_next_rs =
- (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
- }
-
- txq->tx_tail = tx_id;
-
- IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
-
- return nb_pkts;
-}
-
static __rte_always_inline uint64_t
iavf_tx_ctx_lldp_check(struct rte_mbuf *pkt, uint64_t high_ctx_qw)
{
@@ -1809,14 +1741,17 @@ iavf_xmit_pkts_vec_avx2_common(void *tx_queue, struct rte_mbuf **tx_pkts,
{
uint16_t nb_tx = 0;
struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
+ /* vlan_flag gives both the single-VLAN and the QinQ outer tag position */
+ enum ci_l2tag_pos vlan_pos = (txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) ?
+ CI_TAG_IN_DATA_DESC : CI_TAG_IN_CTX_DESC;
while (nb_pkts) {
uint16_t ret, num;
/* cross rs_thresh boundary is not allowed */
num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
- ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
- num, offload);
+ ret = ci_xmit_fixed_burst_vec_avx2(txq, &tx_pkts[nb_tx], num,
+ offload, vlan_pos, vlan_pos);
nb_tx += ret;
nb_pkts -= ret;
if (ret < num)
diff --git a/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
index fe00416660..9f773f226b 100644
--- a/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
+++ b/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
@@ -1830,76 +1830,6 @@ tx_backlog_entry_avx512(struct ci_tx_entry_vec *txep,
#define IAVF_TX_LEN_MASK 0xAA
#define IAVF_TX_OFF_MASK 0x55
-static __rte_always_inline uint16_t
-iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
- uint16_t nb_pkts, bool offload)
-{
- struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
- volatile struct ci_tx_desc *txdp;
- struct ci_tx_entry_vec *txep;
- uint16_t n, nb_commit, tx_id;
- /* bit2 is reserved and must be set to 1 according to Spec */
- uint64_t flags = CI_TX_DESC_CMD_EOP | CI_TX_DESC_CMD_ICRC;
- uint64_t rs = CI_TX_DESC_CMD_RS | flags;
- /* vlan_flag gives both the single-VLAN and the QinQ outer tag position */
- enum ci_l2tag_pos vlan_pos = (txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) ?
- CI_TAG_IN_DATA_DESC : CI_TAG_IN_CTX_DESC;
-
- if (txq->nb_tx_free < txq->tx_free_thresh)
- ci_tx_free_bufs_vec(txq, iavf_tx_desc_done, false);
-
- nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
- if (unlikely(nb_pkts == 0))
- return 0;
- nb_commit = nb_pkts;
-
- tx_id = txq->tx_tail;
- txdp = &txq->ci_tx_ring[tx_id];
- txep = (void *)txq->sw_ring;
- txep += tx_id;
-
- txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
-
- n = (uint16_t)(txq->nb_tx_desc - tx_id);
- if (nb_commit >= n) {
- tx_backlog_entry_avx512(txep, tx_pkts, n);
-
- ci_vtx_avx512(txdp, tx_pkts, n - 1, flags, offload, vlan_pos, vlan_pos);
- tx_pkts += (n - 1);
- txdp += (n - 1);
-
- ci_vtx1(txdp, *tx_pkts++, rs, offload, vlan_pos, vlan_pos);
-
- nb_commit = (uint16_t)(nb_commit - n);
-
- tx_id = 0;
- txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
-
- /* avoid reach the end of ring */
- txdp = &txq->ci_tx_ring[tx_id];
- txep = (void *)txq->sw_ring;
- txep += tx_id;
- }
-
- tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
-
- ci_vtx_avx512(txdp, tx_pkts, nb_commit, flags, offload, vlan_pos, vlan_pos);
-
- tx_id = (uint16_t)(tx_id + nb_commit);
- if (tx_id > txq->tx_next_rs) {
- txq->ci_tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
- rte_cpu_to_le_64(((uint64_t)CI_TX_DESC_CMD_RS) << CI_TXD_QW1_CMD_S);
- txq->tx_next_rs =
- (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
- }
-
- txq->tx_tail = tx_id;
-
- IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
-
- return nb_pkts;
-}
-
static __rte_always_inline uint64_t
iavf_tx_ctx_lldp_check(struct rte_mbuf *pkt, uint64_t high_ctx_qw)
{
@@ -1985,14 +1915,17 @@ iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
{
uint16_t nb_tx = 0;
struct ci_tx_queue *txq = (struct ci_tx_queue *)tx_queue;
+ /* vlan_flag gives both the single-VLAN and the QinQ outer tag position */
+ enum ci_l2tag_pos vlan_pos = (txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) ?
+ CI_TAG_IN_DATA_DESC : CI_TAG_IN_CTX_DESC;
while (nb_pkts) {
uint16_t ret, num;
/* cross rs_thresh boundary is not allowed */
num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
- ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
- num, offload);
+ ret = ci_xmit_fixed_burst_vec_avx512(txq, &tx_pkts[nb_tx], num,
+ offload, vlan_pos, vlan_pos);
nb_tx += ret;
nb_pkts -= ret;
if (ret < num)
--
2.53.0
next prev parent reply other threads:[~2026-09-15 13:38 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 17:01 [PATCH 00/13] Consolidate ice and iavf vector Tx paths Bruce Richardson
2026-09-03 17:01 ` [PATCH 01/13] net/iavf: remove unnecessary alignment calls Bruce Richardson
2026-09-14 14:20 ` Loftus, Ciara
2026-09-03 17:01 ` [PATCH 02/13] net/intel: make Tx context flag common Bruce Richardson
2026-09-14 14:21 ` Loftus, Ciara
2026-09-03 17:01 ` [PATCH 03/13] net/iavf: use separate params for VLAN and QinQ position Bruce Richardson
2026-09-14 14:24 ` Loftus, Ciara
2026-09-03 17:01 ` [PATCH 04/13] net/iavf: deduplicate tunnel field fill functions Bruce Richardson
2026-09-04 7:01 ` David Marchand
2026-09-03 17:01 ` [PATCH 05/13] net/intel: define common macros for tunneling bit-shifts Bruce Richardson
2026-09-14 14:25 ` Loftus, Ciara
2026-09-03 17:01 ` [PATCH 06/13] net/intel: move iavf descriptor writing functions to common Bruce Richardson
2026-09-14 14:34 ` Loftus, Ciara
2026-09-03 17:01 ` [PATCH 07/13] net/intel: use function callback for lldp Bruce Richardson
2026-09-03 17:01 ` [PATCH 08/13] net/ice: use common descriptor creation functions Bruce Richardson
2026-09-14 14:15 ` Loftus, Ciara
2026-09-14 17:02 ` Bruce Richardson
2026-09-03 17:01 ` [PATCH 09/13] net/intel: move vector Tx paths to common Bruce Richardson
2026-09-14 14:38 ` Loftus, Ciara
2026-09-03 17:03 ` [PATCH 10/13] net/ice: use common AVX Tx functions Bruce Richardson
2026-09-14 14:41 ` Loftus, Ciara
2026-09-03 17:04 ` [PATCH 11/13] net/intel: add common vector Tx fns with context handling Bruce Richardson
2026-09-14 14:57 ` Loftus, Ciara
2026-09-03 17:04 ` [PATCH 12/13] net/intel: improve Tx path selection logic Bruce Richardson
2026-09-14 14:59 ` Loftus, Ciara
2026-09-03 17:04 ` [PATCH 13/13] net/ice: enable context desc offloads for vector Tx Bruce Richardson
2026-09-14 14:18 ` Loftus, Ciara
2026-09-14 16:35 ` Bruce Richardson
2026-09-04 7:10 ` [PATCH 00/13] Consolidate ice and iavf vector Tx paths David Marchand
2026-09-15 13:36 ` [PATCH v2 00/15] consolidate ice and iavf Tx vector paths Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 01/15] net/iavf: remove unnecessary alignment calls Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 02/15] net/intel: make Tx context flag common Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 03/15] net/iavf: use separate params for VLAN and QinQ position Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 04/15] net/iavf: deduplicate tunnel field fill functions Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 05/15] net/intel: define common macros for tunneling bit-shifts Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 06/15] net/intel: move iavf descriptor writing functions to common Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 07/15] net/intel: use function callback for lldp Bruce Richardson
2026-09-16 8:56 ` Loftus, Ciara
2026-09-15 13:36 ` [PATCH v2 08/15] net/intel: allow building without IOVA in mbuf Bruce Richardson
2026-09-16 8:57 ` Loftus, Ciara
2026-09-15 13:36 ` [PATCH v2 09/15] net/ice: use common descriptor creation functions Bruce Richardson
2026-09-16 8:58 ` Loftus, Ciara
2026-09-15 13:36 ` Bruce Richardson [this message]
2026-09-15 13:36 ` [PATCH v2 11/15] net/ice: use common AVX Tx functions Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 12/15] net/intel: add common vector Tx fns with context handling Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 13/15] net/intel: improve Tx path selection logic Bruce Richardson
2026-09-15 13:36 ` [PATCH v2 14/15] net/ice: enable context desc offloads for vector Tx Bruce Richardson
2026-09-16 9:03 ` Loftus, Ciara
2026-09-15 13:36 ` [PATCH v2 15/15] net/intel: consolidate Tx vector offload path checks Bruce Richardson
2026-09-16 9:02 ` Loftus, Ciara
2026-09-16 10:36 ` [PATCH v3 00/15] consolidate ice and iavf Tx vector paths Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 01/15] net/iavf: remove unnecessary alignment calls Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 02/15] net/intel: make Tx context flag common Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 03/15] net/iavf: use separate params for VLAN and QinQ position Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 04/15] net/iavf: deduplicate tunnel field fill functions Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 05/15] net/intel: define common macros for tunneling bit-shifts Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 06/15] net/intel: move iavf descriptor writing functions to common Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 07/15] net/intel: use function callback for lldp Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 08/15] net/intel: allow building without IOVA in mbuf Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 09/15] net/ice: use common descriptor creation functions Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 10/15] net/intel: move vector Tx paths to common Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 11/15] net/ice: use common AVX Tx functions Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 12/15] net/intel: add common vector Tx fns with context handling Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 13/15] net/intel: improve Tx path selection logic Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 14/15] net/ice: enable context desc offloads for vector Tx Bruce Richardson
2026-09-16 13:00 ` Loftus, Ciara
2026-09-16 13:06 ` Bruce Richardson
2026-09-16 10:36 ` [PATCH v3 15/15] net/intel: consolidate Tx vector offload path checks Bruce Richardson
2026-09-16 13:09 ` [PATCH v3 00/15] consolidate ice and iavf Tx vector paths Bruce Richardson
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