[PATCH v2 0/8] Add Renesas RZ/G3L TSU support

[PATCH v2 0/8] Add Renesas RZ/G3L TSU support

[Biju Das]

The Thermal sensor unit (a.k.a TSU) IP found on the RZ/G3L SoC is similar
to the RZ/G3S, but it has different calibration constants. Moreover, the
TSU is connected to A/D converter of TSU (a.k.a ADC1) on the RZ/G3L,
whereas it is connected to ADC0 on the RZ/G3S.

Compared to ADC0, there are no A/D conversion result registers(ADCR0 to
ADCR7) on the RZ/G3L, and the INTEN bits in the A/D converter interrupt
control register(a.k.a ADINT)  are also different.

This patch series aims to add support for TSU along with ADC1.

Merge strategy:
  * patch #1 clk subsystem
  * patch #2-#4 thermal subsystem
  * patch #5-#7 iio subsystem
  * patch #8 SoC subsystem

v1->v2:
 * Merged TSU and ADC1 series together.
 * Moved the clk patch.

Biju Das (8):
  clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
  dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU
  thermal/drivers/renesas/rzg3s: Convert calibration defaults to per-SoC
    match data
  thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
  dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells'
    required for R9A08G045
  dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
  iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
  arm64: dts: renesas: r9a08g046: Enable TSU

 .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 28 +++++++-
 .../thermal/renesas,r9a08g045-tsu.yaml        |  4 +-
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 66 +++++++++++++++++++
 drivers/clk/renesas/r9a08g046-cpg.c           | 10 +++
 drivers/iio/adc/rzg2l_adc.c                   |  9 +++
 drivers/thermal/renesas/rzg3s_thermal.c       | 38 ++++++++---
 6 files changed, 144 insertions(+), 11 deletions(-)

-- 
2.43.0

[PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

[Biju Das]

Add clock P20 (PLL2_DIV2/8), module clocks for ADC1 (ADCLK, PCLK)
and TSU (PCLK), along with the corresponding module resets for
ADC1 and TSU on the RZ/G3S (R9A08G046) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change.
---
 drivers/clk/renesas/r9a08g046-cpg.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 22821321a1d3..2c5ca5ab5f57 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -350,6 +350,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
 		    dtable_1_8, 0, 200000000UL, 0, NULL),
 	DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
 		    dtable_1_8, 0, 200000000UL, 0, NULL),
+	DEF_FIXED("P20", R9A08G046_CLK_P20, CLK_PLL2_DIV2, 1, 8),
 	DEF_G3S_DIV("SD0", R9A08G046_CLK_SD0, CLK_SEL_SDHI0, G3L_DIV_SDHI0, G3L_DIV_SDHI0_STS,
 		    dtable_1_4, 800000000UL, 600000000UL, CLK_SET_RATE_PARENT,
 		    rzg3s_cpg_div_clk_notifier),
@@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
 					MSTOP(BUS_MCPU2, BIT(0))),
 	DEF_MOD("gpio_hclk",		R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
 					MSTOP(BUS_PERI_CPU, BIT(6))),
+	DEF_MOD("adc1_adclk",		R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
+					MSTOP(BUS_PERI_VIDEO, BIT(14))),
+	DEF_MOD("adc1_pclk",		R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
+					MSTOP(BUS_PERI_VIDEO, BIT(14))),
+	DEF_MOD("tsu_pclk",		R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
+					MSTOP(BUS_PERI_VIDEO, BIT(15))),
 	DEF_MOD("pci_aclk",		R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0,
 					MSTOP(BUS_PERI_COM, BIT(10))),
 	DEF_MOD("pci_clkl1pm",		R9A08G046_PCI_CLKL1PM, R9A08G046_CLK_P8, 0x608, 1,
@@ -640,6 +647,9 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
 	DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
 	DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
 	DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
+	DEF_RST(R9A08G046_ADC1_PRESETN, 0x8a8, 2),
+	DEF_RST(R9A08G046_ADC1_ADRST_N, 0x8a8, 3),
+	DEF_RST(R9A08G046_TSU_PRESETN, 0x8ac, 0),
 	DEF_RST(R9A08G046_PCI_ARESETN, 0x908, 0),
 	DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
 	DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
-- 
2.43.0

Re: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: renesas: incorrect MSTOP bus for ADC1 and TSU clocks
--

commit e17a7f8fc3947f6cab70a435b3bbdc24af6057ce
Author: Biju Das <biju.das.jz@bp.renesas.com>

clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

This commit adds clock P20, module clocks for ADC1 and TSU, and the
corresponding resets for the RZ/G3S (R9A08G046) SoC.

> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> index 22821321a1d37..2c5ca5ab5f578 100644
> --- a/drivers/clk/renesas/r9a08g046-cpg.c
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
[ ... ]
> @@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
>  					MSTOP(BUS_MCPU2, BIT(0))),
>  	DEF_MOD("gpio_hclk",		R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
>  					MSTOP(BUS_PERI_CPU, BIT(6))),
> +	DEF_MOD("adc1_adclk",		R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
> +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> +	DEF_MOD("adc1_pclk",		R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
> +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> +	DEF_MOD("tsu_pclk",		R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
> +					MSTOP(BUS_PERI_VIDEO, BIT(15))),

[Severity: Medium]
Looking at r9a08g046_mod_clks in drivers/clk/renesas/r9a08g046-cpg.c, are
the MSTOP bus assignments for these ADC1 and TSU clocks correct?

Based on similar architecture mapping in RZ/G2L and RZ/G3S (which use
BUS_MCPU2 for these identical register offsets), it seems this code
might be assigning BUS_PERI_VIDEO when it should use BUS_MCPU2.

If these devices actually reside on BUS_MCPU2, could this regression
cause a write to the wrong MSTOP register during initialization or
runtime PM? This might cause the ADC1 and TSU clocks to fail to ungate
while concurrently corrupting bits 14 and 15 of the video module stop
register when the devices are probed.

>  	DEF_MOD("pci_aclk",		R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0,
>  					MSTOP(BUS_PERI_COM, BIT(10))),

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260918150730.122056-1-biju.das.jz@bp.renesas.com?part=1

RE: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset

[Biju Das]

Hi Sashiko,

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 18 September 2026 16:24

> Subject: Re: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] clk: renesas: incorrect MSTOP bus for ADC1 and TSU clocks
> --
> 
> commit e17a7f8fc3947f6cab70a435b3bbdc24af6057ce
> Author: Biju Das <biju.das.jz@bp.renesas.com>
> 
> clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
> 
> This commit adds clock P20, module clocks for ADC1 and TSU, and the corresponding resets for the RZ/G3S
> (R9A08G046) SoC.
> 
> > diff --git a/drivers/clk/renesas/r9a08g046-cpg.c
> > b/drivers/clk/renesas/r9a08g046-cpg.c
> > index 22821321a1d37..2c5ca5ab5f578 100644
> > --- a/drivers/clk/renesas/r9a08g046-cpg.c
> > +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> [ ... ]
> > @@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
> >  					MSTOP(BUS_MCPU2, BIT(0))),
> >  	DEF_MOD("gpio_hclk",		R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
> >  					MSTOP(BUS_PERI_CPU, BIT(6))),
> > +	DEF_MOD("adc1_adclk",		R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
> > +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> > +	DEF_MOD("adc1_pclk",		R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
> > +					MSTOP(BUS_PERI_VIDEO, BIT(14))),
> > +	DEF_MOD("tsu_pclk",		R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
> > +					MSTOP(BUS_PERI_VIDEO, BIT(15))),
> 
> [Severity: Medium]
> Looking at r9a08g046_mod_clks in drivers/clk/renesas/r9a08g046-cpg.c, are the MSTOP bus assignments for
> these ADC1 and TSU clocks correct?

It is correct as per RZ/G3L hardware manual.

Cheers,
Biju

[PATCH v2 2/8] dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU

[Biju Das]

Add the renesas,r9a08g046-tsu compatible string for the RZ/G3L Thermal
Sensor Unit (a.k.a TSU), which is similar to the RZ/G3S TSU but uses
different calibration constants. TSU is connected to a dedicated ADC IP
(a.k.a ADC1) on RZ/G3L.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Updated commit description.
---
 .../devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml    | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
index 573e2b9d3752..20fc1a8000e3 100644
--- a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
@@ -17,7 +17,9 @@ $ref: thermal-sensor.yaml#
 
 properties:
   compatible:
-    const: renesas,r9a08g045-tsu
+    enum:
+      - renesas,r9a08g045-tsu
+      - renesas,r9a08g046-tsu
 
   reg:
     maxItems: 1
-- 
2.43.0

Re: [PATCH v2 2/8] dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU

[Jonathan Cameron]

> Move the default (software) calibration values SW_CALIB0_VAL and
> SW_CALIB1_VAL, used when FUSE values are missing, into a new
> struct rzg3s_thermal_info retrieved via of_device_get_match_data().
> 
> This allows different SoCs sharing this driver to provide their own
> default calibration constants, which is needed as RZ/G3L uses
> different values than RZ/G3S.
> 
> No functional change intended for RZ/G3S.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
FWIW simple change and looks fine.
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

-- 
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

[PATCH v2 3/8] thermal/drivers/renesas/rzg3s: Convert calibration defaults to per-SoC match data

[Biju Das]

Move the default (software) calibration values SW_CALIB0_VAL and
SW_CALIB1_VAL, used when FUSE values are missing, into a new
struct rzg3s_thermal_info retrieved via of_device_get_match_data().

This allows different SoCs sharing this driver to provide their own
default calibration constants, which is needed as RZ/G3L uses
different values than RZ/G3S.

No functional change intended for RZ/G3S.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change.
---
 drivers/thermal/renesas/rzg3s_thermal.c | 32 ++++++++++++++++++-------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/renesas/rzg3s_thermal.c
index 7ced8f76a0ec..146b73a1b751 100644
--- a/drivers/thermal/renesas/rzg3s_thermal.c
+++ b/drivers/thermal/renesas/rzg3s_thermal.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/reset.h>
 #include <linux/thermal.h>
 #include <linux/units.h>
@@ -27,10 +28,6 @@
 
 #define TSU_READ_STEPS		8
 
-/* Default calibration values, if FUSE values are missing. */
-#define SW_CALIB0_VAL		1297
-#define SW_CALIB1_VAL		751
-
 #define MCELSIUS(temp)		((temp) * MILLIDEGREE_PER_DEGREE)
 
 /**
@@ -55,6 +52,16 @@ struct rzg3s_thermal_priv {
 	u16 calib1;
 };
 
+/**
+ * struct rzg3s_thermal_info - RZ/G3S thermal information
+ * @calib0: calibration value if FUSE value is missing
+ * @calib1: calibration value if FUSE value is missing
+ */
+struct rzg3s_thermal_info {
+	u16 calib0;
+	u16 calib1;
+};
+
 static int rzg3s_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
 {
 	struct rzg3s_thermal_priv *priv = thermal_zone_device_priv(tz);
@@ -149,7 +156,8 @@ static const struct thermal_zone_device_ops rzg3s_tz_of_ops = {
 	.change_mode = rzg3s_thermal_change_mode,
 };
 
-static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv)
+static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv,
+				    const struct rzg3s_thermal_info *info)
 {
 	struct device *dev = priv->dev;
 	u32 val;
@@ -163,13 +171,13 @@ static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv)
 	if (val & OTPTSUTRIM_EN_MASK)
 		priv->calib0 = FIELD_GET(OTPTSUTRIM_MASK, val);
 	else
-		priv->calib0 = SW_CALIB0_VAL;
+		priv->calib0 = info->calib0;
 
 	val = readl(priv->base + OTPTSUTRIM_REG(1));
 	if (val & OTPTSUTRIM_EN_MASK)
 		priv->calib1 = FIELD_GET(OTPTSUTRIM_MASK, val);
 	else
-		priv->calib1 = SW_CALIB1_VAL;
+		priv->calib1 = info->calib1;
 
 	pm_runtime_put_autosuspend(dev);
 
@@ -178,6 +186,7 @@ static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv)
 
 static int rzg3s_thermal_probe(struct platform_device *pdev)
 {
+	const struct rzg3s_thermal_info *info = device_get_match_data(&pdev->dev);
 	struct rzg3s_thermal_priv *priv;
 	struct device *dev = &pdev->dev;
 	int ret;
@@ -208,7 +217,7 @@ static int rzg3s_thermal_probe(struct platform_device *pdev)
 	if (ret)
 		return dev_err_probe(dev, ret, "Failed to enable runtime PM!\n");
 
-	ret = rzg3s_thermal_read_calib(priv);
+	ret = rzg3s_thermal_read_calib(priv, info);
 	if (ret)
 		return dev_err_probe(dev, ret, "Failed to read calibration data!\n");
 
@@ -251,8 +260,13 @@ static const struct dev_pm_ops rzg3s_thermal_pm_ops = {
 	SYSTEM_SLEEP_PM_OPS(rzg3s_thermal_suspend, rzg3s_thermal_resume)
 };
 
+static const struct rzg3s_thermal_info rzg3s_info = {
+	.calib0 = 1297,
+	.calib1 = 751,
+};
+
 static const struct of_device_id rzg3s_thermal_dt_ids[] = {
-	{ .compatible = "renesas,r9a08g045-tsu" },
+	{ .compatible = "renesas,r9a08g045-tsu", .data = &rzg3s_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids);
-- 
2.43.0

Re: [PATCH v2 3/8] thermal/drivers/renesas/rzg3s: Convert calibration defaults to per-SoC match data

[Jonathan Cameron]

> Add the renesas,r9a08g046-tsu compatible string and its default
> (software) calibration constants for RZ/G3L, used when FUSE
> calibration values are missing.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

-- 
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

[PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support

[Biju Das]

Add the renesas,r9a08g046-tsu compatible string and its default
(software) calibration constants for RZ/G3L, used when FUSE
calibration values are missing.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change.
---
 drivers/thermal/renesas/rzg3s_thermal.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/renesas/rzg3s_thermal.c
index 146b73a1b751..a8716da7fcd2 100644
--- a/drivers/thermal/renesas/rzg3s_thermal.c
+++ b/drivers/thermal/renesas/rzg3s_thermal.c
@@ -265,8 +265,14 @@ static const struct rzg3s_thermal_info rzg3s_info = {
 	.calib1 = 751,
 };
 
+static const struct rzg3s_thermal_info rzg3l_info = {
+	.calib0 = 1322,
+	.calib1 = 772,
+};
+
 static const struct of_device_id rzg3s_thermal_dt_ids[] = {
 	{ .compatible = "renesas,r9a08g045-tsu", .data = &rzg3s_info },
+	{ .compatible = "renesas,r9a08g046-tsu", .data = &rzg3l_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids);
-- 
2.43.0

Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support

[Jonathan Cameron]

> Add a conditional schema constraint so that '#io-channel-cells' is
> required when the compatible string is "renesas,r9a08g045-adc".
> 
> This is required because the R9A08G045 ADC serves as an IIO provider,
> allowing external hardware consumer nodes (such as the TSU) to reference
> its individual channels. The '#io-channel-cells' property must be present
> so consumers can correctly specify the channel index in their 'io-channels'
> phandle property.
> 
> Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

I think perhaps the description should include why this only applies
to this part , and not more generally but otherwise this is fine by
me.  The connection would be more obvious if it were
the 046 part that you were specifying this for given that only
has the one channel.

-- 
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

RE: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support

[Biju Das]

Hi Jonathan,

Thanks for the feedback.

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: 20 September 2026 18:39
> Subject: Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
> 
> > Add a conditional schema constraint so that '#io-channel-cells' is
> > required when the compatible string is "renesas,r9a08g045-adc".
> >
> > This is required because the R9A08G045 ADC serves as an IIO provider,
> > allowing external hardware consumer nodes (such as the TSU) to
> > reference its individual channels. The '#io-channel-cells' property
> > must be present so consumers can correctly specify the channel index in their 'io-channels'
> > phandle property.
> >
> > Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document
> > the TSU unit")
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> I think perhaps the description should include why this only applies to this part , and not more
> generally but otherwise this is fine by me.  The connection would be more obvious if it were the 046 part
> that you were specifying this for given that only has the one channel.

I guess there is a copy paste issue as you commented on TSU driver patch
("thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support) instead of
("dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045")??

RZ/G3S ADC has total 9 channels out of which channel 8 is 'io-channels' provider.
I will add this information in commit message to make it clear.

Cheers,
Biju

Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support

[Jonathan Cameron]

On Mon, 21 Sep 2026 01:44:20 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Hi Jonathan,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Jonathan Cameron <jic23@kernel.org>
> > Sent: 20 September 2026 18:39
> > Subject: Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
> >   
> > > Add a conditional schema constraint so that '#io-channel-cells' is
> > > required when the compatible string is "renesas,r9a08g045-adc".
> > >
> > > This is required because the R9A08G045 ADC serves as an IIO provider,
> > > allowing external hardware consumer nodes (such as the TSU) to
> > > reference its individual channels. The '#io-channel-cells' property
> > > must be present so consumers can correctly specify the channel index in their 'io-channels'
> > > phandle property.
> > >
> > > Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document
> > > the TSU unit")
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>  
> > 
> > I think perhaps the description should include why this only applies to this part , and not more
> > generally but otherwise this is fine by me.  The connection would be more obvious if it were the 046 part
> > that you were specifying this for given that only has the one channel.  
> 
> I guess there is a copy paste issue as you commented on TSU driver patch
> ("thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support) instead of
> ("dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045")??
> 
> RZ/G3S ADC has total 9 channels out of which channel 8 is 'io-channels' provider.
> I will add this information in commit message to make it clear.
So if only one channel is used as io-channels provider, the device sounds pretty
useful without that.  Hence my question on whether it should be 'required'.

Where there is just one channel the argument is simpler.

I'll fully admit I've lost track of which part is which!

Jonathan
> 
> Cheers,
> Biju

RE: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support

[Biju Das]

Hi Jonathan Cameron,

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: 21 September 2026 04:28
> Subject: Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
> 
> On Mon, 21 Sep 2026 01:44:20 +0000
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > Hi Jonathan,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Jonathan Cameron <jic23@kernel.org>
> > > Sent: 20 September 2026 18:39
> > > Subject: Re: [PATCH v2 4/8] thermal/drivers/renesas/rzg3s: Add
> > > RZ/G3L TSU support
> > >
> > > > Add a conditional schema constraint so that '#io-channel-cells' is
> > > > required when the compatible string is "renesas,r9a08g045-adc".
> > > >
> > > > This is required because the R9A08G045 ADC serves as an IIO
> > > > provider, allowing external hardware consumer nodes (such as the
> > > > TSU) to reference its individual channels. The '#io-channel-cells'
> > > > property must be present so consumers can correctly specify the channel index in their 'io-
> channels'
> > > > phandle property.
> > > >
> > > > Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu:
> > > > Document the TSU unit")
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > I think perhaps the description should include why this only applies
> > > to this part , and not more generally but otherwise this is fine by
> > > me.  The connection would be more obvious if it were the 046 part that you were specifying this for
> given that only has the one channel.
> >
> > I guess there is a copy paste issue as you commented on TSU driver
> > patch
> > ("thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support) instead of
> > ("dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045")??
> >
> > RZ/G3S ADC has total 9 channels out of which channel 8 is 'io-channels' provider.
> > I will add this information in commit message to make it clear.
> So if only one channel is used as io-channels provider, the device sounds pretty useful without that.
> Hence my question on whether it should be 'required'.

I agree, it is not required as majority channels on RZ/G3S SoC(ADC0..ADC7) are not
providers. I will drop this patch.

Cheers,
Biju

[PATCH v2 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045

[Biju Das]

Add a conditional schema constraint so that '#io-channel-cells' is
required when the compatible string is "renesas,r9a08g045-adc".

This is required because the R9A08G045 ADC serves as an IIO provider,
allowing external hardware consumer nodes (such as the TSU) to reference
its individual channels. The '#io-channel-cells' property must be present
so consumers can correctly specify the channel index in their 'io-channels'
phandle property.

Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change.
---
 .../devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml   | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index 40341d541726..60fbc05acc1a 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -121,6 +121,15 @@ allOf:
             reg:
               maximum: 7
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-adc
+    then:
+      required:
+        - '#io-channel-cells'
+
 additionalProperties: false
 
 examples:
-- 
2.43.0

Re: [PATCH v2 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Make '#io-channel-cells' required for R9A08G045

[Rob Herring (Arm)]

On Fri, 18 Sep 2026 16:07:22 +0100, Biju Das wrote:
> Add a conditional schema constraint so that '#io-channel-cells' is
> required when the compatible string is "renesas,r9a08g045-adc".
> 
> This is required because the R9A08G045 ADC serves as an IIO provider,
> allowing external hardware consumer nodes (such as the TSU) to reference
> its individual channels. The '#io-channel-cells' property must be present
> so consumers can correctly specify the channel index in their 'io-channels'
> phandle property.
> 
> Fixes: a3152e5c742c ("dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change.
> ---
>  .../devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml   | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Add the renesas,r9a08g046-adc1 compatible string for the ADC1
instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal
sensor unit). Unlike the other ADC instances, this one only exposes
a single channel (channel@8), so restrict the allowed channel nodes
accordingly.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change.
---
 .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 21 +++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index 60fbc05acc1a..f4705d5ca543 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -25,7 +25,9 @@ properties:
               - renesas,r9a07g054-adc   # RZ/V2L
           - const: renesas,rzg2l-adc
       - items:
-          - const: renesas,r9a08g045-adc  # RZ/G3S
+          - enum:
+              - renesas,r9a08g045-adc   # RZ/G3S
+              - renesas,r9a08g046-adc1  # RZ/G3L ADC for TSU
 
   reg:
     maxItems: 1
@@ -125,7 +127,22 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a08g045-adc
+            const: renesas,r9a08g046-adc1
+    then:
+      patternProperties:
+        "^channel@[0-7]$": false
+        "^channel@[8]$":
+          properties:
+            reg:
+              const: 8
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a08g045-adc
+              - renesas,r9a08g046-adc1
     then:
       required:
         - '#io-channel-cells'
-- 
2.43.0

Re: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Jonathan Cameron]

> Add renesas,r9a08g046-adc1 compatible string and its hardware
> parameters for the ADC1 IP on RZ/G3L, which is dedicated to
> the on-chip TSU (thermal sensor unit).
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> index 408fbf8c29cc..35eaebfbdd77 100644
> --- a/drivers/iio/adc/rzg2l_adc.c
> +++ b/drivers/iio/adc/rzg2l_adc.c
> @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
>  	.adint_inten_mask = GENMASK(11, 0),
>  };
>  
> +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> +	.num_channels = 9,

This maybe needs a comment that only channel 8 actually goes anywhere.

-- 
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>

RE: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Hi Jonathan,

Thanks for the feedback.

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: 20 September 2026 18:39
> Subject: Re: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> 
> > Add renesas,r9a08g046-adc1 compatible string and its hardware
> > parameters for the ADC1 IP on RZ/G3L, which is dedicated to the
> > on-chip TSU (thermal sensor unit).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> > index 408fbf8c29cc..35eaebfbdd77 100644
> > --- a/drivers/iio/adc/rzg2l_adc.c
> > +++ b/drivers/iio/adc/rzg2l_adc.c
> > @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
> >  	.adint_inten_mask = GENMASK(11, 0),
> >  };
> >
> > +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> > +	.num_channels = 9,
> 
> This maybe needs a comment that only channel 8 actually goes anywhere.

Yes, it deserves a comment as it has only 1 channel and its channel number is 8.
Or
change the variable name from num_channels to max_channels to make it
Clear. Shall I change the variable name? or still you prefer adding comment.
Please let me know.

RZ/G3S ADC has 9 channels{ADC0..ADC8) and ADC8 is connected to thermal sensor unit.
RZ/G3L ADC1 IP has 1 channel ADC8 and ADC8 is connected to thermal sensor unit.
RZ/G3L ADC0 IP has 8 channels (ADC0..ADC7).

Note:
Looks like copy paste mistake. You commented on binding patches for 
Driver changes.

https://lore.kernel.org/all/20260918150730.122056-8-biju.das.jz@bp.renesas.com/

Cheers,
Biju

Re: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Jonathan Cameron]

On Mon, 21 Sep 2026 02:03:18 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Hi Jonathan,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Jonathan Cameron <jic23@kernel.org>
> > Sent: 20 September 2026 18:39
> > Subject: Re: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> >   
> > > Add renesas,r9a08g046-adc1 compatible string and its hardware
> > > parameters for the ADC1 IP on RZ/G3L, which is dedicated to the
> > > on-chip TSU (thermal sensor unit).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> > > index 408fbf8c29cc..35eaebfbdd77 100644
> > > --- a/drivers/iio/adc/rzg2l_adc.c
> > > +++ b/drivers/iio/adc/rzg2l_adc.c
> > > @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
> > >  	.adint_inten_mask = GENMASK(11, 0),
> > >  };
> > >
> > > +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> > > +	.num_channels = 9,  
> > 
> > This maybe needs a comment that only channel 8 actually goes anywhere.  
> 
> Yes, it deserves a comment as it has only 1 channel and its channel number is 8.
> Or
> change the variable name from num_channels to max_channels to make it
> Clear. Shall I change the variable name? or still you prefer adding comment.
> Please let me know.

That makes sense.  So yes, please rename.

> 
> RZ/G3S ADC has 9 channels{ADC0..ADC8) and ADC8 is connected to thermal sensor unit.
> RZ/G3L ADC1 IP has 1 channel ADC8 and ADC8 is connected to thermal sensor unit.
> RZ/G3L ADC0 IP has 8 channels (ADC0..ADC7).
> 
> Note:
> Looks like copy paste mistake. You commented on binding patches for 
> Driver changes.
> 
> https://lore.kernel.org/all/20260918150730.122056-8-biju.das.jz@bp.renesas.com/

Don't think so. That was about the binding.  I was asking why io-channels is required
which is all about what channels exist and how useful a subset is.

> 
> Cheers,
> Biju
> 
> 

RE: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Hi Jonathan Cameron,

Thanks for the feedback.

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: 21 September 2026 04:30
> Subject: Re: [PATCH v2 6/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> 
> On Mon, 21 Sep 2026 02:03:18 +0000
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > Hi Jonathan,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Jonathan Cameron <jic23@kernel.org>
> > > Sent: 20 September 2026 18:39
> > > Subject: Re: [PATCH v2 6/8] dt-bindings: iio: adc:
> > > renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> > >
> > > > Add renesas,r9a08g046-adc1 compatible string and its hardware
> > > > parameters for the ADC1 IP on RZ/G3L, which is dedicated to the
> > > > on-chip TSU (thermal sensor unit).
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > diff --git a/drivers/iio/adc/rzg2l_adc.c
> > > > b/drivers/iio/adc/rzg2l_adc.c index 408fbf8c29cc..35eaebfbdd77
> > > > 100644
> > > > --- a/drivers/iio/adc/rzg2l_adc.c
> > > > +++ b/drivers/iio/adc/rzg2l_adc.c
> > > > @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
> > > >  	.adint_inten_mask = GENMASK(11, 0),  };
> > > >
> > > > +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> > > > +	.num_channels = 9,
> > >
> > > This maybe needs a comment that only channel 8 actually goes anywhere.
> >
> > Yes, it deserves a comment as it has only 1 channel and its channel number is 8.
> > Or
> > change the variable name from num_channels to max_channels to make it
> > Clear. Shall I change the variable name? or still you prefer adding comment.
> > Please let me know.
> 
> That makes sense.  So yes, please rename.

OK.

> 
> >
> > RZ/G3S ADC has 9 channels{ADC0..ADC8) and ADC8 is connected to thermal sensor unit.
> > RZ/G3L ADC1 IP has 1 channel ADC8 and ADC8 is connected to thermal sensor unit.
> > RZ/G3L ADC0 IP has 8 channels (ADC0..ADC7).
> >
> > Note:
> > Looks like copy paste mistake. You commented on binding patches for
> > Driver changes.
> >
> > https://lore.kernel.org/all/20260918150730.122056-8-biju.das.jz@bp.ren
> > esas.com/
> 
> Don't think so. That was about the binding.  I was asking why io-channels is required which is all about
> what channels exist and how useful a subset is.

OK. I will drop the required property 'io-channels' from RZ/G3L binding as well.

Cheers,
Biju

[PATCH v2 7/8] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU

[Biju Das]

Add renesas,r9a08g046-adc1 compatible string and its hardware
parameters for the ADC1 IP on RZ/G3L, which is dedicated to
the on-chip TSU (thermal sensor unit).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change.
---
 drivers/iio/adc/rzg2l_adc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 408fbf8c29cc..35eaebfbdd77 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
 	.adint_inten_mask = GENMASK(11, 0),
 };
 
+static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
+	.num_channels = 9,
+	.default_adcmp = 0x1d,
+	.default_adsmp = { 0x7f, 0xff },
+	.adsmp_mask = GENMASK(7, 0),
+	.adint_inten_mask = BIT(8),
+};
+
 static const struct of_device_id rzg2l_adc_match[] = {
 	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
+	{ .compatible = "renesas,r9a08g046-adc1", .data = &rzg3l_adc1_hw_params },
 	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
 	{ }
 };
-- 
2.43.0

[PATCH v2 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[Biju Das]

Add #cooling-cells to the CPU nodes, and describe the ADC1 (used
exclusively by the TSU) and TSU nodes along with a CPU thermal zone
using passive and critical trip points, with CPU frequency cooling
maps for thermal mitigation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 66 ++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 53e68b1c3258..29ce1ab2a57f 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -179,6 +179,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -189,6 +190,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -199,6 +201,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -209,6 +212,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -374,6 +378,37 @@ scif5: serial@1004e000 {
 			status = "disabled";
 		};
 
+		adc1: adc@108c0000 {
+			compatible = "renesas,r9a08g046-adc1";
+			reg = <0 0x108c0000 0 0x10000>;
+			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
+				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A08G046_ADC1_PRESETN>,
+				 <&cpg R9A08G046_ADC1_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@8 {
+				reg = <8>;
+			};
+		};
+
+		tsu: thermal@108d0000 {
+			compatible = "renesas,r9a08g046-tsu";
+			reg = <0 0x108d0000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
+			resets = <&cpg R9A08G046_TSU_PRESETN>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			io-channels = <&adc1 0>;
+			io-channel-names = "tsu";
+		};
+
 		i2c0: i2c@100ae000 {
 			compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
 			reg = <0 0x100ae000 0 0x400>;
@@ -1570,6 +1605,37 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				sensor_crit: sensor-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+
+				target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.43.0

Re: [PATCH v2 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt: io-channels hardcodes Linux array index instead of hardware ID
--

commit 43dcf56f74f46f025839610adda743ab502b8711
Author: Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: r9a08g046: Enable TSU

This commit adds cooling cells to the CPU nodes and describes the ADC1 and TSU
nodes to enable thermal mitigation. It also sets up a CPU thermal zone with
passive and critical trip points.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index c63a857f0e5b0..a2f6718c0043a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
[ ... ]
> +		adc1: adc@108c0000 {
> +			compatible = "renesas,r9a08g046-adc1";
> +			reg = <0 0x108c0000 0 0x10000>;
> +			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
> +			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
> +				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
> +			clock-names = "adclk", "pclk";
> +			resets = <&cpg R9A08G046_ADC1_PRESETN>,
> +				 <&cpg R9A08G046_ADC1_ADRST_N>;
> +			reset-names = "presetn", "adrst-n";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#io-channel-cells = <1>;
> +
> +			channel@8 {
> +				reg = <8>;
> +			};
> +		};
> +
> +		tsu: thermal@108d0000 {
> +			compatible = "renesas,r9a08g046-tsu";
> +			reg = <0 0x108d0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> +			power-domains = <&cpg>;
> +			#thermal-sensor-cells = <0>;
> +			io-channels = <&adc1 0>;
> +			io-channel-names = "tsu";

[Severity: Medium]
Does this hardcode an internal Linux array index (0) instead of the actual
hardware channel ID (8)?

Since channel@8 is the only defined channel in the adc1 node, it currently
sits at index 0 in the driver's array, which masks the issue.

If a future device tree update enables another channel (like channel@0),
would the array shift so index 0 points to the wrong physical channel? This
looks like it could cause the CPU to read incorrect thermal data and break
thermal mitigation.

> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260918150730.122056-1-biju.das.jz@bp.renesas.com?part=8

RE: [PATCH v2 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[Biju Das]

Hi Sashiko,

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 18 September 2026 16:23
> Subject: Re: [PATCH v2 8/8] arm64: dts: renesas: r9a08g046: Enable TSU
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] dt: io-channels hardcodes Linux array index instead of hardware ID
> --
> 
> commit 43dcf56f74f46f025839610adda743ab502b8711
> Author: Biju Das <biju.das.jz@bp.renesas.com>
> arm64: dts: renesas: r9a08g046: Enable TSU
> 
> This commit adds cooling cells to the CPU nodes and describes the ADC1 and TSU nodes to enable thermal
> mitigation. It also sets up a CPU thermal zone with passive and critical trip points.
> 
> > diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > index c63a857f0e5b0..a2f6718c0043a 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> [ ... ]
> > +		adc1: adc@108c0000 {
> > +			compatible = "renesas,r9a08g046-adc1";
> > +			reg = <0 0x108c0000 0 0x10000>;
> > +			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
> > +			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
> > +				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
> > +			clock-names = "adclk", "pclk";
> > +			resets = <&cpg R9A08G046_ADC1_PRESETN>,
> > +				 <&cpg R9A08G046_ADC1_ADRST_N>;
> > +			reset-names = "presetn", "adrst-n";
> > +			power-domains = <&cpg>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			#io-channel-cells = <1>;
> > +
> > +			channel@8 {
> > +				reg = <8>;
> > +			};
> > +		};
> > +
> > +		tsu: thermal@108d0000 {
> > +			compatible = "renesas,r9a08g046-tsu";
> > +			reg = <0 0x108d0000 0 0x10000>;
> > +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> > +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> > +			power-domains = <&cpg>;
> > +			#thermal-sensor-cells = <0>;
> > +			io-channels = <&adc1 0>;
> > +			io-channel-names = "tsu";
> 
> [Severity: Medium]
> Does this hardcode an internal Linux array index (0) instead of the actual hardware channel ID (8)?

There is a mapping between internal Linux array index (0) and the actual hardware channel ID (8).

See the code
https://elixir.bootlin.com/linux/v7.3-rc3/source/drivers/iio/adc/rzg2l_adc.c#L354

Cheers,
Biju