* [PATCH 0/2] arm64: add support for Olimex i.MX8MP-SOM-EVB kit @ 2026-09-18 19:55 Zoltan HERPAI 2026-09-18 19:55 ` [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Zoltan HERPAI 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 0 siblings, 2 replies; 8+ messages in thread From: Zoltan HERPAI @ 2026-09-18 19:55 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel Cc: wigyori, devicetree, linux-arm-kernel, linux-kernel This series adds support for the Olimex i.MX8MP-SOM-EVB kit, consisting of a carrier board and a SoM. Patch 1/2 documents the respective bindings, Patch 2/2 adds the SoM dtsi and the carrier board dts. Zoltan HERPAI (2): dt-bindings: arm64: fsl: add Olimex i.MX8MP boards arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit .../devicetree/bindings/arm/fsl.yaml | 7 + arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-olimex-som-evb.dts | 168 +++++ .../boot/dts/freescale/imx8mp-olimex-som.dtsi | 578 ++++++++++++++++++ 4 files changed, 754 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards 2026-09-18 19:55 [PATCH 0/2] arm64: add support for Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI @ 2026-09-18 19:55 ` Zoltan HERPAI 2026-09-18 20:04 ` sashiko-bot 2026-09-19 7:11 ` Krzysztof Kozlowski 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 1 sibling, 2 replies; 8+ messages in thread From: Zoltan HERPAI @ 2026-09-18 19:55 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel Cc: wigyori, devicetree, linux-arm-kernel, linux-kernel Document board compatible bindings for the Olimex i.MX8MP-SOM and -EVB boards. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 656f2596e..aef153222 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1146,6 +1146,8 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - olimex,imx8mp-som # Olimex i.MX8MP-SOM + - olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB - prt,prt8ml # Protonic PRT8ML - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel @@ -1225,6 +1227,11 @@ properties: - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM - const: fsl,imx8mp + - description: Olimex i.MX8MP boards + items: + - const: olimex,imx8mp-som # Olimex i.MX8MP-SOM + - const: olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB + - description: PHYTEC phyCORE-i.MX8MP FPSC based boards items: - enum: -- 2.39.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards 2026-09-18 19:55 ` [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Zoltan HERPAI @ 2026-09-18 20:04 ` sashiko-bot 2026-09-19 7:11 ` Krzysztof Kozlowski 1 sibling, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-09-18 20:04 UTC (permalink / raw) To: Zoltan HERPAI; +Cc: robh, conor+dt, devicetree Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] dt-bindings: broken compatible string sequence for Olimex i.MX8MP -- commit fac5462a0966914cfbc1e0773b00c8f06fddde88 Author: Zoltan HERPAI <wigyori@uid0.hu> dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Document board compatible bindings for the Olimex i.MX8MP-SOM and -EVB boards. > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > index 656f2596e1d53..aef15322293e1 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -1146,6 +1146,8 @@ properties: > - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board > - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board > - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board > + - olimex,imx8mp-som # Olimex i.MX8MP-SOM > + - olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB [Severity: Low] Does adding the EVB string directly to this enum permit it to bypass the SoM component string dependency? It seems this validates a 2-item sequence instead of the standard 3-item sequence (Carrier -> SoM -> SoC) expected for SoM-based carrier boards. > - prt,prt8ml # Protonic PRT8ML > - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate [ ... ] > @@ -1225,6 +1227,11 @@ properties: > - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM > - const: fsl,imx8mp > > + - description: Olimex i.MX8MP boards > + items: > + - const: olimex,imx8mp-som # Olimex i.MX8MP-SOM > + - const: olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB [Severity: Low] Does this block enforce a backwards 2-item sequence with the most specific board listed last? Also, it appears the mandatory SoC fallback (fsl,imx8mp) is entirely omitted here. Will this cause dt_binding_check or dtbs_check to fail when run on a properly constructed 3-item compatible array? > + > - description: PHYTEC phyCORE-i.MX8MP FPSC based boards > items: > - enum: -- Sashiko AI review · https://sashiko.dev/#/patchset/20260918195559.130443-1-wigyori@uid0.hu?part=1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards 2026-09-18 19:55 ` [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Zoltan HERPAI 2026-09-18 20:04 ` sashiko-bot @ 2026-09-19 7:11 ` Krzysztof Kozlowski 1 sibling, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2026-09-19 7:11 UTC (permalink / raw) To: Zoltan HERPAI, robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel Cc: devicetree, linux-arm-kernel, linux-kernel On 18/09/2026 21:55, Zoltan HERPAI wrote: > Document board compatible bindings for the Olimex i.MX8MP-SOM and > -EVB boards. > > Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > index 656f2596e..aef153222 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -1146,6 +1146,8 @@ properties: > - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board > - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board > - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board > + - olimex,imx8mp-som # Olimex i.MX8MP-SOM > + - olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB How som can be used alone? > - prt,prt8ml # Protonic PRT8ML > - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate > - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel > @@ -1225,6 +1227,11 @@ properties: > - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM > - const: fsl,imx8mp > > + - description: Olimex i.MX8MP boards > + items: > + - const: olimex,imx8mp-som # Olimex i.MX8MP-SOM > + - const: olimex,imx8mp-som-evb # Olimex i.MX8MP-SOM-EVB This makes no sense. Why duplicated? And where is fallback? Why are you doing it completely different than everybody else? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit 2026-09-18 19:55 [PATCH 0/2] arm64: add support for Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 2026-09-18 19:55 ` [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Zoltan HERPAI @ 2026-09-18 19:55 ` Zoltan HERPAI 2026-09-18 20:07 ` sashiko-bot ` (2 more replies) 1 sibling, 3 replies; 8+ messages in thread From: Zoltan HERPAI @ 2026-09-18 19:55 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel Cc: wigyori, devicetree, linux-arm-kernel, linux-kernel This adds support for an i.MX8-based system-on-module + EVB board. The product pages are here [1] and here [2] respectively. There are two new files, one dts for the EVB and one dtsi for the SoM. EVB features: - microSD slot, eMMC headers - 2x Ethernet 1Gb - 2x USB 3.0 - 1x m.2 PCIe slot - 2x CAN interface - audio (2x jacks via ES8328) - at24 eeprom - separate UARTs for the A53 and the M7 cores - HDMI - UEXT and GPIO connectors with I2C available SoM features: - NXP i.MX8MP @ 1600MHz - 4GByte memory - LVDS interface - 2x MIPI_CSI, 1x MIPI_DSI - status LED [1] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-4GB-IND [2] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-EVB-IND Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-olimex-som-evb.dts | 137 +++++ .../boot/dts/freescale/imx8mp-olimex-som.dtsi | 571 ++++++++++++++++++ 3 files changed, 709 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 95ae85ab4..3657e3464 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -447,6 +447,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-olimex-som-evb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-etml1010g3dra.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts new file mode 100644 index 000000000..26fee72d5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2026 Zoltan HERPAI <wigyori@uid0.hu> + */ + +/dts-v1/; + +#include "imx8mp-olimex-som.dtsi" + +/ { + compatible = "olimex,imx8mp-som-evb", "fsl,imx8mp"; + model = "Olimex i.MX8MP-SOM-EVB"; + + chosen { + stdout-path = &uart2; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + + status = "okay"; +}; + +&i2c1 { + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <122>; + + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb1_host_vbus>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; + + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi new file mode 100644 index 000000000..9876d3e7b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2026 Zoltan HERPAI <wigyori@uid0.hu> + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/leds/common.h> +#include "imx8mp.dtsi" + +/ { + compatible = "olimex,imx8mp-som", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led_status: status { + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; + }; + + pcie0_refclk: clock-pcie0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-100tx; + eee-broken-1000t; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <150000>; + reset-deassert-us = <10000>; + + reg = <3>; + }; + }; +}; + +&fec { + fsl,magic-packet; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <150000>; + reset-deassert-us = <10000>; + + reg = <7>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + status = "okay"; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; + + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + + status = "okay"; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* PCIE_RESET */ + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; -- 2.39.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI @ 2026-09-18 20:07 ` sashiko-bot 2026-09-19 7:10 ` Krzysztof Kozlowski 2026-09-20 15:04 ` Andrew Lunn 2 siblings, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-09-18 20:07 UTC (permalink / raw) To: Zoltan HERPAI; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 7 potential issue(s) to consider: - [High] dt: PMIC interrupt misconfigured as edge-rising instead of level-low - [Medium] dt: EVB carrier features incorrectly enabled in SOM dtsi - [Medium] dt: unused CAN standby pinctrl groups leave transceivers disabled - [Medium] dt: missing pinctrl-names in PMIC node prevents pinmux application - [Low] dt: duplicate pinctrl_usb1_vbus label causes build error - [Low] dt: rohm,dh2228fv compatible string abused for generic SPI header - [Low] dt: deprecated reset-gpio property used in PCIe node -- commit b3a5c80438428e973d66a598e54426ad5ece4f26 Author: Zoltan HERPAI <wigyori@uid0.hu> arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit This adds support for an i.MX8-based system-on-module + EVB board. The product pages are here [1] and here [2] respectively. There are two new files, one dts for the EVB and one dtsi for the SoM. > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts > new file mode 100644 > index 0000000000000..26fee72d50c90 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts [ ... ] > +&ecspi2 { > + #address-cells = <1>; > + #size-cells = <0>; > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; > + > + status = "okay"; > + > + spidev1: spi@0 { > + reg = <0>; > + compatible = "rohm,dh2228fv"; > + spi-max-frequency = <500000>; > + }; > +}; [Severity: Low] Is it appropriate to use the rohm,dh2228fv compatible string here for a generic SPI header? This appears to be forcing the spidev driver to bind and silences DTC warnings, which goes against the device tree compatible string mechanism. [ ... ] > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + > + status = "okay"; > +}; [Severity: Medium] Will this configuration leave the CAN1 transceiver disabled? The flexcan1 node fails to reference the pinctrl_flexcan1_reg standby pins or a regulator for them. [ ... ] > + pinctrl_flexcan1_reg: flexcan1reggrp { > + fsl,pins = < > + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ > + >; > + }; Because these standby pins are configured but never used, the physical CAN transceivers will likely remain disabled. [ ... ] > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi > new file mode 100644 > index 0000000000000..9876d3e7b81a3 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi [ ... ] > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + > + status = "okay"; > + > + pmic: pmic@25 { > + reg = <0x25>; > + compatible = "nxp,pca9450c"; > + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio1>; > + interrupts = <3 GPIO_ACTIVE_LOW>; [Severity: Medium] Does the pmic@25 node need a pinctrl-names = "default"; property here? Without it, the kernel's pinctrl core will not automatically apply the pinctrl-0 state during probe, potentially leaving the interrupt pin floating. [Severity: High] Does this interrupt configuration break the delivery of PMIC events? The GPIO_ACTIVE_LOW flag resolves to 1, which corresponds to IRQ_TYPE_EDGE_RISING. Since the PCA9450's INTb line is active low, the host expecting a rising edge will miss the interrupts. Should this be IRQ_TYPE_LEVEL_LOW instead? [ ... ] > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; > + vpcie-supply = <®_pcie0>; > + > + status = "okay"; > +}; [Severity: Medium] Is it correct to enable EVB carrier features like PCIe inside the shared SOM .dtsi file? Hardcoding baseboard-specific peripheral enablement here causes pin conflicts and prevents this .dtsi from being reused for other carrier board designs. [Severity: Low] Does this node use a deprecated property? The reset-gpio property is deprecated by standard PCI bindings which require the generic reset-gpios plural format. [ ... ] > +&usdhc2 { > + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > + assigned-clock-rates = <400000000>; > + bus-width = <4>; > + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + vmmc-supply = <®_usdhc2_vmmc>; > + > + status = "okay"; > +}; [Severity: Medium] Should the usdhc2 (microSD slot) be enabled in the SOM .dtsi? Similar to PCIe, enabling baseboard-specific features in the shared SoM file breaks device tree abstraction and forces other carrier boards to inherit this configuration. [ ... ] > + pinctrl_usb1_vbus: usb1grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { [ ... ] > + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { > + fsl,pins = < > + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 > + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 > + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 > + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 > + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 > + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 > + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 > + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 > + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 > + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 > + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 > + >; > + }; > + > + pinctrl_usb1_vbus: usb1grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 > + >; > + }; [Severity: Low] Does this code duplicate the pinctrl_usb1_vbus label? The Device Tree Compiler (DTC) prohibits identically named nodes and duplicate labels at the same scope level, and this will cause a build failure. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260918195559.130443-1-wigyori@uid0.hu?part=2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 2026-09-18 20:07 ` sashiko-bot @ 2026-09-19 7:10 ` Krzysztof Kozlowski 2026-09-20 15:04 ` Andrew Lunn 2 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2026-09-19 7:10 UTC (permalink / raw) To: Zoltan HERPAI, robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel Cc: devicetree, linux-arm-kernel, linux-kernel On 18/09/2026 21:55, Zoltan HERPAI wrote: > This adds support for an i.MX8-based system-on-module + EVB board. The Please do not use "This commit/patch/change", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94 > product pages are here [1] and here [2] respectively. > > There are two new files, one dts for the EVB and one dtsi for the SoM. > ... > +&ecspi2 { > + #address-cells = <1>; > + #size-cells = <0>; > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; > + > + status = "okay"; > + > + spidev1: spi@0 { > + reg = <0>; > + compatible = "rohm,dh2228fv"; No, strong no. This does not exist. Don't invent fake devices on your board. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 2026-09-18 20:07 ` sashiko-bot 2026-09-19 7:10 ` Krzysztof Kozlowski @ 2026-09-20 15:04 ` Andrew Lunn 2 siblings, 0 replies; 8+ messages in thread From: Andrew Lunn @ 2026-09-20 15:04 UTC (permalink / raw) To: Zoltan HERPAI Cc: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, kernel, devicetree, linux-arm-kernel, linux-kernel On Fri, Sep 18, 2026 at 09:55:59PM +0200, Zoltan HERPAI wrote: > This adds support for an i.MX8-based system-on-module + EVB board. The > product pages are here [1] and here [2] respectively. > > There are two new files, one dts for the EVB and one dtsi for the SoM. > > EVB features: > - microSD slot, eMMC headers > - 2x Ethernet 1Gb > - 2x USB 3.0 > - 1x m.2 PCIe slot > - 2x CAN interface > - audio (2x jacks via ES8328) > - at24 eeprom > - separate UARTs for the A53 and the M7 cores > - HDMI > - UEXT and GPIO connectors with I2C available > > SoM features: > - NXP i.MX8MP @ 1600MHz > - 4GByte memory > - LVDS interface > - 2x MIPI_CSI, 1x MIPI_DSI > - status LED > > [1] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-4GB-IND > [2] https://www.olimex.com/Products/SOM/NXP-iMX8/iMX8MP-SOM-EVB-IND > > Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../dts/freescale/imx8mp-olimex-som-evb.dts | 137 +++++ > .../boot/dts/freescale/imx8mp-olimex-som.dtsi | 571 ++++++++++++++++++ > 3 files changed, 709 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 95ae85ab4..3657e3464 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -447,6 +447,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-olimex-som-evb.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb > imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ > imx8mp-phyboard-pollux-etml1010g3dra.dtbo > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts > new file mode 100644 > index 000000000..26fee72d5 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som-evb.dts > @@ -0,0 +1,137 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2019 NXP > + * Copyright 2026 Zoltan HERPAI <wigyori@uid0.hu> > + */ > + > +/dts-v1/; > + > +#include "imx8mp-olimex-som.dtsi" > + > +/ { > + compatible = "olimex,imx8mp-som-evb", "fsl,imx8mp"; > + model = "Olimex i.MX8MP-SOM-EVB"; > + > + chosen { > + stdout-path = &uart2; > + }; > +}; > + > +&ecspi2 { > + #address-cells = <1>; > + #size-cells = <0>; > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; > + > + status = "okay"; > + > + spidev1: spi@0 { > + reg = <0>; > + compatible = "rohm,dh2228fv"; > + spi-max-frequency = <500000>; > + }; > +}; > + > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + > + status = "okay"; > +}; > + > +&flexcan2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + > + status = "okay"; > +}; > + > +&i2c1 { > + eeprom: eeprom@50 { > + compatible = "atmel,24c16"; > + reg = <0x50>; > + pagesize = <16>; > + }; > +}; > + > +&snvs_pwrkey { > + status = "okay"; > +}; > + > +&usb3_phy0 { > + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; > + fsl,phy-tx-vref-tune-percent = <122>; > + > + status = "okay"; > +}; > + > +&usb3_0 { > + status = "okay"; > +}; > + > +&usb_dwc3_0 { > + dr_mode = "host"; > + > + status = "okay"; > +}; > + > +&usb3_phy1 { > + vbus-supply = <®_usb1_host_vbus>; > + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; > + fsl,phy-tx-vref-tune-percent = <116>; > + > + status = "okay"; > +}; > + > +&usb3_1 { > + status = "okay"; > +}; > + > +&usb_dwc3_1 { > + dr_mode = "host"; > + > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_ecspi2: ecspi2grp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 > + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 > + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 > + >; > + }; > + > + pinctrl_ecspi2_cs: ecspi2csgrp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 > + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 > + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 > + >; > + }; > + > + pinctrl_flexcan1_reg: flexcan1reggrp { > + fsl,pins = < > + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ > + >; > + }; > + > + pinctrl_flexcan2_reg: flexcan2reggrp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ > + >; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi > new file mode 100644 > index 000000000..9876d3e7b > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-olimex-som.dtsi > @@ -0,0 +1,571 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2019 NXP > + * Copyright 2026 Zoltan HERPAI <wigyori@uid0.hu> > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/usb/pd.h> > +#include <dt-bindings/phy/phy-imx8-pcie.h> > +#include <dt-bindings/leds/common.h> > +#include "imx8mp.dtsi" > + > +/ { > + compatible = "olimex,imx8mp-som", "fsl,imx8mp"; > + > + chosen { > + stdout-path = &uart2; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_led>; > + > + led_status: status { > + color = <LED_COLOR_ID_YELLOW>; > + function = LED_FUNCTION_STATUS; > + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; > + default-state = "on"; > + }; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0 0xc0000000>, > + <0x1 0x00000000 0 0x40000000>; > + }; > + > + pcie0_refclk: clock-pcie0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > + reg_pcie0: regulator-pcie { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0_reg>; > + regulator-name = "MPCIE_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usb1_host_vbus: regulator-usb1-vbus { > + compatible = "regulator-fixed"; > + regulator-name = "usb1_host_vbus"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb1_vbus>; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > +}; > + > +&A53_0 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck2>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck2>; > +}; > + > +&eqos { > + phy-handle = <ðphy0>; > + phy-mode = "rgmii-id"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_eqos>; > + > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + eee-broken-100tx; > + eee-broken-1000t; Do you know what is actually broken here? Is it the PHY? The MAC? The combination of MAC and PHY? Andrew ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-09-20 15:04 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-09-18 19:55 [PATCH 0/2] arm64: add support for Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 2026-09-18 19:55 ` [PATCH 1/2] dt-bindings: arm64: fsl: add Olimex i.MX8MP boards Zoltan HERPAI 2026-09-18 20:04 ` sashiko-bot 2026-09-19 7:11 ` Krzysztof Kozlowski 2026-09-18 19:55 ` [PATCH 2/2] arm64: dts: imx8mp: add Olimex i.MX8MP-SOM-EVB kit Zoltan HERPAI 2026-09-18 20:07 ` sashiko-bot 2026-09-19 7:10 ` Krzysztof Kozlowski 2026-09-20 15:04 ` Andrew Lunn
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