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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Srirangan Madhavan <smadhavan@nvidia.com>
Subject: [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method
Date: Tue, 22 Sep 2026 08:39:23 +0000	[thread overview]
Message-ID: <20260922083924.2451158-15-smadhavan@nvidia.com> (raw)
In-Reply-To: <20260922083924.2451158-1-smadhavan@nvidia.com>

Register cxl_reset with the PCI reset-method interface and place it before
FLR, which does not reset CXL.cache or CXL.mem protocol state.

Return -ENOTTY when device capabilities, function scope, cached HDM state,
or required cache synchronization do not permit a safe reset.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 drivers/cxl/core/resource.c | 8 ++++----
 drivers/pci/pci.c           | 2 ++
 include/linux/pci.h         | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
index 79ed12ecea81..6bf503e498e1 100644
--- a/drivers/cxl/core/resource.c
+++ b/drivers/cxl/core/resource.c
@@ -1225,9 +1225,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
 
 	rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CAP, &cap);
 	if (rc)
-		return pcibios_err_to_errno(rc);
+		return probe ? -ENOTTY : pcibios_err_to_errno(rc);
 	if (PCI_POSSIBLE_ERROR(cap))
-		return -ENODEV;
+		return probe ? -ENOTTY : -ENODEV;
 	if (!(cap & PCI_DVSEC_CXL_CACHE_CAPABLE) ||
 	    !(cap & PCI_DVSEC_CXL_MEM_CAPABLE) ||
 	    !(cap & PCI_DVSEC_CXL_RST_CAPABLE) ||
@@ -1236,9 +1236,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
 
 	rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL, &ctrl);
 	if (rc)
-		return pcibios_err_to_errno(rc);
+		return probe ? -ENOTTY : pcibios_err_to_errno(rc);
 	if (PCI_POSSIBLE_ERROR(ctrl))
-		return -ENODEV;
+		return probe ? -ENOTTY : -ENODEV;
 	if (!(ctrl & PCI_DVSEC_CXL_CACHE_ENABLE) ||
 	    !(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
 		return -ENOTTY;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fe611340f5ab..dc57a202c91f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -35,6 +35,7 @@
 #include <linux/aer.h>
 #include <linux/bitfield.h>
 #include <linux/suspend.h>
+#include <cxl/cxl.h>
 #include "pci.h"
 
 DEFINE_MUTEX(pci_slot_mutex);
@@ -5148,6 +5149,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods[] = {
 	{ },
 	{ pci_dev_specific_reset, .name = "device_specific" },
 	{ pci_dev_acpi_reset, .name = "acpi" },
+	{ cxl_reset_function, .name = "cxl_reset" },
 	{ pcie_reset_flr, .name = "flr" },
 	{ pci_af_flr, .name = "af_flr" },
 	{ pci_pm_reset, .name = "pm" },
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7bb37fcb556d..743b57ff885a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -52,7 +52,7 @@
 			       PCI_STATUS_PARITY)
 
 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
-#define PCI_NUM_RESET_METHODS 8
+#define PCI_NUM_RESET_METHODS 9
 
 #define PCI_RESET_PROBE		true
 #define PCI_RESET_DO_RESET	false
-- 
2.43.0


  parent reply	other threads:[~2026-09-22  8:40 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22  8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-22  8:41   ` sashiko-bot
2026-09-24  1:16   ` Jonathan Cameron
2026-09-24 16:23   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:21     ` Jonathan Cameron
2026-09-24 16:55       ` Dave Jiang
2026-10-01 22:33       ` Srirangan Madhavan
2026-09-24  1:22   ` Jonathan Cameron
2026-10-01 22:28     ` Srirangan Madhavan
2026-09-24 17:01   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-22  8:50   ` sashiko-bot
2026-09-24  1:29   ` Jonathan Cameron
2026-10-01 23:40     ` Srirangan Madhavan
2026-09-24 17:02   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-22  8:48   ` sashiko-bot
2026-09-24  1:31   ` Jonathan Cameron
2026-09-24 17:03   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:35     ` Jonathan Cameron
2026-10-01 22:43     ` Srirangan Madhavan
2026-09-24  2:45   ` Jonathan Cameron
2026-10-01 23:42     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-22  8:54   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  2:49     ` Jonathan Cameron
2026-10-01 22:46     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-22  8:55   ` sashiko-bot
2026-09-24  3:05   ` Jonathan Cameron
2026-10-01 23:52     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 22:58     ` Srirangan Madhavan
2026-09-24  3:08   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-22  8:54   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 23:14     ` Srirangan Madhavan
2026-09-24  3:36   ` Jonathan Cameron
2026-10-01 23:55     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-22  8:49   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24 17:29     ` Dave Jiang
2026-10-01 23:36     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-22  8:51   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 23:25     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-22  8:56   ` sashiko-bot
2026-09-23 21:41   ` Cheatham, Benjamin
2026-09-24 17:33     ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-22  8:55   ` sashiko-bot
2026-09-24  3:50   ` Jonathan Cameron
2026-10-01 23:58     ` Srirangan Madhavan
2026-09-22  8:39 ` Srirangan Madhavan [this message]
2026-09-22  9:02   ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method sashiko-bot
2026-09-22  8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-09-22  9:01   ` sashiko-bot

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