All of lore.kernel.org
 help / color / mirror / Atom feed
From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Srirangan Madhavan <smadhavan@nvidia.com>
Subject: [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset
Date: Tue, 22 Sep 2026 08:39:24 +0000	[thread overview]
Message-ID: <20260922083924.2451158-16-smadhavan@nvidia.com> (raw)
In-Reply-To: <20260922083924.2451158-1-smadhavan@nvidia.com>

CXL bus reset can clear HDM decoder programming and CXL Device DVSEC
control state. Restore the cached state after a successful cxl_bus reset
while IOMMU exclusion remains active.

Restore PCI configuration first so HDM MMIO is accessible, and preserve a
disabled state if restoration fails.

Tested-by: Richard Cheng <icheng@nvidia.com>
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 drivers/cxl/core/resource.c | 23 +++++++++++++++++++++--
 drivers/pci/pci.c           |  8 ++++++++
 include/cxl/cxl.h           | 17 +++++++++++++++++
 3 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
index 6bf503e498e1..0af0f96d5526 100644
--- a/drivers/cxl/core/resource.c
+++ b/drivers/cxl/core/resource.c
@@ -601,12 +601,12 @@ static int cxl_restore_hdm_decoder(struct pci_dev *pdev, void __iomem *hdm,
 	return 0;
 }
 
-static int cxl_snapshot_hdm(struct pci_dev *pdev,
-			    struct cxl_hdm_info **snapshot)
+int cxl_snapshot_hdm(struct pci_dev *pdev, struct cxl_hdm_info **snapshot)
 {
 	struct cxl_hdm_info *info;
 	size_t size;
 
+	device_lock_assert(&pdev->dev);
 	guard(rwsem_read)(&cxl_rwsem.dpa);
 	info = pdev->hdm;
 	if (!info)
@@ -762,6 +762,25 @@ static int cxl_reset_save_restored_state(struct pci_dev *pdev, u16 command)
 	return rc;
 }
 
+int cxl_restore_state_after_pci_reset(struct pci_dev *pdev,
+				      struct cxl_hdm_info *snapshot)
+{
+	u16 command;
+	int rc;
+
+	device_lock_assert(&pdev->dev);
+	guard(rwsem_write)(&cxl_rwsem.region);
+
+	cxl_restore_pci_state_for_hdm_restore(pdev, &command);
+	rc = cxl_restore_state(pdev, snapshot);
+	if (rc) {
+		cxl_reset_save_disabled_state(pdev);
+		return rc;
+	}
+
+	return cxl_reset_save_restored_state(pdev, command);
+}
+
 /*
  * CXL r4.0 sec 9.7.2 defines the reset completion timeout encodings.
  * Sec 9.7.3 leaves config-space access behavior undefined for 100 ms after
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index dc57a202c91f..6928c99aa785 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5015,6 +5015,7 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
 
 static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
 {
+	struct cxl_hdm_info *snapshot __free(kfree) = NULL;
 	struct pci_dev *bridge;
 	u16 dvsec, reg, val;
 	int rc;
@@ -5037,6 +5038,10 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
 	if (rc)
 		return -ENOTTY;
 
+	rc = cxl_snapshot_hdm(dev, &snapshot);
+	if (rc && rc != -ENXIO)
+		return rc;
+
 	rc = pci_dev_reset_iommu_prepare(dev);
 	if (rc) {
 		pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc);
@@ -5057,6 +5062,9 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
 		pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL,
 				      reg);
 
+	if (!rc && snapshot)
+		rc = cxl_restore_state_after_pci_reset(dev, snapshot);
+
 	pci_dev_reset_iommu_done(dev);
 	return rc;
 }
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index a07dbf7463c0..2ff5bb117942 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -202,6 +202,9 @@ struct cxl_register_map {
 #ifdef CONFIG_CXL_RESET
 void pci_cxl_hdm_cache_init(struct pci_dev *pdev);
 void pci_cxl_hdm_cache_release(struct pci_dev *pdev);
+int cxl_snapshot_hdm(struct pci_dev *pdev, struct cxl_hdm_info **snapshot);
+int cxl_restore_state_after_pci_reset(struct pci_dev *pdev,
+				      struct cxl_hdm_info *snapshot);
 int cxl_reset_function(struct pci_dev *pdev, bool probe);
 #else
 static inline void pci_cxl_hdm_cache_init(struct pci_dev *pdev)
@@ -212,6 +215,20 @@ static inline void pci_cxl_hdm_cache_release(struct pci_dev *pdev)
 {
 }
 
+static inline int cxl_snapshot_hdm(struct pci_dev *pdev,
+				   struct cxl_hdm_info **snapshot)
+{
+	*snapshot = NULL;
+	return -ENXIO;
+}
+
+static inline int
+cxl_restore_state_after_pci_reset(struct pci_dev *pdev,
+				  struct cxl_hdm_info *snapshot)
+{
+	return 0;
+}
+
 static inline int cxl_reset_function(struct pci_dev *pdev, bool probe)
 {
 	return -ENOTTY;
-- 
2.43.0


  parent reply	other threads:[~2026-09-22  8:40 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22  8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-22  8:41   ` sashiko-bot
2026-09-24  1:16   ` Jonathan Cameron
2026-09-24 16:23   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:21     ` Jonathan Cameron
2026-09-24 16:55       ` Dave Jiang
2026-10-01 22:33       ` Srirangan Madhavan
2026-09-24  1:22   ` Jonathan Cameron
2026-10-01 22:28     ` Srirangan Madhavan
2026-09-24 17:01   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-22  8:50   ` sashiko-bot
2026-09-24  1:29   ` Jonathan Cameron
2026-10-01 23:40     ` Srirangan Madhavan
2026-09-24 17:02   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-22  8:48   ` sashiko-bot
2026-09-24  1:31   ` Jonathan Cameron
2026-09-24 17:03   ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:35     ` Jonathan Cameron
2026-10-01 22:43     ` Srirangan Madhavan
2026-09-24  2:45   ` Jonathan Cameron
2026-10-01 23:42     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-22  8:54   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  2:49     ` Jonathan Cameron
2026-10-01 22:46     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-22  8:55   ` sashiko-bot
2026-09-24  3:05   ` Jonathan Cameron
2026-10-01 23:52     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-22  8:47   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 22:58     ` Srirangan Madhavan
2026-09-24  3:08   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-22  8:54   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 23:14     ` Srirangan Madhavan
2026-09-24  3:36   ` Jonathan Cameron
2026-10-01 23:55     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-22  8:49   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24 17:29     ` Dave Jiang
2026-10-01 23:36     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-22  8:51   ` sashiko-bot
2026-09-23 21:40   ` Cheatham, Benjamin
2026-10-01 23:25     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-22  8:56   ` sashiko-bot
2026-09-23 21:41   ` Cheatham, Benjamin
2026-09-24 17:33     ` Dave Jiang
2026-09-22  8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-22  8:55   ` sashiko-bot
2026-09-24  3:50   ` Jonathan Cameron
2026-10-01 23:58     ` Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22  9:02   ` sashiko-bot
2026-09-22  8:39 ` Srirangan Madhavan [this message]
2026-09-22  9:01   ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset sashiko-bot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260922083924.2451158-16-smadhavan@nvidia.com \
    --to=smadhavan@nvidia.com \
    --cc=alex.williamson@redhat.com \
    --cc=alison.schofield@intel.com \
    --cc=alwilliamson@nvidia.com \
    --cc=bhelgaas@google.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=icheng@nvidia.com \
    --cc=ira.weiny@intel.com \
    --cc=jan@nvidia.com \
    --cc=jic23@kernel.org \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=mhonap@nvidia.com \
    --cc=skancherla@nvidia.com \
    --cc=vaslot@nvidia.com \
    --cc=vishal.l.verma@intel.com \
    --cc=vsethi@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.