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From: Linus Walleij <linusw@kernel.org>
To: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>
Cc: dmaengine@vger.kernel.org, phone-devel@vger.kernel.org,
	 Linus Walleij <linusw@kernel.org>,
	sashiko-bot@kernel.org
Subject: [PATCH v5 11/23] dmaengine: ste_dma40: Fix DMA registration unwind
Date: Wed, 23 Sep 2026 01:30:56 +0200	[thread overview]
Message-ID: <20260923-dma40-fixes-v5-11-709d160cde76@kernel.org> (raw)
In-Reply-To: <20260923-dma40-fixes-v5-0-709d160cde76@kernel.org>

d40_dmaengine_init() registers DMAengine devices using devres-managed
unregister actions. If probe fails after one of those registrations, the
DMAengine devices stay visible until devres unwinds after d40_probe()
returns.

The channel tasklets are also initialized before each DMAengine device is
registered. An interrupt can therefore have queued a tasklet by the time a
later registration step fails, but unregistering the DMAengine devices
does not drain that tasklet before probe-owned storage is released.

Add tasklet cleanup actions to the DMAengine registration devres group.
On failure, free the IRQ before releasing the group so no new tasklets can
be scheduled, then unregister the DMAengine devices and drain their
tasklets before freeing the remaining probe resources. Keep the managed
registrations and cleanup actions in place on successful probe by removing
only the temporary group markers.

Fixes: 42ae6f1695be ("dmaengine: ste_dma40: Remove platform data")
Reported-by: sashiko-bot@kernel.org
Closes: https://lore.kernel.org/dmaengine/20260819225215.5EA2F1F000E9@smtp.kernel.org/
Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 drivers/dma/ste_dma40.c | 46 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 0782becdab11..3f5b25933ff5 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3047,6 +3047,18 @@ static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
 	}
 }
 
+static void d40_kill_tasklets(void *data)
+{
+	struct dma_device *dma = data;
+	struct d40_chan *d40c;
+	struct dma_chan *chan;
+
+	list_for_each_entry(chan, &dma->channels, device_node) {
+		d40c = container_of(chan, struct d40_chan, chan);
+		tasklet_kill(&d40c->tasklet);
+	}
+}
+
 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
 {
 	if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) {
@@ -3093,6 +3105,11 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 
 	d40_ops_init(base, &base->dma_slave);
 
+	err = devm_add_action_or_reset(base->dev, d40_kill_tasklets,
+				       &base->dma_slave);
+	if (err)
+		goto exit;
+
 	err = dmaenginem_async_device_register(&base->dma_slave);
 
 	if (err) {
@@ -3108,6 +3125,11 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 
 	d40_ops_init(base, &base->dma_memcpy);
 
+	err = devm_add_action_or_reset(base->dev, d40_kill_tasklets,
+				       &base->dma_memcpy);
+	if (err)
+		goto exit;
+
 	err = dmaenginem_async_device_register(&base->dma_memcpy);
 
 	if (err) {
@@ -3125,6 +3147,12 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 	dma_cap_set(DMA_CYCLIC, base->dma_both.cap_mask);
 
 	d40_ops_init(base, &base->dma_both);
+
+	err = devm_add_action_or_reset(base->dev, d40_kill_tasklets,
+				       &base->dma_both);
+	if (err)
+		goto exit;
+
 	err = dmaenginem_async_device_register(&base->dma_both);
 
 	if (err) {
@@ -3722,6 +3750,7 @@ static int __init d40_probe(struct platform_device *pdev)
 	struct d40_base *base;
 	struct resource *res;
 	struct resource res_lcpa;
+	void *dmaenginem_reg_group;
 	int num_reserved_chans;
 	bool runtime_pm_enabled = false;
 	bool irq_requested = false;
@@ -3855,20 +3884,33 @@ static int __init d40_probe(struct platform_device *pdev)
 	d40_hw_init(base);
 	enable_irq(base->irq);
 
+	dmaenginem_reg_group = devres_open_group(dev, NULL, GFP_KERNEL);
+	if (!dmaenginem_reg_group) {
+		ret = -ENOMEM;
+		goto destroy_cache;
+	}
+
 	ret = d40_dmaengine_init(base, num_reserved_chans);
 	if (ret)
-		goto destroy_cache;
+		goto release_dmaenginem;
 
 	ret = of_dma_controller_register(np, d40_xlate, NULL);
 	if (ret) {
 		dev_err(dev,
 			"could not register of_dma_controller\n");
-		goto destroy_cache;
+		goto release_dmaenginem;
 	}
+	devres_remove_group(dev, dmaenginem_reg_group);
 
 	dev_info(base->dev, "initialized\n");
 	return 0;
 
+ release_dmaenginem:
+	if (irq_requested) {
+		free_irq(base->irq, base);
+		irq_requested = false;
+	}
+	devres_release_group(dev, dmaenginem_reg_group);
  destroy_cache:
 	if (base->lcla_pool.dma_addr)
 		dma_unmap_single(base->dev, base->lcla_pool.dma_addr,

-- 
2.55.0


  parent reply	other threads:[~2026-09-22 23:31 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 23:30 [PATCH v5 00/23] dmaengine: ste_dma40: Fix numerous accumulated bugs Linus Walleij
2026-09-22 23:30 ` [PATCH v5 01/23] dmaengine: ste_dma40: Fix physical cyclic capability Linus Walleij
2026-09-22 23:30 ` [PATCH v5 02/23] dmaengine: ste_dma40: Fix cyclic transfer residue Linus Walleij
2026-09-22 23:30 ` [PATCH v5 03/23] dmaengine: ste_dma40: Recover coalesced cyclic callbacks Linus Walleij
2026-09-22 23:30 ` [PATCH v5 04/23] dmaengine: ste_dma40: Fix failed start cleanup Linus Walleij
2026-09-22 23:30 ` [PATCH v5 05/23] dmaengine: ste_dma40: Fix probe runtime PM disable Linus Walleij
2026-09-22 23:30 ` [PATCH v5 06/23] dmaengine: ste_dma40: Check runtime PM in IRQ Linus Walleij
2026-09-22 23:30 ` [PATCH v5 07/23] dmaengine: ste_dma40: Handle runtime PM resume errors Linus Walleij
2026-09-22 23:30 ` [PATCH v5 08/23] dmaengine: ste_dma40: Return IRQ_NONE when no interrupt is pending Linus Walleij
2026-09-22 23:41   ` sashiko-bot
2026-09-22 23:30 ` [PATCH v5 09/23] dmaengine: ste_dma40: Init hardware before registration Linus Walleij
2026-09-22 23:30 ` [PATCH v5 10/23] dmaengine: ste_dma40: Fix probe IRQ leak Linus Walleij
2026-09-22 23:30 ` Linus Walleij [this message]
2026-09-22 23:30 ` [PATCH v5 12/23] dmaengine: ste_dma40: Fix LCLA allocation order Linus Walleij
2026-09-22 23:30 ` [PATCH v5 13/23] dmaengine: ste_dma40: Fix probe LCLA free Linus Walleij
2026-09-22 23:30 ` [PATCH v5 14/23] dmaengine: ste_dma40: Put the LCPA SRAM node Linus Walleij
2026-09-22 23:31 ` [PATCH v5 15/23] dmaengine: ste_dma40: Fix memcpy channel parsing Linus Walleij
2026-09-22 23:31 ` [PATCH v5 16/23] dmaengine: ste_dma40: Validate disabled channel indexes Linus Walleij
2026-09-22 23:31 ` [PATCH v5 17/23] dmaengine: ste_dma40: Validate DMA specifier length Linus Walleij
2026-09-22 23:31 ` [PATCH v5 18/23] dmaengine: ste_dma40: Reject direction changes after allocation Linus Walleij
2026-09-22 23:31 ` [PATCH v5 19/23] dmaengine: ste_dma40: Fix logical channel bounds check Linus Walleij
2026-09-22 23:31 ` [PATCH v5 20/23] dmaengine: ste_dma40: Fix event group bounds Linus Walleij
2026-09-22 23:31 ` [PATCH v5 21/23] dmaengine: ste_dma40: Search all blocks for fixed logical channels Linus Walleij
2026-09-22 23:31 ` [PATCH v5 22/23] dmaengine: ste_dma40: Validate fixed physical channel indexes Linus Walleij
2026-09-22 23:31 ` [PATCH v5 23/23] dmaengine: ste_dma40: Validate memcpy configuration Linus Walleij
2026-09-22 23:34 ` [PATCH v5 00/23] dmaengine: ste_dma40: Fix numerous accumulated bugs Linus Walleij
  -- strict thread matches above, loose matches on Subject: below --
2026-09-20 18:59 Linus Walleij
2026-09-20 18:59 ` [PATCH v5 11/23] dmaengine: ste_dma40: Fix DMA registration unwind Linus Walleij

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