All of lore.kernel.org
 help / color / mirror / Atom feed
From: Linus Walleij <linusw@kernel.org>
To: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>
Cc: dmaengine@vger.kernel.org, phone-devel@vger.kernel.org,
	 Linus Walleij <linusw@kernel.org>
Subject: [PATCH v5 03/23] dmaengine: ste_dma40: Recover coalesced cyclic callbacks
Date: Wed, 23 Sep 2026 01:30:48 +0200	[thread overview]
Message-ID: <20260923-dma40-fixes-v5-3-709d160cde76@kernel.org> (raw)
In-Reply-To: <20260923-dma40-fixes-v5-0-709d160cde76@kernel.org>

DMA40 has one terminal-count status bit per channel, so cyclic period
interrupts can coalesce.

Use the memory-side pointer displacement to queue the minimum observable
number of callbacks. If sampling fails, queue one callback and invalidate
the saved position; the next successful sample resynchronizes without
recounting it.

The pointer is modulo the cyclic buffer: a displacement of d periods can
mean d plus n complete iterations of the buffer. Report d, so the driver
could have missed n iterations of the buffer; DMA40 has no counter to
recover them. For an unchanged pointer, report one callback rather than
risk a spurious full-buffer burst.

This condition has not been seen in practice and is only a product of
review comments that the buffer can miss interrupts.

The preceding cyclic-residue fix ensures that every cyclic period fits in
one LLI, so each boundary corresponds to one client callback.

Fixes: 0c842b551063 ("dma40: cyclic xfer support")
Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 drivers/dma/ste_dma40.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index eab9c09b4bfe..7384a50cb895 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -384,11 +384,14 @@ struct d40_lli_pool {
  * @cyclic_dma_addr: Start address of the cyclic buffer.
  * @cyclic_buf_len: Length of the cyclic buffer.
  * @cyclic_residue: Last valid cyclic residue sample.
+ * @cyclic_period_len: Length of one cyclic period.
+ * @cyclic_callback_pos: Position after the callbacks already queued.
  * @txd: DMA engine struct. Used for among other things for communication
  * during a transfer.
  * @node: List entry.
  * @is_in_client_list: true if the client owns this descriptor.
  * @cyclic: true if this is a cyclic job
+ * @cyclic_callback_pos_valid: Whether cyclic_callback_pos is reliable.
  *
  * This descriptor is used for both logical and physical transfers.
  */
@@ -405,12 +408,15 @@ struct d40_desc {
 	dma_addr_t			 cyclic_dma_addr;
 	size_t				 cyclic_buf_len;
 	size_t				 cyclic_residue;
+	size_t				 cyclic_period_len;
+	size_t				 cyclic_callback_pos;
 
 	struct dma_async_tx_descriptor	 txd;
 	struct list_head		 node;
 
 	bool				 is_in_client_list;
 	bool				 cyclic;
+	bool				 cyclic_callback_pos_valid;
 };
 
 /**
@@ -1487,6 +1493,64 @@ static bool d40_cyclic_offset(struct d40_chan *d40c, struct d40_desc *d40d,
 	return false;
 }
 
+static unsigned int d40_cyclic_periods_elapsed(struct d40_chan *d40c,
+					       struct d40_desc *d40d)
+{
+	size_t current_pos;
+	size_t offset;
+	unsigned int periods;
+
+	if (!d40d->cyclic_period_len)
+		return 1;
+
+	if (!d40_cyclic_offset(d40c, d40d, &offset)) {
+		d40d->cyclic_callback_pos_valid = false;
+		return 1;
+	}
+
+	current_pos = rounddown(offset, d40d->cyclic_period_len);
+	if (!d40_residue(d40c) && current_pos != offset)
+		current_pos += d40d->cyclic_period_len;
+	if (current_pos == d40d->cyclic_buf_len)
+		current_pos = 0;
+
+	if (!d40d->cyclic_callback_pos_valid) {
+		/*
+		 * The previous interrupt was reported without a pointer
+		 * sample. Resynchronize without using the stale position,
+		 * which would count that callback again.
+		 */
+		d40d->cyclic_callback_pos = current_pos;
+		d40d->cyclic_callback_pos_valid = true;
+		return 1;
+	}
+
+	/*
+	 * The pointer wraps with the cyclic buffer, so its displacement is
+	 * only the minimum number of elapsed periods. Complete buffer laps
+	 * are not observable.
+	 */
+	if (current_pos > d40d->cyclic_callback_pos) {
+		periods = (current_pos - d40d->cyclic_callback_pos) /
+			d40d->cyclic_period_len;
+	} else if (current_pos < d40d->cyclic_callback_pos) {
+		periods = (d40d->cyclic_buf_len -
+			d40d->cyclic_callback_pos + current_pos) /
+			d40d->cyclic_period_len;
+	} else {
+		/*
+		 * The TC status is a single latched bit. An unchanged pointer
+		 * cannot distinguish a complete lap from a repeated interrupt,
+		 * so do not amplify it into a buffer's worth of callbacks.
+		 */
+		periods = 1;
+	}
+
+	d40d->cyclic_callback_pos = current_pos;
+
+	return periods;
+}
+
 static bool d40_tx_is_linked(struct d40_chan *d40c)
 {
 	bool is_link;
@@ -1609,6 +1673,7 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
 static void dma_tc_handle(struct d40_chan *d40c)
 {
 	struct d40_desc *d40d;
+	unsigned int callbacks = 1;
 
 	/* Get first active entry from list */
 	d40d = d40_first_active_get(d40c);
@@ -1633,6 +1698,8 @@ static void dma_tc_handle(struct d40_chan *d40c)
 			if (d40d->lli_current == d40d->lli_len)
 				d40d->lli_current = 0;
 		}
+
+		callbacks = d40_cyclic_periods_elapsed(d40c, d40d);
 	} else {
 		d40_lcla_free_all(d40c, d40d);
 
@@ -1653,7 +1720,7 @@ static void dma_tc_handle(struct d40_chan *d40c)
 		d40_desc_done(d40c, d40d);
 	}
 
-	d40c->pending_tx++;
+	d40c->pending_tx += callbacks;
 	tasklet_schedule(&d40c->tasklet);
 
 }
@@ -2638,6 +2705,9 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
 		desc->cyclic_dma_addr = buf_addr;
 		desc->cyclic_buf_len = buf_len;
 		desc->cyclic_residue = buf_len;
+		desc->cyclic_period_len = period_len;
+		desc->cyclic_callback_pos = 0;
+		desc->cyclic_callback_pos_valid = true;
 	}
 
 	kfree(sg);

-- 
2.55.0


  parent reply	other threads:[~2026-09-22 23:30 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 23:30 [PATCH v5 00/23] dmaengine: ste_dma40: Fix numerous accumulated bugs Linus Walleij
2026-09-22 23:30 ` [PATCH v5 01/23] dmaengine: ste_dma40: Fix physical cyclic capability Linus Walleij
2026-09-22 23:30 ` [PATCH v5 02/23] dmaengine: ste_dma40: Fix cyclic transfer residue Linus Walleij
2026-09-22 23:30 ` Linus Walleij [this message]
2026-09-22 23:30 ` [PATCH v5 04/23] dmaengine: ste_dma40: Fix failed start cleanup Linus Walleij
2026-09-22 23:30 ` [PATCH v5 05/23] dmaengine: ste_dma40: Fix probe runtime PM disable Linus Walleij
2026-09-22 23:30 ` [PATCH v5 06/23] dmaengine: ste_dma40: Check runtime PM in IRQ Linus Walleij
2026-09-22 23:30 ` [PATCH v5 07/23] dmaengine: ste_dma40: Handle runtime PM resume errors Linus Walleij
2026-09-22 23:30 ` [PATCH v5 08/23] dmaengine: ste_dma40: Return IRQ_NONE when no interrupt is pending Linus Walleij
2026-09-22 23:41   ` sashiko-bot
2026-09-22 23:30 ` [PATCH v5 09/23] dmaengine: ste_dma40: Init hardware before registration Linus Walleij
2026-09-22 23:30 ` [PATCH v5 10/23] dmaengine: ste_dma40: Fix probe IRQ leak Linus Walleij
2026-09-22 23:30 ` [PATCH v5 11/23] dmaengine: ste_dma40: Fix DMA registration unwind Linus Walleij
2026-09-22 23:30 ` [PATCH v5 12/23] dmaengine: ste_dma40: Fix LCLA allocation order Linus Walleij
2026-09-22 23:30 ` [PATCH v5 13/23] dmaengine: ste_dma40: Fix probe LCLA free Linus Walleij
2026-09-22 23:30 ` [PATCH v5 14/23] dmaengine: ste_dma40: Put the LCPA SRAM node Linus Walleij
2026-09-22 23:31 ` [PATCH v5 15/23] dmaengine: ste_dma40: Fix memcpy channel parsing Linus Walleij
2026-09-22 23:31 ` [PATCH v5 16/23] dmaengine: ste_dma40: Validate disabled channel indexes Linus Walleij
2026-09-22 23:31 ` [PATCH v5 17/23] dmaengine: ste_dma40: Validate DMA specifier length Linus Walleij
2026-09-22 23:31 ` [PATCH v5 18/23] dmaengine: ste_dma40: Reject direction changes after allocation Linus Walleij
2026-09-22 23:31 ` [PATCH v5 19/23] dmaengine: ste_dma40: Fix logical channel bounds check Linus Walleij
2026-09-22 23:31 ` [PATCH v5 20/23] dmaengine: ste_dma40: Fix event group bounds Linus Walleij
2026-09-22 23:31 ` [PATCH v5 21/23] dmaengine: ste_dma40: Search all blocks for fixed logical channels Linus Walleij
2026-09-22 23:31 ` [PATCH v5 22/23] dmaengine: ste_dma40: Validate fixed physical channel indexes Linus Walleij
2026-09-22 23:31 ` [PATCH v5 23/23] dmaengine: ste_dma40: Validate memcpy configuration Linus Walleij
2026-09-22 23:34 ` [PATCH v5 00/23] dmaengine: ste_dma40: Fix numerous accumulated bugs Linus Walleij
  -- strict thread matches above, loose matches on Subject: below --
2026-09-20 18:59 Linus Walleij
2026-09-20 18:59 ` [PATCH v5 03/23] dmaengine: ste_dma40: Recover coalesced cyclic callbacks Linus Walleij
2026-09-21 21:51   ` Frank Li
2026-09-22 21:13     ` Linus Walleij

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260923-dma40-fixes-v5-3-709d160cde76@kernel.org \
    --to=linusw@kernel.org \
    --cc=Frank.Li@kernel.org \
    --cc=dmaengine@vger.kernel.org \
    --cc=phone-devel@vger.kernel.org \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.