arch/x86/coco/sev/core.c:996:69-74: opportunity for str_write_read(write)

arch/x86/coco/sev/core.c:996:69-74: opportunity for str_write_read(write)

[kernel test robot]

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Melody Wang <huibo.wang@amd.com>
CC: 0day robot <lkp@intel.com>

tree:   https://github.com/intel-lab-lkp/linux/commits/Melody-Wang/x86-sev-Make-SVSM-calls-preemption-safe/20260914-005717
head:   65dbde829c5e2d48b15dbe2c9d605d1f1ddbe691
commit: f00a21f19691e20aa2ed7fdfc46805cc7510d9da x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation
date:   10 days ago
:::::: branch date: 10 days ago
:::::: commit date: 10 days ago
config: x86_64-randconfig-2103-20260923 (https://download.01.org/0day-ci/archive/20260923/202609231726.xTdfsvWe-lkp@intel.com/config)
compiler: clang version 22.1.8 (https://github.com/llvm/llvm-project ca7933e47d3a3451d81e72ac174dcb5aa28b59d1)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202609231726.xTdfsvWe-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> arch/x86/coco/sev/core.c:996:69-74: opportunity for str_write_read(write)

vim +996 arch/x86/coco/sev/core.c

39336f4ffb2478 arch/x86/kernel/sev-es.c Tom Lendacky    2020-09-07   974  
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   975  static u64 __sev_apic_ghcb_msr_rw(u32 reg, u64 value, bool write)
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   976  {
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   977  	u64 msr = APIC_BASE_MSR + (reg >> 4);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   978  	struct pt_regs regs = { .cx = msr };
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   979  	struct es_em_ctxt ctxt = { .regs = &regs };
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   980  	struct ghcb_state state;
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   981  	enum es_result res;
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   982  	struct ghcb *ghcb;
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   983  
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   984  	if (write) {
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   985  		regs.ax = lower_32_bits(value);
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   986  		regs.dx = upper_32_bits(value);
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   987  	}
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   988  
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   989  	guard(irqsave)();
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   990  
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   991  	ghcb = __sev_get_ghcb(&state);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   992  	vc_ghcb_invalidate(ghcb);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   993  
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   994  	res = __vc_handle_msr(ghcb, &ctxt, write);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   995  	if (res != ES_OK) {
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14  @996  		pr_err("APIC MSR via GHCB (0x%llx) %s returned error (%d)\n", msr, write ? "write" : "read", res);
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   997  		/* MSR read/write failures are treated as fatal errors */
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14   998  		sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28   999  	}
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1000  
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1001  	__sev_put_ghcb(&state);
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1002  
f00a21f19691e2 arch/x86/coco/sev/core.c Melody Wang     2026-09-14  1003  	/* The return value will be ignored by the caller for a write */
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1004  	return regs.ax | regs.dx << 32;
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1005  }
ea7d792e11e10f arch/x86/coco/sev/core.c Neeraj Upadhyay 2025-08-28  1006  

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