Re: [PATCH v12 09/12] clk: zte: Introduce a driver for zx297520v3 matrix clocks - sashiko-bot

From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: lee@kernel.org, vkoul@kernel.org, linux-phy@lists.infradead.org,
	neil.armstrong@linaro.org, linux-clk@vger.kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	mfd@lists.linux.dev, robh@kernel.org, olteanv@gmail.com
Subject: Re: [PATCH v12 09/12] clk: zte: Introduce a driver for zx297520v3 matrix clocks
Date: Wed, 23 Sep 2026 18:40:50 +0000	[thread overview]
Message-ID: <20260923184051.0BA291F0089E@smtp.kernel.org> (raw)
In-Reply-To: <20260923-zx29clk-v12-9-9c243796b6d2@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: zte: missing DT export for ZX297520V3_RFFE_WCLK
--

commit 4d2c5025ee60ae5cdf0e636caff70b2cdc8a3e60
Author: Stefan Dösinger <stefandoesinger@gmail.com>

clk: zte: Introduce a driver for zx297520v3 matrix clocks

This clock controller controls high speed devices: CPU, DMA, RAM, SDIO,
Ethernet. The only non-clock, non-reset registers I have spotted here
are hardware spinlocks.

> diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx297520v3.c
> index 68bfeab84d745..92b56571b1556 100644
> --- a/drivers/clk/zte/clk-zx297520v3.c
> +++ b/drivers/clk/zte/clk-zx297520v3.c

[ ... ]

> +static const unsigned int zx297520v3_matrix_exports[] = {
> +	[ZX297520V3_SYS_TIMER_WCLK] =		ZX_CLK_SYS_TIMER_WCLK,
> +	[ZX297520V3_CPU_WCLK] =			ZX_CLK_CPU_WCLK,

[ ... ]

> +	[ZX297520V3_PDCFG_WCLK] =		ZX_CLK_PDCFG_WCLK,
> +	[ZX297520V3_PDCFG_PCLK] =		ZX_CLK_PDCFG_PCLK,
> +	[ZX297520V3_SSC_WCLK] =			ZX_CLK_SSC_WCLK,
> +	[ZX297520V3_SSC_PCLK] =			ZX_CLK_SSC_PCLK,

[Severity: Medium]
Is the mapping for ZX297520V3_RFFE_WCLK intentionally missing from
zx297520v3_matrix_exports?

Because this mapping is omitted, any device querying for the RFFE work clock
via the device tree will be silently mapped to index 0. This index corresponds
to the ZX_CLK_MATRIX_OSC26M_D4 clock rather than the intended rffe-wclk.

Could this incorrect mapping break the LTE radio hardware and potentially
disrupt actual consumers of the 6.5 MHz matrix-osc26m-d4 clock when a driver
probes and operates on the hardware block?

> +	[ZX297520V3_AXI_WCLK] =			ZX_CLK_AXI_WCLK,
> +	[ZX297520V3_GMAC_WCLK] =		ZX_CLK_GMAC_WCLK,
> +	[ZX297520V3_GMAC_PCLK] =		ZX_CLK_GMAC_PCLK,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923-zx29clk-v12-0-9c243796b6d2@gmail.com?part=9

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