From: Ryan Chen <ryan_chen@aspeedtech.com>
To: Stefan Schaeckeler <sschaeck@cisco.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Borislav Petkov <bp@alien8.de>, Tony Luck <tony.luck@intel.com>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
<linux-edac@vger.kernel.org>, Borislav Petkov <bp@suse.de>,
Ryan Chen <ryan_chen@aspeedtech.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Subject: [PATCH v4 5/9] dt-bindings: edac: aspeed: Add AST2700 SDRAM EDAC
Date: Wed, 30 Sep 2026 13:15:03 +0800 [thread overview]
Message-ID: <20260930-edac-v4-5-c2e526f3ed79@aspeedtech.com> (raw)
In-Reply-To: <20260930-edac-v4-0-c2e526f3ed79@aspeedtech.com>
Add the "aspeed,ast2700-sdram-edac" compatible and note DDR5 support.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
index 09735826d707..685b6815f293 100644
--- a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
+++ b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
@@ -10,8 +10,9 @@ maintainers:
- Stefan Schaeckeler <sschaeck@cisco.com>
description: >
- The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
- correction check).
+ The Aspeed BMC SoCs support DDR memory with and without ECC (error
+ correction check): DDR3 and DDR4 on the AST2400, AST2500 and AST2600,
+ and DDR4 and DDR5 on the AST2700.
The memory controller supports SECDED (single bit error correction, double bit
error detection) and single bit error auto scrubbing by reserving 8 bits for
@@ -25,6 +26,7 @@ properties:
- aspeed,ast2400-sdram-edac
- aspeed,ast2500-sdram-edac
- aspeed,ast2600-sdram-edac
+ - aspeed,ast2700-sdram-edac
reg:
maxItems: 1
--
2.34.1
next prev parent reply other threads:[~2026-09-30 5:15 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 5:14 [PATCH v4 0/9] Add Aspeed AST2700 SDRAM EDAC support Ryan Chen
2026-09-30 5:14 ` [PATCH v4 1/9] EDAC/aspeed: Set the DIMM grain Ryan Chen
2026-09-30 5:15 ` [PATCH v4 2/9] EDAC/aspeed: Free the interrupt before the mem_ctl_info on remove Ryan Chen
2026-10-04 21:21 ` Borislav Petkov
2026-10-05 3:00 ` Ryan Chen
2026-09-30 5:15 ` [PATCH v4 3/9] EDAC/aspeed: Clean up whitespace and include ordering Ryan Chen
2026-09-30 5:15 ` [PATCH v4 4/9] EDAC/aspeed: Free the mem_ctl_info unconditionally on remove Ryan Chen
2026-09-30 5:15 ` Ryan Chen [this message]
2026-09-30 5:15 ` [PATCH v4 6/9] EDAC/aspeed: Replace regmap with direct register access Ryan Chen
2026-09-30 5:25 ` sashiko-bot
2026-09-30 5:15 ` [PATCH v4 7/9] EDAC/aspeed: Abstract SoC differences behind chip data Ryan Chen
2026-09-30 5:15 ` [PATCH v4 8/9] EDAC/aspeed: Add AST2700 support Ryan Chen
2026-09-30 5:15 ` [PATCH v4 9/9] MAINTAINERS: Step down as Aspeed AST2500 EDAC driver maintainer Ryan Chen
2026-09-30 5:20 ` sashiko-bot
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