[PATCH 23/26] powerpc: mpc85xx: Remove BSC9131 support

[Bradley Morgan <brads@mainlining.org>]

NXP marks each BSC9131 part number End of Life. No target selects
ARCH_BSC9131, so its mux, LAW and reset register paths have no users.

Remove that family support.

Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
 arch/Kconfig.nxp                      |   3 +-
 arch/powerpc/cpu/mpc85xx/Kconfig      |  22 +----
 arch/powerpc/cpu/mpc8xxx/cpu.c        |   1 -
 arch/powerpc/include/asm/fsl_law.h    |   4 -
 arch/powerpc/include/asm/immap_85xx.h | 116 --------------------------
 board/nxp/common/sdhc_boot.c          |   2 +-
 boot/Kconfig                          |   2 +-
 drivers/mmc/Kconfig                   |   2 +-
 8 files changed, 6 insertions(+), 146 deletions(-)

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 15e56ffb35a..e52ed3ddb21 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -286,8 +286,7 @@ config SYS_FSL_IFC_BANK_COUNT
 	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
 		ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
 		ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
-		ARCH_T2080 || ARCH_P1010 || ARCH_BSC9131
-	default 3 if ARCH_BSC9131
+		ARCH_T2080 || ARCH_P1010
 	default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
 			ARCH_B4420 || ARCH_P1010
 	default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6cb37b8a378..6d5e81f47ac 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -281,22 +281,6 @@ config ARCH_B4860
 	imply CMD_NAND
 	imply CMD_REGINFO
 
-config ARCH_BSC9131
-	bool
-	select FSL_LAW
-	select SYS_FSL_DDR_VER_44
-	select SYS_FSL_ERRATUM_A004477
-	select SYS_FSL_ERRATUM_A005125
-	select SYS_FSL_ERRATUM_ESDHC111
-	select SYS_FSL_HAS_DDR3
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_BE
-	select SYS_FSL_SEC_COMPAT_4
-	select FSL_IFC
-	imply CMD_EEPROM
-	imply CMD_NAND
-	imply CMD_REGINFO
-
 config ARCH_MPC8544
 	bool
 	select BTB
@@ -699,8 +683,7 @@ config MAX_CPUS
 
 config SYS_CCSRBAR_DEFAULT
 	hex "Default CCSRBAR address"
-	default	0xff700000 if	ARCH_BSC9131	|| \
-				ARCH_MPC8544	|| \
+	default	0xff700000 if	ARCH_MPC8544	|| \
 				ARCH_P1010	|| \
 				ARCH_P1020	|| \
 				ARCH_P1021	|| \
@@ -904,8 +887,7 @@ config SYS_FSL_NUM_LAWS
 	default 16 if	ARCH_T1024	|| \
 			ARCH_T1040	|| \
 			ARCH_T1042
-	default 12 if	ARCH_BSC9131	|| \
-			ARCH_P1010	|| \
+	default 12 if	ARCH_P1010	|| \
 			ARCH_P1020	|| \
 			ARCH_P1021	|| \
 			ARCH_P2020
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 3840cb42b76..8ebef9d5991 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -77,7 +77,6 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(T2080, T2080, 0),
 	CPU_TYPE_ENTRY(T2081, T2081, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
-	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9232, 9232, 2),
 	CPU_TYPE_ENTRY(C291, C291, 1),
 	CPU_TYPE_ENTRY(C292, C292, 1),
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index bdef61bc80f..ce40fe31742 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -79,12 +79,8 @@ enum law_trgt_if {
 	LAW_TRGT_IF_PCI = 0x00,
 	LAW_TRGT_IF_PCI_2 = 0x01,
 	LAW_TRGT_IF_PCIE_1 = 0x02,
-#if defined(CONFIG_ARCH_BSC9131)
-	LAW_TRGT_IF_OCN_DSP = 0x03,
-#else
 #if !defined(CONFIG_ARCH_P2020)
 	LAW_TRGT_IF_PCIE_3 = 0x03,
-#endif
 #endif
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index e1167dbb3d7..45f96fefc62 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1726,11 +1726,7 @@ typedef struct ccsr_rcpm {
 #else
 typedef struct ccsr_gur {
 	u32	porpllsr;	/* POR PLL ratio status */
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
-#else
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
-#endif
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
 #define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
@@ -1846,50 +1842,6 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE10		0x00000020
 #define MPC85xx_PMUXCR_QE11		0x00000010
 #define MPC85xx_PMUXCR_QE12		0x00000008
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
-#define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
-#define MPC85xx_PMUXCR_TSEC2_1588_PPS		0x10000000
-#define MPC85xx_PMUXCR_TSEC2_1588_RSVD		0x30000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO		0x04000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
-#define MPC85xx_PMUXCR_IFC_AD15_GPIO		0x01000000
-#define MPC85xx_PMUXCR_IFC_AD15_TIMER2		0x02000000
-#define MPC85xx_PMUXCR_IFC_AD16_GPO8		0x00400000
-#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0		0x00800000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO		0x00100000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
-#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
-#define MPC85xx_PMUXCR_IFC_CS2_GPO65		0x00040000
-#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
-#define MPC85xx_PMUXCR_SDHC_USIM		0x00010000
-#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
-#define MPC85xx_PMUXCR_SDHC_GPIO77		0x00030000
-#define MPC85xx_PMUXCR_SDHC_RESV		0x00004000
-#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
-#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
-#define MPC85xx_PMUXCR_USB_CLK_UART_SIN		0x00001000
-#define MPC85xx_PMUXCR_USB_CLK_GPIO69		0x00002000
-#define MPC85xx_PMUXCR_USB_CLK_TIMER3		0x00003000
-#define MPC85xx_PMUXCR_USB_UART_GPIO0		0x00000400
-#define MPC85xx_PMUXCR_USB_RSVD			0x00000C00
-#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
-#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
-#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
-#define MPC85xx_PMUXCR_USB_D1_2_RSVD		0x00000300
-#define MPC85xx_PMUXCR_USB_DIR_GPIO2		0x00000040
-#define MPC85xx_PMUXCR_USB_DIR_TIMER1		0x00000080
-#define MPC85xx_PMUXCR_USB_DIR_MCP_B		0x000000C0
-#define MPC85xx_PMUXCR_SPI1_UART3		0x00000010
-#define MPC85xx_PMUXCR_SPI1_SIM			0x00000020
-#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
-#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
-#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
-#define MPC85xx_PMUXCR_SPI1_CS2_GPO75		0x0000000C
-#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
-#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
-#define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
-#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_ARCH_P1010)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
@@ -1916,68 +1868,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
 #endif
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0x40000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0x80000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
-#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
-#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
-#define MPC85xx_PMUXCR2_ANT1_TIMER5			0x00100000
-#define MPC85xx_PMUXCR2_ANT1_TSEC_1588			0x00200000
-#define MPC85xx_PMUXCR2_ANT1_GPIO95_19			0x00300000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
-#define MPC85xx_PMUXCR2_ANT2_RSVD			0x00000100
-#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
-#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
-#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
-#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
-#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
-#define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
-#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
-	u32	pmuxcr3;
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
-#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
-#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
-#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93			0x00100000
-#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
-#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
-#define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
-	u32 pmuxcr4;
-#else
 	u8	res6[8];
-#endif
 	u32	devdisr;	/* Device disable control */
 #define MPC85xx_DEVDISR_PCI1		0x80000000
 #define MPC85xx_DEVDISR_PCI2		0x40000000
@@ -2027,14 +1918,7 @@ typedef struct ccsr_gur {
 	u32	ddrdllcr;	/* DDR DLL control */
 	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
-#if defined(CONFIG_ARCH_BSC9131)
-	u8	res15[12];
-	u32	halt_req_mask;
-#define HALTED_TO_HALT_REQ_MASK_0	0x80000000
-	u8	res18[232];
-#else
 	u8	res15[248];
-#endif
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
diff --git a/board/nxp/common/sdhc_boot.c b/board/nxp/common/sdhc_boot.c
index 16b6f0fc343..d49064f23f0 100644
--- a/board/nxp/common/sdhc_boot.c
+++ b/board/nxp/common/sdhc_boot.c
@@ -45,7 +45,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u64 *env_addr)
 
 #ifdef CONFIG_ESDHC_HC_BLK_ADDR
 	/*
-	 * On P1010 and BSC9131:
+	 * On P1010:
 	 * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
 	 * code length of these soc specify the memory address in block address
 	 * format. Block length is fixed to 512 bytes as per the SD High
diff --git a/boot/Kconfig b/boot/Kconfig
index 0fc550c3e01..63828e5e005 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1199,7 +1199,7 @@ config FSL_FIXED_MMC_LOCATION
 
 config ESDHC_HC_BLK_ADDR
 	def_bool y
-	depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_P1010)
+	depends on FSL_FIXED_MMC_LOCATION && ARCH_P1010
 	help
 	  In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
 	  code length of these soc specify the memory address in block address
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 671cae7aaf2..7a690721b91 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -911,7 +911,7 @@ config FSL_SDHC_V2_3
 config FSL_ESDHC
 	bool "Freescale/NXP eSDHC controller support"
 	depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || PPC
-	select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131
+	select FSL_SDHC_V2_3 if ARCH_P1010
 	help
 	  This selects support for the eSDHC (Enhanced Secure Digital Host
 	  Controller) found on numerous Freescale/NXP SoCs.
-- 
2.47.3