From: Bin Meng <bin.meng@processmission.com>
To: QEMU <qemu-devel@nongnu.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v4 08/27] tests/qtest: Add SiFive L2 cache controller coverage
Date: Wed, 14 Oct 2026 09:22:48 +0800 [thread overview]
Message-ID: <20261014012323.322790-9-bin.meng@processmission.com> (raw)
In-Reply-To: <20261014012323.322790-1-bin.meng@processmission.com>
Exercise Config, WayEnable, and indexed WayMask registers on the
PolarFire and FU540 integrations, including their different master
counts, reset, monotonic writes, and unimplemented-register logging.
Verify that enabling cache ways hides the corresponding LIM range,
while the controller's Zero window stays accessible. Check that reset
restores hidden LIM data without clearing the Zero RAM stand-in.
Migrate register state and both RAM backings, verify the destination
LIM view, and confirm that writes to hidden addresses do not alter the
data restored by a later reset.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
---
(no changes since v3)
Changes in v3:
- Rename the test for the shared SiFive L2CC model
- Exercise 15 masters on PolarFire and 21 masters on FU540
MAINTAINERS | 1 +
tests/qtest/sifive_l2cc_test.c | 306 +++++++++++++++++++++++++++++++++
tests/qtest/meson.build | 3 +
3 files changed, 310 insertions(+)
create mode 100644 tests/qtest/sifive_l2cc_test.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1312bbd1bd..acb79a7d61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1827,6 +1827,7 @@ F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
F: tests/functional/riscv64/test_sifive_u.py
+F: tests/qtest/sifive_l2cc_test.c
Tenstorrent Machines
M: Joel Stanley <joel@jms.id.au>
diff --git a/tests/qtest/sifive_l2cc_test.c b/tests/qtest/sifive_l2cc_test.c
new file mode 100644
index 0000000000..fef80f3438
--- /dev/null
+++ b/tests/qtest/sifive_l2cc_test.c
@@ -0,0 +1,306 @@
+/*
+ * QTest testcase for the SiFive L2 cache controller
+ *
+ * Copyright (c) 2026 Process Mission
+ *
+ * Author:
+ * Bin Meng <bin.meng@processmission.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "libqtest.h"
+#include "migration/migration-qmp.h"
+#include "migration/migration-util.h"
+
+#define L2CC_BASE 0x02010000
+#define L2CC_CONFIG 0x000
+#define L2CC_CONFIG_VALUE 0x06091004
+#define L2CC_WAY_ENABLE 0x008
+#define L2CC_ECC_INJECT 0x040
+#define L2CC_FLUSH64 0x200
+#define L2CC_WAY_MASK_BASE 0x800
+#define L2CC_WAY_MASK_COUNT 15
+#define L2CC_MAX_MASTERS 21
+#define L2CC_WAY_MASK(n) (L2CC_WAY_MASK_BASE + 8 * (n))
+#define L2CC_MASTER15 L2CC_WAY_MASK(L2CC_WAY_MASK_COUNT)
+#define L2CC_WAY_ENABLE_RESET 0
+#define L2CC_WAY_MASK_RESET UINT64_MAX
+
+#define L2_LIM_BASE 0x08000000
+#define L2_WAY_SIZE (128 * KiB)
+#define L2_LIM_RESET_WAYS 15
+#define L2_ZERO_BASE 0x0a000000
+#define L2_ZERO_SIZE (2 * MiB)
+
+static QTestState *sifive_l2cc_start(const char *firmware)
+{
+ return qtest_initf("-machine microchip-icicle-kit -smp 5 -m 2G "
+ "-bios \"%s\"", firmware);
+}
+
+static char *sifive_l2cc_create_firmware(void)
+{
+ static const uint8_t firmware[] = {
+ 0x13, 0x00, 0x00, 0x00,
+ 0x6f, 0x00, 0x00, 0x00,
+ };
+ char *path;
+ int fd;
+ ssize_t written;
+
+ fd = g_file_open_tmp("sifive_l2cc_XXXXXX", &path, NULL);
+ g_assert_cmpint(fd, >=, 0);
+
+ written = write(fd, firmware, sizeof(firmware));
+ g_assert_cmpint(written, ==, sizeof(firmware));
+ close(fd);
+
+ return path;
+}
+
+static uint64_t l2cc_way_mask_test_value(unsigned int master)
+{
+ return UINT64_C(0xfedcba9876543201) + master;
+}
+
+static void test_l2cc_registers(void)
+{
+ g_autofree char *firmware = sifive_l2cc_create_firmware();
+ QTestState *qts = sifive_l2cc_start(firmware);
+ unsigned int i;
+
+ unlink(firmware);
+
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+ qtest_writel(qts, L2CC_BASE + L2CC_CONFIG, UINT32_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xd);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xd);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 3);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xd);
+ qtest_writeq(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xf);
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xf);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 0xe);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0xf);
+
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ qtest_writeq(qts, L2CC_BASE + L2CC_WAY_MASK(i),
+ l2cc_way_mask_test_value(i));
+ }
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ l2cc_way_mask_test_value(i));
+ }
+
+ qtest_system_reset(qts);
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_CONFIG), ==,
+ L2CC_CONFIG_VALUE);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ for (i = 0; i < L2CC_WAY_MASK_COUNT; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ }
+
+ qtest_quit(qts);
+}
+
+static void test_l2lim_topology(void)
+{
+ g_autofree char *firmware = sifive_l2cc_create_firmware();
+ uint32_t original[L2_LIM_RESET_WAYS];
+ const uint32_t poison = 0xdeadc0de;
+ const uint64_t zero_last = L2_ZERO_BASE + L2_ZERO_SIZE - 4;
+ QTestState *qts = sifive_l2cc_start(firmware);
+ unsigned int i;
+
+ unlink(firmware);
+
+ /* Check the fixed aperture, not the RAM stand-in's eviction behavior */
+ qtest_writel(qts, zero_last, 0xa55a9669);
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0xa55a9669);
+
+ for (i = 1; i <= L2_LIM_RESET_WAYS; i++) {
+ uint64_t l2lim_size = (L2_LIM_RESET_WAYS - i) * L2_WAY_SIZE;
+ uint64_t hidden = L2_LIM_BASE + l2lim_size;
+ uint32_t tail = 0x96000000 | i;
+
+ original[i - 1] = 0x69000000 | i;
+ qtest_writel(qts, hidden, original[i - 1]);
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, original[i - 1]);
+
+ if (l2lim_size) {
+ qtest_writel(qts, hidden - 4, tail);
+ g_assert_cmphex(qtest_readl(qts, hidden - 4), ==, tail);
+ }
+
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, i);
+ g_assert_cmphex(qtest_readb(qts,
+ L2CC_BASE + L2CC_WAY_ENABLE), ==, i);
+ if (l2lim_size) {
+ g_assert_cmphex(qtest_readl(qts, hidden - 4), ==, tail);
+ }
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, 0);
+ qtest_writel(qts, hidden, poison);
+ g_assert_cmphex(qtest_readl(qts, hidden), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0xa55a9669);
+ }
+
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, UINT8_MAX);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ UINT8_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2_LIM_BASE), ==, 0);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 3);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ UINT8_MAX);
+ g_assert_cmphex(qtest_readl(qts, L2_LIM_BASE), ==, 0);
+
+ qtest_system_reset(qts);
+ g_assert_cmphex(qtest_readb(qts, L2CC_BASE + L2CC_WAY_ENABLE), ==,
+ L2CC_WAY_ENABLE_RESET);
+ for (i = 1; i <= L2_LIM_RESET_WAYS; i++) {
+ uint64_t restored = L2_LIM_BASE +
+ (L2_LIM_RESET_WAYS - i) * L2_WAY_SIZE;
+
+ g_assert_cmphex(qtest_readl(qts, restored), ==, original[i - 1]);
+ }
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0xa55a9669);
+
+ qtest_quit(qts);
+}
+
+static void test_l2cc_master_count(void)
+{
+ g_autofree char *firmware = sifive_l2cc_create_firmware();
+ QTestState *qts = qtest_initf(
+ "-machine sifive_u -smp 5 -bios \"%s\"", firmware);
+ const uint64_t zero_last = L2_ZERO_BASE + L2_ZERO_SIZE - 4;
+ unsigned int i;
+
+ unlink(firmware);
+
+ for (i = 0; i < L2CC_MAX_MASTERS; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ qtest_writeq(qts, L2CC_BASE + L2CC_WAY_MASK(i),
+ l2cc_way_mask_test_value(i));
+ }
+ for (i = 0; i < L2CC_MAX_MASTERS; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ l2cc_way_mask_test_value(i));
+ }
+ g_assert_cmphex(qtest_readq(qts,
+ L2CC_BASE + L2CC_WAY_MASK(L2CC_MAX_MASTERS)),
+ ==, 0);
+ qtest_writel(qts, zero_last, 0x12345678);
+ qtest_writel(qts, L2_ZERO_BASE + L2_ZERO_SIZE, 0xdeadc0de);
+ g_assert_cmphex(qtest_readl(qts, L2_ZERO_BASE + L2_ZERO_SIZE), ==, 0);
+ qtest_writeb(qts, L2CC_BASE + L2CC_WAY_ENABLE, 15);
+ g_assert_cmphex(qtest_readl(qts, zero_last), ==, 0x12345678);
+ g_assert_cmphex(qtest_readl(qts, L2_LIM_BASE), ==, 0);
+
+ qtest_system_reset(qts);
+ for (i = 0; i < L2CC_MAX_MASTERS; i++) {
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_WAY_MASK(i)), ==,
+ L2CC_WAY_MASK_RESET);
+ }
+ qtest_quit(qts);
+}
+
+static void test_l2cc_migration(void)
+{
+ g_autofree char *firmware = sifive_l2cc_create_firmware();
+ QTestState *from = sifive_l2cc_start(firmware);
+ QTestState *to = qtest_initf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G "
+ "-bios \"%s\" -incoming defer", firmware);
+ const uint64_t hidden = L2_LIM_BASE + 8 * L2_WAY_SIZE;
+ const uint64_t zero_last = L2_ZERO_BASE + L2_ZERO_SIZE - 4;
+
+ unlink(firmware);
+
+ qtest_writel(from, L2_LIM_BASE, 0x11223344);
+ qtest_writel(from, hidden, 0x55667788);
+ qtest_writel(from, zero_last, 0x99aabbcc);
+ qtest_writeb(from, L2CC_BASE + L2CC_WAY_ENABLE, 7);
+ qtest_writeq(from, L2CC_BASE + L2CC_WAY_MASK(14), 0x1234);
+ g_assert_cmphex(qtest_readl(from, hidden), ==, 0);
+
+ migrate_incoming_qmp(to, "tcp:127.0.0.1:0", NULL, "{}");
+ migrate_qmp(from, to, NULL, NULL, "{}");
+ wait_for_migration_complete(from);
+
+ g_assert_cmphex(qtest_readb(to, L2CC_BASE + L2CC_WAY_ENABLE), ==, 7);
+ g_assert_cmphex(qtest_readq(to, L2CC_BASE + L2CC_WAY_MASK(14)), ==, 0x1234);
+ g_assert_cmphex(qtest_readl(to, L2_LIM_BASE), ==, 0x11223344);
+ g_assert_cmphex(qtest_readl(to, hidden), ==, 0);
+ qtest_writel(to, hidden, 0xdeadc0de);
+ g_assert_cmphex(qtest_readl(to, zero_last), ==, 0x99aabbcc);
+
+ qtest_system_reset(to);
+ g_assert_cmphex(qtest_readb(to, L2CC_BASE + L2CC_WAY_ENABLE), ==, 0);
+ g_assert_cmphex(qtest_readl(to, hidden), ==, 0x55667788);
+ g_assert_cmphex(qtest_readl(to, zero_last), ==, 0x99aabbcc);
+
+ qtest_quit(from);
+ qtest_quit(to);
+}
+
+static void test_l2cc_unimplemented(void)
+{
+ g_autofree char *firmware = sifive_l2cc_create_firmware();
+ g_autofree char *log_path = NULL;
+ g_autofree char *log = NULL;
+ QTestState *qts;
+ int fd;
+
+ fd = g_file_open_tmp("sifive_l2cc_unimp_XXXXXX", &log_path, NULL);
+ g_assert_cmpint(fd, >=, 0);
+ close(fd);
+
+ qts = qtest_initf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G -bios \"%s\" "
+ "-d unimp -D \"%s\"", firmware, log_path);
+ unlink(firmware);
+
+ g_assert_cmphex(qtest_readl(qts, L2CC_BASE + L2CC_ECC_INJECT), ==, 0);
+ qtest_writeq(qts, L2CC_BASE + L2CC_FLUSH64, 0x1234);
+ g_assert_cmphex(qtest_readq(qts, L2CC_BASE + L2CC_MASTER15), ==, 0);
+ qtest_quit(qts);
+
+ g_assert_true(g_file_get_contents(log_path, &log, NULL, NULL));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device read (size 4, offset 0x40)"));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device write (size 8, value 0x1234, offset 0x200)"));
+ g_assert_nonnull(strstr(log,
+ "unimplemented device read (size 8, offset 0x878)"));
+ unlink(log_path);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ if (qtest_has_machine("microchip-icicle-kit")) {
+ qtest_add_func("/sifive_l2cc/registers", test_l2cc_registers);
+ qtest_add_func("/sifive_l2cc/l2lim_topology", test_l2lim_topology);
+ qtest_add_func("/sifive_l2cc/unimplemented", test_l2cc_unimplemented);
+ qtest_add_func("/sifive_l2cc/migration", test_l2cc_migration);
+ }
+ if (qtest_has_machine("sifive_u")) {
+ qtest_add_func("/sifive_l2cc/master_count", test_l2cc_master_count);
+ }
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 200abf6f36..1fe008c9ed 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -311,6 +311,7 @@ qtests_riscv32 = \
qtests_riscv64 = ['riscv-csr-test'] + \
(unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_SIFIVE_L2CC') ? ['sifive_l2cc_test'] : []) + \
(config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and
config_all_devices.has_key('CONFIG_RISCV_IOMMU') ?
['iommu-riscv-test'] : []) + \
@@ -427,6 +428,8 @@ qtests = {
'erst-test': files('erst-test.c'),
'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'],
'migration-test': test_migration_files + migration_tls_files + migration_colo_files,
+ 'sifive_l2cc_test': files('migration/migration-qmp.c',
+ 'migration/migration-util.c'),
'pxe-test': files('boot-sector.c'),
'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c',
'pnv-xive2-nvpg_bar.c'),
--
2.53.0
next prev parent reply other threads:[~2026-10-14 1:24 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 1:22 [PATCH v4 00/27] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-10-14 1:22 ` [PATCH v4 01/27] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14 1:22 ` [PATCH v4 02/27] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-10-14 1:22 ` [PATCH v4 03/27] hw/misc: pfsoc: Support DDR training with newer HSS Bin Meng
2026-10-14 1:22 ` [PATCH v4 04/27] hw/misc: Add SiFive L2 cache controller model Bin Meng
2026-10-14 1:22 ` [PATCH v4 05/27] hw/riscv: pfsoc: Map the SiFive L2CC memory windows Bin Meng
2026-10-14 1:22 ` [PATCH v4 06/27] hw/riscv: sifive_u: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14 1:22 ` [PATCH v4 07/27] hw/riscv: sifive_u: Use the shared SiFive L2 cache controller Bin Meng
2026-10-14 1:22 ` Bin Meng [this message]
2026-10-14 1:22 ` [PATCH v4 09/27] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-10-14 1:22 ` [PATCH v4 10/27] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer Bin Meng
2026-10-14 1:22 ` [PATCH v4 11/27] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-10-14 1:22 ` [PATCH v4 12/27] hw/sd: cadence: Add 64-bit system bus property Bin Meng
2026-10-14 1:22 ` [PATCH v4 13/27] hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support Bin Meng
2026-10-14 1:22 ` [PATCH v4 14/27] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-10-14 1:22 ` [PATCH v4 15/27] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-10-14 1:22 ` [PATCH v4 16/27] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-10-14 1:22 ` [PATCH v4 17/27] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-10-14 1:22 ` [PATCH v4 18/27] hw/misc: pfsoc: Honor service notification requests Bin Meng
2026-10-14 1:22 ` [PATCH v4 19/27] hw/misc: pfsoc: Let IOSCB own service interrupt state Bin Meng
2026-10-14 1:23 ` [PATCH v4 20/27] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-10-14 1:23 ` [PATCH v4 21/27] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-10-14 1:23 ` [PATCH v4 22/27] hw/riscv: pfsoc: Default Icicle Kit to five harts Bin Meng
2026-10-14 1:23 ` [PATCH v4 23/27] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-10-14 1:23 ` [PATCH v4 24/27] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-10-14 1:23 ` [PATCH v4 25/27] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-10-14 1:23 ` [PATCH v4 26/27] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-10-14 1:23 ` [PATCH v4 27/27] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer Bin Meng
2026-10-14 4:16 ` Philippe Mathieu-Daudé
2026-10-14 8:06 ` Daniel P. Berrangé
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