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From: Bin Meng <bin.meng@processmission.com>
To: QEMU <qemu-devel@nongnu.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Chao Liu <chao.liu@processmission.com>,
	Conor Dooley <conor@kernel.org>,
	Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
	Sebastian Huber <sebastian.huber@embedded-brains.de>,
	Weiwei Li <liwei1518@gmail.com>,
	qemu-riscv@nongnu.org
Subject: [PATCH v4 22/27] hw/riscv: pfsoc: Default Icicle Kit to five harts
Date: Wed, 14 Oct 2026 09:23:02 +0800	[thread overview]
Message-ID: <20261014012323.322790-23-bin.meng@processmission.com> (raw)
In-Reply-To: <20261014012323.322790-1-bin.meng@processmission.com>

The Icicle Kit contains one E51 management hart and four U54 application
harts. Defaulting to two harts can accidentally boot firmware and a
device tree that expect the full five-hart topology.

Default to all five harts, while retaining the existing two-to-five
range for users intentionally configuring fewer application harts.
Document that firmware and device trees must match the selected count.

Signed-off-by: Bin Meng <bin.meng@processmission.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>

---

(no changes since v3)

Changes in v3:
- Change only the default hart count and retain the minimum of two
- Document reduced topologies and matching firmware requirements

 docs/system/riscv/microchip-icicle-kit.rst | 3 +++
 hw/riscv/microchip_pfsoc.c                 | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
index b0ad24f174..138289a913 100644
--- a/docs/system/riscv/microchip-icicle-kit.rst
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -27,6 +27,9 @@ The ``microchip-icicle-kit`` machine supports the following devices:
 * 1 SDHC storage controller
 
 The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected.
+The machine defaults to all five harts. ``-smp`` may select two to five harts,
+with one E51 and one to four U54 cores. The firmware and device tree must match
+the selected topology; the HSS boot flow below uses all five harts.
 
 Boot options
 ------------
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 855c719f76..9d8e5916e7 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -752,7 +752,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc,
     mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
                    MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
     mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
-    mc->default_cpus = mc->min_cpus;
+    mc->default_cpus = mc->max_cpus;
     mc->default_ram_id = "microchip.icicle.kit.ram";
     mc->auto_create_sdcard = true;
 
-- 
2.53.0



  parent reply	other threads:[~2026-10-14  1:29 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-14  1:22 [PATCH v4 00/27] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-10-14  1:22 ` [PATCH v4 01/27] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14  1:22 ` [PATCH v4 02/27] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-10-14  1:22 ` [PATCH v4 03/27] hw/misc: pfsoc: Support DDR training with newer HSS Bin Meng
2026-10-14  1:22 ` [PATCH v4 04/27] hw/misc: Add SiFive L2 cache controller model Bin Meng
2026-10-14  1:22 ` [PATCH v4 05/27] hw/riscv: pfsoc: Map the SiFive L2CC memory windows Bin Meng
2026-10-14  1:22 ` [PATCH v4 06/27] hw/riscv: sifive_u: Correct the L2LIM maximum mapped size Bin Meng
2026-10-14  1:22 ` [PATCH v4 07/27] hw/riscv: sifive_u: Use the shared SiFive L2 cache controller Bin Meng
2026-10-14  1:22 ` [PATCH v4 08/27] tests/qtest: Add SiFive L2 cache controller coverage Bin Meng
2026-10-14  1:22 ` [PATCH v4 09/27] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-10-14  1:22 ` [PATCH v4 10/27] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer Bin Meng
2026-10-14  1:22 ` [PATCH v4 11/27] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-10-14  1:22 ` [PATCH v4 12/27] hw/sd: cadence: Add 64-bit system bus property Bin Meng
2026-10-14  1:22 ` [PATCH v4 13/27] hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support Bin Meng
2026-10-14  1:22 ` [PATCH v4 14/27] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-10-14  1:22 ` [PATCH v4 15/27] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-10-14  1:22 ` [PATCH v4 16/27] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-10-14  1:22 ` [PATCH v4 17/27] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-10-14  1:22 ` [PATCH v4 18/27] hw/misc: pfsoc: Honor service notification requests Bin Meng
2026-10-14  1:22 ` [PATCH v4 19/27] hw/misc: pfsoc: Let IOSCB own service interrupt state Bin Meng
2026-10-14  1:23 ` [PATCH v4 20/27] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-10-14  1:23 ` [PATCH v4 21/27] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-10-14  1:23 ` Bin Meng [this message]
2026-10-14  1:23 ` [PATCH v4 23/27] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-10-14  1:23 ` [PATCH v4 24/27] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-10-14  1:23 ` [PATCH v4 25/27] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-10-14  1:23 ` [PATCH v4 26/27] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-10-14  1:23 ` [PATCH v4 27/27] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer Bin Meng
2026-10-14  4:16   ` Philippe Mathieu-Daudé
2026-10-14  8:06     ` Daniel P. Berrangé

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