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From: George Neacsu <geocausa@gmail.com>
To: David Heidelberg <david@ixit.cz>
Cc: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	Loic Poulain <loic.poulain@oss.qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
	Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
	Suresh Vankadara <svankada@qti.qualcomm.com>,
	tjose@qti.qualcomm.com,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	linux-phy@lists.infradead.org, linux-media@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100
Date: Fri, 16 Oct 2026 17:08:58 +0100	[thread overview]
Message-ID: <20261016160858.193572-1-geocausa@gmail.com> (raw)
In-Reply-To: <6564f9f8-6ecd-4912-b029-c92dfba792c1@ixit.cz>

Hi David,

On 16/10/2026 16:10, David Heidelberg wrote:
>> +	{.reg_addr = CSIPHY_LN_CTRLn(1, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
>
> Thank you for the change. While the lane being decimal number is completely
> fine, I believe the register passed should stay in hex :)

Agreed. In the next version the macro will take the register offset
within the lane in hex, e.g. CSIPHY_LN_REG(1, 0x68), so each entry
reads like the downstream header. The object code stays the same.

Thanks,
George

WARNING: multiple messages have this Message-ID (diff)
From: George Neacsu <geocausa@gmail.com>
To: David Heidelberg <david@ixit.cz>
Cc: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	Loic Poulain <loic.poulain@oss.qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
	Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
	Suresh Vankadara <svankada@qti.qualcomm.com>,
	tjose@qti.qualcomm.com,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	linux-phy@lists.infradead.org, linux-media@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100
Date: Fri, 16 Oct 2026 17:08:58 +0100	[thread overview]
Message-ID: <20261016160858.193572-1-geocausa@gmail.com> (raw)
In-Reply-To: <6564f9f8-6ecd-4912-b029-c92dfba792c1@ixit.cz>

Hi David,

On 16/10/2026 16:10, David Heidelberg wrote:
>> +	{.reg_addr = CSIPHY_LN_CTRLn(1, 26), .reg_data = 0xf1, .param_type = CSIPHY_DEFAULT_PARAMS},
>
> Thank you for the change. While the lane being decimal number is completely
> fine, I believe the register passed should stay in hex :)

Agreed. In the next version the macro will take the register offset
within the lane in hex, e.g. CSIPHY_LN_REG(1, 0x68), so each entry
reads like the downstream header. The object code stays the same.

Thanks,
George

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-10-16 16:09 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16 14:56 [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100 George Neacsu via B4 Relay
2026-10-16 14:56 ` George Neacsu via B4 Relay
2026-10-16 14:56 ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 1/6] phy: Add MIPI C-PHY mode and configuration options George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 2/6] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 3/6] phy: qcom-mipi-csi2: Rename the D-PHY init sequence George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 4/6] phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 5/6] phy: qcom-mipi-csi2: Use fsleep() for init sequence delays George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 14:56 ` [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu via B4 Relay
2026-10-16 14:56   ` George Neacsu
2026-10-16 15:10   ` David Heidelberg
2026-10-16 15:10     ` David Heidelberg
2026-10-16 16:08     ` George Neacsu [this message]
2026-10-16 16:08       ` George Neacsu
2026-10-16 16:09 ` [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 16:09   ` Bryan O'Donoghue
2026-10-16 21:48   ` George Neacsu
2026-10-16 21:48     ` George Neacsu
2026-10-16 22:04     ` David Heidelberg
2026-10-16 22:04       ` David Heidelberg

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