* drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
@ 2026-10-18 7:48 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2026-10-18 7:48 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
Unfiltered warning: this smatch report is sent as-is and has not been
reviewed for false positives, so please treat it with due skepticism.
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
CC: "Borislav Petkov (AMD)" <bp@alien8.de>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 70dd4ee72eb2d5793c62e71c14e3aba78e5a4e56
commit: 62a9fc50e8d947601ea3484e732b1a65a0a54b96 EDAC/versalnet: Refactor memory controller initialization and cleanup
date: 8 months ago
:::::: branch date: 20 hours ago
:::::: commit date: 8 months ago
config: arm64-randconfig-r2202-20261017 (https://download.01.org/0day-ci/archive/20261017/202610171355.FpDCX5PE-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
smatch: v0.5.0-9187-g5189e3fb
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 62a9fc50e8d9 ("EDAC/versalnet: Refactor memory controller initialization and cleanup")
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202610171355.FpDCX5PE-lkp@intel.com/
smatch warnings:
drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
vim +785 drivers/edac/versalnet_edac.c
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 774
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 775 static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 776 {
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 777 u32 num_chans, rank, dwidth, config;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 778 struct edac_mc_layer layers[2];
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 779 struct mem_ctl_info *mci;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 780 struct device *dev;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 781 enum dev_type dt;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 782 char *name;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 783 int rc;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 784
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 @785 config = priv->adec[CONF + i * ADEC_NUM];
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 786 num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 787 rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 788 dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 789
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 790 switch (dwidth) {
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 791 case XDDR5_BUS_WIDTH_16:
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 792 dt = DEV_X16;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 793 break;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 794 case XDDR5_BUS_WIDTH_32:
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 795 dt = DEV_X32;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 796 break;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 797 case XDDR5_BUS_WIDTH_64:
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 798 dt = DEV_X64;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 799 break;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 800 default:
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 801 dt = DEV_UNKNOWN;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 802 }
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 803
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 804 if (dt == DEV_UNKNOWN)
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 805 return 0;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 806
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 807 /* Find the first enabled device and register that one. */
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 808 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 809 layers[0].size = rank;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 810 layers[0].is_virt_csrow = true;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 811 layers[1].type = EDAC_MC_LAYER_CHANNEL;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 812 layers[1].size = num_chans;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 813 layers[1].is_virt_csrow = false;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 814
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 815 rc = -ENOMEM;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 816 name = kzalloc(MC_NAME_LEN, GFP_KERNEL);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 817 if (!name)
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 818 return rc;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 819
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 820 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 821 if (!dev)
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 822 goto err_name_free;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 823
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 824 mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv));
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 825 if (!mci) {
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 826 edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 827 goto err_dev_free;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 828 }
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 829
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 830 sprintf(name, "versal-net-ddrmc5-edac-%d", i);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 831
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 832 dev->init_name = name;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 833 dev->release = versal_edac_release;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 834
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 835 rc = device_register(dev);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 836 if (rc)
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 837 goto err_mc_free;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 838
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 839 mci->pdev = dev;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 840 mc_init(mci, dev);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 841
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 842 rc = edac_mc_add_mc(mci);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 843 if (rc) {
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 844 edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 845 goto err_unreg;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 846 }
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 847
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 848 priv->mci[i] = mci;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 849 priv->dwidth = dt;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 850
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 851 platform_set_drvdata(pdev, priv);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 852
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 853 return 0;
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 854
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 855 err_unreg:
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 856 device_unregister(mci->pdev);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 857 err_mc_free:
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 858 edac_mc_free(mci);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 859 err_dev_free:
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 860 kfree(dev);
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 861 err_name_free:
62a9fc50e8d9476 Shubhrajyoti Datta 2025-11-04 862 kfree(name);
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 863
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 864 return rc;
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 865 }
d5fe2fec6c40dda Shubhrajyoti Datta 2025-09-08 866
:::::: The code at line 785 was first introduced by commit
:::::: d5fe2fec6c40dda03df8cc9b4a97de0b7e39f984 EDAC: Add a driver for the AMD Versal NET DDR controller
:::::: TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
:::::: CC: Borislav Petkov (AMD) <bp@alien8.de>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread* drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
@ 2026-06-06 4:27 kernel test robot
2026-06-26 5:35 ` Datta, Shubhrajyoti
0 siblings, 1 reply; 4+ messages in thread
From: kernel test robot @ 2026-06-06 4:27 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
CC: "Borislav Petkov (AMD)" <bp@alien8.de>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 8e65320d91cdc3b241d4b94855c88459b91abf66
commit: 62a9fc50e8d947601ea3484e732b1a65a0a54b96 EDAC/versalnet: Refactor memory controller initialization and cleanup
date: 3 months ago
:::::: branch date: 3 hours ago
:::::: commit date: 3 months ago
config: arm64-randconfig-r072-20260606 (https://download.01.org/0day-ci/archive/20260606/202606061200.j14yIFYw-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 8.5.0
smatch: v0.5.0-9185-gbcc58b9c
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 62a9fc50e8d9 ("EDAC/versalnet: Refactor memory controller initialization and cleanup")
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202606061200.j14yIFYw-lkp@intel.com/
smatch warnings:
drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
vim +785 drivers/edac/versalnet_edac.c
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 774
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 775 static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 776 {
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 777 u32 num_chans, rank, dwidth, config;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 778 struct edac_mc_layer layers[2];
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 779 struct mem_ctl_info *mci;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 780 struct device *dev;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 781 enum dev_type dt;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 782 char *name;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 783 int rc;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 784
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 @785 config = priv->adec[CONF + i * ADEC_NUM];
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 786 num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 787 rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 788 dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 789
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 790 switch (dwidth) {
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 791 case XDDR5_BUS_WIDTH_16:
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 792 dt = DEV_X16;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 793 break;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 794 case XDDR5_BUS_WIDTH_32:
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 795 dt = DEV_X32;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 796 break;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 797 case XDDR5_BUS_WIDTH_64:
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 798 dt = DEV_X64;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 799 break;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 800 default:
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 801 dt = DEV_UNKNOWN;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 802 }
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 803
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 804 if (dt == DEV_UNKNOWN)
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 805 return 0;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 806
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 807 /* Find the first enabled device and register that one. */
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 808 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 809 layers[0].size = rank;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 810 layers[0].is_virt_csrow = true;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 811 layers[1].type = EDAC_MC_LAYER_CHANNEL;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 812 layers[1].size = num_chans;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 813 layers[1].is_virt_csrow = false;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 814
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 815 rc = -ENOMEM;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 816 name = kzalloc(MC_NAME_LEN, GFP_KERNEL);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 817 if (!name)
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 818 return rc;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 819
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 820 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 821 if (!dev)
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 822 goto err_name_free;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 823
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 824 mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv));
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 825 if (!mci) {
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 826 edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 827 goto err_dev_free;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 828 }
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 829
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 830 sprintf(name, "versal-net-ddrmc5-edac-%d", i);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 831
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 832 dev->init_name = name;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 833 dev->release = versal_edac_release;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 834
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 835 rc = device_register(dev);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 836 if (rc)
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 837 goto err_mc_free;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 838
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 839 mci->pdev = dev;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 840 mc_init(mci, dev);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 841
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 842 rc = edac_mc_add_mc(mci);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 843 if (rc) {
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 844 edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 845 goto err_unreg;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 846 }
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 847
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 848 priv->mci[i] = mci;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 849 priv->dwidth = dt;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 850
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 851 platform_set_drvdata(pdev, priv);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 852
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 853 return 0;
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 854
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 855 err_unreg:
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 856 device_unregister(mci->pdev);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 857 err_mc_free:
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 858 edac_mc_free(mci);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 859 err_dev_free:
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 860 kfree(dev);
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 861 err_name_free:
62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 862 kfree(name);
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 863
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 864 return rc;
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 865 }
d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 866
:::::: The code at line 785 was first introduced by commit
:::::: d5fe2fec6c40dda03df8cc9b4a97de0b7e39f984 EDAC: Add a driver for the AMD Versal NET DDR controller
:::::: TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
:::::: CC: Borislav Petkov (AMD) <bp@alien8.de>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
2026-06-06 4:27 kernel test robot
@ 2026-06-26 5:35 ` Datta, Shubhrajyoti
2026-06-26 9:42 ` Dan Carpenter
0 siblings, 1 reply; 4+ messages in thread
From: Datta, Shubhrajyoti @ 2026-06-26 5:35 UTC (permalink / raw)
To: kernel test robot, oe-kbuild; +Cc: Dan Carpenter
On 6/6/2026 9:57 AM, kernel test robot wrote:
> BCC: lkp@intel.com
> CC: oe-kbuild-all@lists.linux.dev
> CC: linux-kernel@vger.kernel.org
> TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> CC: "Borislav Petkov (AMD)" <bp@alien8.de>
>
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
> head: 8e65320d91cdc3b241d4b94855c88459b91abf66
> commit: 62a9fc50e8d947601ea3484e732b1a65a0a54b96 EDAC/versalnet: Refactor memory controller initialization and cleanup
> date: 3 months ago
> :::::: branch date: 3 hours ago
> :::::: commit date: 3 months ago
> config: arm64-randconfig-r072-20260606 (https://download.01.org/0day-ci/archive/20260606/202606061200.j14yIFYw-lkp@intel.com/config)
> compiler: aarch64-linux-gcc (GCC) 8.5.0
> smatch: v0.5.0-9185-gbcc58b9c
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Fixes: 62a9fc50e8d9 ("EDAC/versalnet: Refactor memory controller initialization and cleanup")
> | Reported-by: kernel test robot <lkp@intel.com>
> | Reported-by: Dan Carpenter <error27@gmail.com>
> | Closes: https://lore.kernel.org/r/202606061200.j14yIFYw-lkp@intel.com/
>
> smatch warnings:
> drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
>
> vim +785 drivers/edac/versalnet_edac.c
>
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 774
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 775 static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
This is a static function called from
865 for (i = 0; i < NUM_CONTROLLERS; i++) {
866 rc = init_one_mc(priv, pdev, i);
867 if (rc) {
The NUM_CONTROLLERS is 8 so the value of i at max can be 8.
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 776 {
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 777 u32 num_chans, rank, dwidth, config;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 778 struct edac_mc_layer layers[2];
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 779 struct mem_ctl_info *mci;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 780 struct device *dev;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 781 enum dev_type dt;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 782 char *name;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 783 int rc;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 784
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 @785 config = priv->adec[CONF + i * ADEC_NUM];
The max offset can be 8*19 =152.
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 786 num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 787 rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 788 dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 789
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 790 switch (dwidth) {
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 791 case XDDR5_BUS_WIDTH_16:
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 792 dt = DEV_X16;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 793 break;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 794 case XDDR5_BUS_WIDTH_32:
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 795 dt = DEV_X32;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 796 break;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 797 case XDDR5_BUS_WIDTH_64:
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 798 dt = DEV_X64;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 799 break;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 800 default:
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 801 dt = DEV_UNKNOWN;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 802 }
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 803
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 804 if (dt == DEV_UNKNOWN)
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 805 return 0;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 806
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 807 /* Find the first enabled device and register that one. */
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 808 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 809 layers[0].size = rank;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 810 layers[0].is_virt_csrow = true;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 811 layers[1].type = EDAC_MC_LAYER_CHANNEL;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 812 layers[1].size = num_chans;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 813 layers[1].is_virt_csrow = false;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 814
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 815 rc = -ENOMEM;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 816 name = kzalloc(MC_NAME_LEN, GFP_KERNEL);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 817 if (!name)
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 818 return rc;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 819
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 820 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 821 if (!dev)
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 822 goto err_name_free;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 823
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 824 mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv));
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 825 if (!mci) {
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 826 edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 827 goto err_dev_free;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 828 }
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 829
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 830 sprintf(name, "versal-net-ddrmc5-edac-%d", i);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 831
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 832 dev->init_name = name;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 833 dev->release = versal_edac_release;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 834
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 835 rc = device_register(dev);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 836 if (rc)
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 837 goto err_mc_free;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 838
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 839 mci->pdev = dev;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 840 mc_init(mci, dev);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 841
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 842 rc = edac_mc_add_mc(mci);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 843 if (rc) {
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 844 edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 845 goto err_unreg;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 846 }
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 847
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 848 priv->mci[i] = mci;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 849 priv->dwidth = dt;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 850
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 851 platform_set_drvdata(pdev, priv);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 852
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 853 return 0;
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 854
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 855 err_unreg:
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 856 device_unregister(mci->pdev);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 857 err_mc_free:
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 858 edac_mc_free(mci);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 859 err_dev_free:
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 860 kfree(dev);
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 861 err_name_free:
> 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 862 kfree(name);
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 863
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 864 return rc;
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 865 }
> d5fe2fec6c40dd Shubhrajyoti Datta 2025-09-08 866
>
> :::::: The code at line 785 was first introduced by commit
> :::::: d5fe2fec6c40dda03df8cc9b4a97de0b7e39f984 EDAC: Add a driver for the AMD Versal NET DDR controller
>
> :::::: TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> :::::: CC: Borislav Petkov (AMD) <bp@alien8.de>
>
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
2026-06-26 5:35 ` Datta, Shubhrajyoti
@ 2026-06-26 9:42 ` Dan Carpenter
0 siblings, 0 replies; 4+ messages in thread
From: Dan Carpenter @ 2026-06-26 9:42 UTC (permalink / raw)
To: Datta, Shubhrajyoti; +Cc: kernel test robot, oe-kbuild
On Fri, Jun 26, 2026 at 11:05:11AM +0530, Datta, Shubhrajyoti wrote:
>
> On 6/6/2026 9:57 AM, kernel test robot wrote:
> > BCC: lkp@intel.com
> > CC: oe-kbuild-all@lists.linux.dev
> > CC: linux-kernel@vger.kernel.org
> > TO: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> > CC: "Borislav Petkov (AMD)" <bp@alien8.de>
> >
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
> > head: 8e65320d91cdc3b241d4b94855c88459b91abf66
> > commit: 62a9fc50e8d947601ea3484e732b1a65a0a54b96 EDAC/versalnet: Refactor memory controller initialization and cleanup
> > date: 3 months ago
> > :::::: branch date: 3 hours ago
> > :::::: commit date: 3 months ago
> > config: arm64-randconfig-r072-20260606 (https://download.01.org/0day-ci/archive/20260606/202606061200.j14yIFYw-lkp@intel.com/config)
> > compiler: aarch64-linux-gcc (GCC) 8.5.0
> > smatch: v0.5.0-9185-gbcc58b9c
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > the same patch/commit), kindly add following tags
> > | Fixes: 62a9fc50e8d9 ("EDAC/versalnet: Refactor memory controller initialization and cleanup")
> > | Reported-by: kernel test robot <lkp@intel.com>
> > | Reported-by: Dan Carpenter <error27@gmail.com>
> > | Closes: https://lore.kernel.org/r/202606061200.j14yIFYw-lkp@intel.com/
> >
> > smatch warnings:
> > drivers/edac/versalnet_edac.c:785 init_one_mc() error: buffer overflow 'priv->adec' 152 <= s32max
> >
> > vim +785 drivers/edac/versalnet_edac.c
> >
> > 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 774
> > 62a9fc50e8d947 Shubhrajyoti Datta 2025-11-04 775 static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i)
>
> This is a static function called from
>
> 865 for (i = 0; i < NUM_CONTROLLERS; i++) {
> 866 rc = init_one_mc(priv, pdev, i);
> 867 if (rc) {
>
> The NUM_CONTROLLERS is 8 so the value of i at max can be 8.
>
Yeah...
The zero day bot doesn't do cross function analysis. It cann't
scale well enough.
These warnings are normally filtered by a human before being resent, but
since you're using lei you get the unfiltered patches that didn't go out
to the public. As more and more people adopt lei, we should probably
stop sending unfiltered warnings to the list...
regards,
dan carpenter
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-10-18 7:52 UTC | newest]
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2026-06-26 5:35 ` Datta, Shubhrajyoti
2026-06-26 9:42 ` Dan Carpenter
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