[PATCH 08/14] hw/hexagon: add the SC8480XP NSP0 machine

[Brian Cain <brian.cain@oss.qualcomm.com>]

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 include/hw/hexagon/hexagon.h               |  1 +
 hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc | 52 +++++++++++++
 hw/hexagon/sc8480xp_nsp0.c                 | 90 ++++++++++++++++++++++
 tests/qtest/l2vic-test.c                   |  2 +
 tests/qtest/qcom-dsp-test.c                |  1 +
 tests/qtest/qct-qtimer-test.c              |  2 +
 hw/hexagon/Kconfig                         |  6 ++
 hw/hexagon/meson.build                     |  1 +
 8 files changed, 155 insertions(+)
 create mode 100644 hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc
 create mode 100644 hw/hexagon/sc8480xp_nsp0.c

diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h
index 1d0d55ea938..5f993214784 100644
--- a/include/hw/hexagon/hexagon.h
+++ b/include/hw/hexagon/hexagon.h
@@ -29,6 +29,7 @@ typedef enum {
     v73_rev = 0x8c73,
     v73m_rev = 0xcc73,
     v81_rev = 0x8781,
+    v81_sc8480xp_rev = 0x8081,
     v81dgb_1_rev = 0xcc81,
 } Rev_t;
 #define HEXAGON_LATEST_REV v73
diff --git a/hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc b/hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc
new file mode 100644
index 00000000000..5a39e53d834
--- /dev/null
+++ b/hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/* Config table of the SC8480XP NSP0. */
+static const struct hexagon_machine_config sc8480xp_nsp0 = {
+    .ddr_base = 0x80000000,
+    .cfgbase = 0x30180000,
+    .l2vic_base = 0x32390000,
+    .l2vic_size = 0x1000,
+    .csr_base = 0x323a0000,
+    .qtmr_region = 0x323a1000,
+    .cfgtable = {
+        .l2tcm_base = 0x3000,
+        .subsystem_base = 0x3238,
+        .etm_base = 0x3019,
+        .l2cfg_base = 0x301a,
+        .l1s0_base = 0x3100,
+        .fastl2vic_base = 0x301e,
+        .jtlb_size_entries = 0x80,
+        .coproc_present = 0xd,
+        .ext_contexts = 8,
+        .vtcm_base = 0x3100,
+        .vtcm_size_kb = 0x2000,
+        .l2tag_size = 0x400,
+        .l2ecomem_size = 0x400,
+        .thread_enable_mask = 0xfff,
+        .l2line_size = 0x80,
+        .l2itcm_base = 0xd800,
+        .dma_version = 8,
+        .hvx_vec_log_length = 7,
+        .coproc2_reg0 = 0x10,
+        .coproc2_reg1 = 8,
+        .acd_preset = 1,
+        .mnd_preset = 1,
+        .l1d_size_kb = 0x40,
+        .l1i_size_kb = 0x40,
+        .l1d_write_policy = 2,
+        .vtcm_bank_width = 0x80,
+        .reserved4 = 1,
+        .axi3_lowaddr = 0x4000,
+        .corecfg_present = 0xd,
+        .coproc2_fp16_acc_exp = 1,
+        .AXIM_data_width = 0x100,
+        .l1d_ways = 8,
+        .l1i_ways = 4,
+        .l2way_num = 8,
+        .dma_jtlb_entries = 0x40,
+    },
+};
diff --git a/hw/hexagon/sc8480xp_nsp0.c b/hw/hexagon/sc8480xp_nsp0.c
new file mode 100644
index 00000000000..68003f88161
--- /dev/null
+++ b/hw/hexagon/sc8480xp_nsp0.c
@@ -0,0 +1,90 @@
+/*
+ * Models the Hexagon v81 NSP of the SC8480XP.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/core/boards.h"
+#include "hw/hexagon/hexagon.h"
+#include "hw/hexagon/qcom_dsp.h"
+#include "target/hexagon/cpu.h"
+
+#include "machine_cfg_sc8480xp_nsp0.h.inc"
+
+#define TYPE_SC8480XP_NSP0_MACHINE MACHINE_TYPE_NAME("sc8480xp-nsp0")
+
+static const QcomDspRegion sc8480xp_nsp0_regions[] = {
+    { "tcsr", 0x01f40000, 0xc0000 },
+    { "hwkm-prng", 0x010ca000 },
+    { "pll", 0x32340000 },
+    { "clkctl", 0x32344000, 0x4000 },
+    { "turing-cc", 0x32008000, 0x14000 },
+    { "rsc", 0x320a4000 },
+    { "dsp-rsc", 0x323c0000 },
+    { "ipcc", 0x03e00000 },
+    { "ipcc-legacy", 0x32380000 },
+    { "pinctrl", 0x0f100000, 0x0f00000 },
+    { "gcc", 0x00100000, 0x200000 },
+    { "turing-cc-pll", 0x32000000, 0x8000 },
+    { "q6-acd", 0x32350000, 0x800 },
+    { "hmx-pll", 0x32348000 },
+    { "hmx-cc", 0x3234c000, 0x4000 },
+    { "hmx-acd", 0x32350800, 0x800 },
+    { "stmtrace", 0x16000000, 0x1000000 },
+    { "stmcfg", 0x10002000 },
+    { "etb", 0x11c05000 },
+    { "tpdm", 0x11181000, 0x6000 },
+    { "tpda", 0x11188000 },
+    { "funnel", 0x10041000 },
+    { "funnel", 0x11c04000 },
+    { "llcc", 0x20400000, 0x100000 },
+    { "llcc", 0x20600000, 0x100000 },
+    { "llcc", 0x21800000, 0x100000 },
+    { "llcc", 0x21a00000, 0x100000 },
+    { "llcc", 0x21c00000, 0x100000 },
+    { "llcc", 0x21e00000, 0x100000 },
+    { "llcc", 0x22800000, 0x100000 },
+    { "llcc", 0x22a00000, 0x100000 },
+    { "llcc", 0x22c00000, 0x100000 },
+    { "llcc", 0x22e00000, 0x100000 },
+    { "llcc", 0x23800000, 0x100000 },
+    { "llcc", 0x23a00000, 0x100000 },
+    { "llcc", 0x23c00000, 0x100000 },
+    { "llcc", 0x23e00000, 0x100000 },
+    { "ddrss", 0x20280000, 0x400 },
+};
+
+static void sc8480xp_nsp0_init_devices(MachineState *ms)
+{
+    qcom_dsp_add_regions(ms, sc8480xp_nsp0_regions,
+                         ARRAY_SIZE(sc8480xp_nsp0_regions));
+
+    qcom_soc_add_qup_geni_ports("sc8480xp", 0x07980000, 15, 0x4000);
+    qcom_soc_add_qup_geni_ports("sc8480xp", 0x00b80000, 8, 0x4000);
+    qcom_soc_add_qup_geni_ports("sc8480xp", 0x00a80000, 8, 0x4000);
+    qcom_soc_add_qup_geni_ports("sc8480xp", 0x00980000, 2, 0x4000);
+    qcom_soc_add_qup_geni_ports("sc8480xp", 0x00880000, 8, 0x4000);
+}
+
+static const QcomDspMachineInfo sc8480xp_nsp0_info = {
+    .desc = "SC8480XP NSP",
+    .cpu_type = HEXAGON_CPU_TYPE_NAME("v81"),
+    .cpus = 12,
+    .rev = v81_sc8480xp_rev,
+    .cfg = &sc8480xp_nsp0,
+    .kernel_addr = 0xa0000000,
+    .init_devices = sc8480xp_nsp0_init_devices,
+};
+
+static const TypeInfo sc8480xp_nsp0_types[] = {
+    {
+        .name = TYPE_SC8480XP_NSP0_MACHINE,
+        .parent = TYPE_QCOM_DSP_MACHINE,
+        .class_init = qcom_dsp_class_init,
+        .class_data = &sc8480xp_nsp0_info,
+    },
+};
+
+DEFINE_TYPES(sc8480xp_nsp0_types)
diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c
index 5d30d18a9fd..7afeabdbed8 100644
--- a/tests/qtest/l2vic-test.c
+++ b/tests/qtest/l2vic-test.c
@@ -12,6 +12,7 @@
 #include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
 #include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
 #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc"
 #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
 
 /* L2VIC register offsets exercised by this test */
@@ -49,6 +50,7 @@ static const L2VICMachineCfg l2vic_machines[] = {
     { "V66G_1024", &v66g_1024 },
     { "qcs6490-cdsp", &qcs6490_cdsp },
     { "sa8775p-cdsp", &SA8775P_cdsp0 },
+    { "sc8480xp-nsp0", &sc8480xp_nsp0 },
 };
 
 static uint32_t l2vic_read32(uint64_t base, uint32_t offset)
diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c
index 586e113c181..46bbae47881 100644
--- a/tests/qtest/qcom-dsp-test.c
+++ b/tests/qtest/qcom-dsp-test.c
@@ -25,6 +25,7 @@
 static const char *const qcom_dsp_machines[] = {
     "qcs6490-cdsp",
     "sa8775p-cdsp",
+    "sc8480xp-nsp0",
 };
 
 static void test_console(const void *machine)
diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c
index b20d4a2bced..629a11802ef 100644
--- a/tests/qtest/qct-qtimer-test.c
+++ b/tests/qtest/qct-qtimer-test.c
@@ -13,6 +13,7 @@
 #include "hw/hexagon/machine_cfg_v68n_1024.h.inc"
 #include "hw/hexagon/machine_cfg_v66g_1024.h.inc"
 #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc"
+#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc"
 #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc"
 
 #define QTIMER_DEFAULT_FREQ_HZ 19200000ULL
@@ -346,6 +347,7 @@ static const QtimerMachineCfg qtimer_machines[] = {
     { "V66G_1024", &v66g_1024 },
     { "qcs6490-cdsp", &qcs6490_cdsp },
     { "sa8775p-cdsp", &SA8775P_cdsp0 },
+    { "sc8480xp-nsp0", &sc8480xp_nsp0 },
 };
 
 static void test_qtimer_on_machine(gconstpointer data)
diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig
index bdda7872878..8785129da0e 100644
--- a/hw/hexagon/Kconfig
+++ b/hw/hexagon/Kconfig
@@ -42,3 +42,9 @@ config HEX_SA8775P_CDSP
     default y
     depends on HEX_DSP && FDT
     select HEX_QCOM_DSP
+
+config HEX_SC8480XP_NSP0
+    bool
+    default y
+    depends on HEX_DSP && FDT
+    select HEX_QCOM_DSP
diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build
index b7496426c9a..b42a37b14de 100644
--- a/hw/hexagon/meson.build
+++ b/hw/hexagon/meson.build
@@ -9,5 +9,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c'))
 hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: files('qcom_dsp.c'))
 hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cdsp.c'))
 hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cdsp.c'))
+hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true: files('sc8480xp_nsp0.c'))
 
 hw_arch += {'hexagon': hexagon_ss}
-- 
2.34.1