From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Pedro Barbuda <pbarbuda@microsoft.com>,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
Peter Maydell <peter.maydell@linaro.org>,
Mohamed Mediouni <mohamed@unpredictable.fr>,
Doug Cook <dcook@microsoft.com>
Subject: [PATCH v2 01/18] target/i386/whpx: fix VMX capability MSR values
Date: Tue, 27 Oct 2026 16:57:20 +0100 [thread overview]
Message-ID: <20261027155737.59271-2-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20261027155737.59271-1-mohamed@unpredictable.fr>
From: Doug Cook <dcook@microsoft.com>
whpx_get_supported_msr_feature() had two bugs in how it reports the
VMX control MSRs:
- MSR_IA32_VMX_TRUE_PINBASED_CTLS and MSR_IA32_VMX_TRUE_PROCBASED_CTLS
were queried using the non-TRUE capability codes
(WHvCapabilityCodeVmxPinbasedCtls and WHvCapabilityCodeVmxProcbasedCtls).
- For PROCBASED_CTLS2 and the four TRUE_* control MSRs, the raw
allowed-0/allowed-1 pair was returned. The feature-word code expects
only the bits that may be 1 but are not required to be 1. Apply the
same transformation as kvm_arch_get_supported_msr_feature();
make_vmx_msr_value() adds the must-be-one bits back afterwards.
As a result, with +vmx QEMU treated many VMX features the host does
support (secondary controls, EPT, VPID, MSR bitmaps, ...) as missing,
warned about each of them, and dropped them from the CPU model. The
guest itself reads the VMX MSRs from the hypervisor, not from QEMU,
so this did not change what the guest saw.
Signed-off-by: Doug Cook <dcook@microsoft.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
target/i386/whpx/whpx-all.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 113f79afb9..1386affa9c 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -1452,10 +1452,10 @@ uint64_t whpx_get_supported_msr_feature(uint32_t index)
cap = WHvCapabilityCodeVmxEptVpidCap;
break;
case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
- cap = WHvCapabilityCodeVmxPinbasedCtls;
+ cap = WHvCapabilityCodeVmxTruePinbasedCtls;
break;
case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
- cap = WHvCapabilityCodeVmxProcbasedCtls;
+ cap = WHvCapabilityCodeVmxTrueProcbasedCtls;
break;
case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
cap = WHvCapabilityCodeVmxTrueEntryCtls;
@@ -1474,6 +1474,31 @@ uint64_t whpx_get_supported_msr_feature(uint32_t index)
if (FAILED(hr)) {
return 0;
}
+
+ switch (index) {
+ case MSR_IA32_VMX_PROCBASED_CTLS2:
+ case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
+ case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
+ case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
+ case MSR_IA32_VMX_TRUE_EXIT_CTLS: {
+ /*
+ * These MSRs hold the allowed-0 settings in the low half and the
+ * allowed-1 settings in the high half. QEMU's feature words want
+ * only the bits that can be one but do not have to be one, so
+ * apply the same transformation as
+ * kvm_arch_get_supported_msr_feature(); make_vmx_msr_value()
+ * restores the must-be-one bits later.
+ */
+ uint32_t must_be_one = (uint32_t)val;
+ uint32_t can_be_one = (uint32_t)(val >> 32);
+
+ val = can_be_one & ~must_be_one;
+ break;
+ }
+ default:
+ break;
+ }
+
return val;
}
return 0;
--
2.54.0 (Apple Git-157)
next prev parent reply other threads:[~2026-10-27 15:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 15:57 [PATCH v2 00/18] whpx: i386: updates for QEMU 11.2 Mohamed Mediouni
2026-10-27 15:57 ` Mohamed Mediouni [this message]
2026-10-27 15:57 ` [PATCH v2 02/18] target/i386/whpx: whpx_get_xsave_state error handling Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 03/18] whpx: i386: get APIC state before VM save Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 04/18] whpx: i386: fix TPR encodings for local APIC Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 05/18] whpx: i386: save/restore xss Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 06/18] whpx: i386: make nested virtualisation init failure non-fatal Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 07/18] whpx: i386: allow migration for restricted scenarios Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 08/18] whpx: i386: avoid updating hflags for vmexits Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 09/18] target/i386/whpx: handle processor reset Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 10/18] target/arm/whpx: " Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 11/18] whpx: apic: migrate APIC implementation to new interface Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 12/18] whpx: i386: forward the dynamic EBX of CPUID[0xD] sub-leaves 0 and 1, not 1 and 2 Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 13/18] whpx: i386: do not require ProcessorFeaturesBanks on legacy Windows Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 14/18] whpx: i386: fall back to xAPIC when the MSR exit bitmap is unavailable Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 15/18] multi-target: restrict whpx-accel-*-cpu to matching target Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 16/18] whpx: i386: also save debug registers Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 17/18] whpx: i386: save/restore pending interruption/events Mohamed Mediouni
2026-10-27 15:57 ` [PATCH v2 18/18] whpx: docs: update for experimental VM save/restore support Mohamed Mediouni
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