[PATCH 1/3] arm64: tegra: Fix address translation on Tegra264

[PATCH 1/3] arm64: tegra: Fix address translation on Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The TOP chiplet has a region of memory at the local offset 0x20000000.
This region is currently unused, so remapping the non-prefetchable, 32
bit PCI region through that region works fine. However, subsequent
changes will need to make the actual hardware within this region
available, which then causes an address translation conflict.

Fix this by moving the interim translation address (note that this is
purely used for address translation in the operating system and never
used by the driver code) to an unused region of the chiplet's address
space.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 5ab34cd09a3d..ddcc6d3ac9f0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3420,9 +3420,9 @@ bus@8100000000 {
 		#address-cells = <2>;
 		#size-cells = <2>;
 
-		ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */
-			 <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */
-			 <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */
+		ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x18000000>, /* MMIO (384 MiB) */
+			 <0x00 0x18000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (32-bit, 128 MiB) */
+			 <0x00 0x20000000 0x81 0x20000000 0x00 0x30000000>, /* MMIO (768 MiB) */
 			 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
 
 		smmu1: iommu@5000000 {
@@ -3582,7 +3582,7 @@ pci@c000000 {
 			dma-coherent;
 
 			ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */
-				 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
+				 <0x82000000 0x00 0x20000000 0x00 0x18000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
 				 <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
 			bus-range = <0x0 0xff>;
 
-- 
2.55.0

[PATCH 2/3] arm64: tegra: Fix memory size unit in comment

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The non-prefetchable, 32-bit region of PCI addresses in the UPHY chiplet
is not actually 1536 GiB. This is a typo and it should say 1536 MiB.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index ddcc6d3ac9f0..ea2e9adff6d9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -4105,7 +4105,7 @@ bus@a800000000 {
 		#size-cells = <2>;
 
 		ranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */
-			 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
+			 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 MiB) */
 			 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
 
 		pinmux_uphy: pinmux@82e0000 {
-- 
2.55.0

[PATCH 3/3] arm64: tegra: Remove PCI ranges from VISION chiplet

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The VISION chiplet doesn't have any PCI controllers and therefore
doesn't need PCI related ranges for address translation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index ea2e9adff6d9..b7f6b649baab 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3996,9 +3996,7 @@ bus@8180000000 {
 		#address-cells = <2>;
 		#size-cells = <2>;
 
-		ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */
-			 <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
-			 <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
+		ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>; /* MMIO (256 MiB) */
 
 		host1x@1200000 {
 			compatible = "nvidia,tegra264-host1x";
-- 
2.55.0