From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: qemu-devel@nongnu.org
Cc: "Wei Liu" <liuwe@microsoft.com>,
"Magnus Kulke" <magnuskulke@linux.microsoft.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Wei Liu" <wei.liu@kernel.org>,
"Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>,
"Doru Blânzeanu" <dblanzeanu@microsoft.com>,
"Magnus Kulke" <magnuskulke@microsoft.com>
Subject: [PATCH v2 0/3] Add CPU topology extension support for mshv guests
Date: Tue, 10 Nov 2026 11:56:14 +0200 [thread overview]
Message-ID: <20261110095617.50713-1-dblanzeanu@linux.microsoft.com> (raw)
This patch changes how MSHV constructs and registers the guest CPUID table.
It consists of three commits:
1. i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled
2. mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves
3. accel/mshv: Enable SMT support for the mshv partition
The first commit changes the extended CPUID level to 0x8000_001E when the TOPOEXT
feature is enabled.
This fix correctly reports CPU topology and cache leaves when TOPOEXT is
enabled.
Previous to the second commit, `collect_cpuid_entries` treated `0x0b` and `0x1f`
like ordinary leaves and collected only sub-leaf zero. But these Intel topology
leaves contain one sub-leaf per topology level.
With this patch, now it repeatedly calls `cpu_x86_cpuid` and stores every
result until ECX[15:8] becomes zero (same as kvm does).
Changes since V1:
- Enable SMT support in the mshv partition
Doru Blânzeanu (3):
i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is
enabled
mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache
subleaves
accel/mshv: Enable SMT support for the mshv partition
accel/mshv/mshv-all.c | 3 ++-
target/i386/cpu.c | 5 +++++
target/i386/mshv/mshv-cpu.c | 41 +++++++++++++++++++++++++++++--------
3 files changed, 40 insertions(+), 9 deletions(-)
--
2.54.0
next reply other threads:[~2026-11-10 9:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 9:56 Doru Blânzeanu [this message]
2026-11-10 9:56 ` [PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled Doru Blânzeanu
2026-11-11 10:54 ` Magnus Kulke
2026-11-10 9:56 ` [PATCH v2 2/3] mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves Doru Blânzeanu
2026-11-10 9:56 ` [PATCH v2 3/3] accel/mshv: Enable SMT support for the mshv partition Doru Blânzeanu
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