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From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: qemu-devel@nongnu.org
Cc: "Wei Liu" <liuwe@microsoft.com>,
	"Magnus Kulke" <magnuskulke@linux.microsoft.com>,
	"Zhao Liu" <zhao1.liu@intel.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Wei Liu" <wei.liu@kernel.org>,
	"Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>,
	"Doru Blânzeanu" <dblanzeanu@microsoft.com>,
	"Magnus Kulke" <magnuskulke@microsoft.com>
Subject: [PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled
Date: Tue, 10 Nov 2026 11:56:15 +0200	[thread overview]
Message-ID: <20261110095617.50713-2-dblanzeanu@linux.microsoft.com> (raw)
In-Reply-To: <20261110095617.50713-1-dblanzeanu@linux.microsoft.com>

This ensures the guests can discover the AMD cache and processor topology leaves
when TOPOEXT feature is enabled.

Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
---
 target/i386/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eab0d5a4d4..e443132ce9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9911,6 +9911,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
     }
 
+    /* TOPOEXT requires CPUID[0x8000001D] and CPUID[0x8000001E] */
+    if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
+        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E);
+    }
+
     /* SEV requires CPUID[0x8000001F] */
     if (sev_enabled()) {
         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
-- 
2.54.0



  reply	other threads:[~2026-11-10  9:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10  9:56 [PATCH v2 0/3] Add CPU topology extension support for mshv guests Doru Blânzeanu
2026-11-10  9:56 ` Doru Blânzeanu [this message]
2026-11-11 10:54   ` [PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled Magnus Kulke
2026-11-10  9:56 ` [PATCH v2 2/3] mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves Doru Blânzeanu
2026-11-10  9:56 ` [PATCH v2 3/3] accel/mshv: Enable SMT support for the mshv partition Doru Blânzeanu

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