From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: qemu-devel@nongnu.org
Cc: "Wei Liu" <liuwe@microsoft.com>,
"Magnus Kulke" <magnuskulke@linux.microsoft.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Wei Liu" <wei.liu@kernel.org>,
"Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>,
"Doru Blânzeanu" <dblanzeanu@microsoft.com>,
"Magnus Kulke" <magnuskulke@microsoft.com>
Subject: [PATCH v2 3/3] accel/mshv: Enable SMT support for the mshv partition
Date: Tue, 10 Nov 2026 11:56:17 +0200 [thread overview]
Message-ID: <20261110095617.50713-4-dblanzeanu@linux.microsoft.com> (raw)
In-Reply-To: <20261110095617.50713-1-dblanzeanu@linux.microsoft.com>
Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
---
accel/mshv/mshv-all.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index d820a67b95..2b854c1ebd 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -178,7 +178,8 @@ static int create_partition(int mshv_fd, int *vm_fd)
pt_flags = (1ULL << MSHV_PT_BIT_LAPIC) |
(1ULL << MSHV_PT_BIT_X2APIC) |
(1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) |
- (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES);
+ (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES) |
+ (1ULL << MSHV_PT_BIT_SMT_ENABLED_GUEST);
/* enable all */
disabled_xsave_features.as_uint64 = 0;
--
2.54.0
prev parent reply other threads:[~2026-11-10 9:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 9:56 [PATCH v2 0/3] Add CPU topology extension support for mshv guests Doru Blânzeanu
2026-11-10 9:56 ` [PATCH v2 1/3] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled Doru Blânzeanu
2026-11-11 10:54 ` Magnus Kulke
2026-11-10 9:56 ` [PATCH v2 2/3] mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves Doru Blânzeanu
2026-11-10 9:56 ` Doru Blânzeanu [this message]
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