[RFC PATCH 00/38] target/riscv: Add Zvdota/Zvbdota families of dot-product extensions

[RFC PATCH 00/38] target/riscv: Add Zvdota/Zvbdota families of dot-product extensions

[Max Chou]

This RFC patchset introduces the Zvdota/Zvbdota families of dot-product
extensions based on the ISA specification
(https://github.com/riscv/riscv-isa-manual/pull/2618 v1.0 commit: 570e32e)
- Zvdota: Zvqwdota8i/Zvqwdota16i/Zvfwdota16bf/Zvfqwdota8f
- Zvbdota: Zvqwbdota8i/Zvqwbdota16i/Zvfwbdota16bf/Zvfqwbdota8f/Zvfbdota32f

This RFC patchset assigns the Zvdota/Zvbdota cpu properties as the
experimental cpu isa extension properties. These experimental cpu isa
extension properties will be replaced after the Zvdota/Zvbdota isa
specification is ratified.

The toolchains support Zvdota/Zvbdota families extensions:
 - LLVM (after 23.1.0)
   - Support v0.2 Zvdota/Zvbdota extensions
     - https://releases.llvm.org/23.1.0/docs/RISCVUsage.html
   - llvm/llvm-project#196467, commit d25ec4b84487, merged 2026-05-27.
     - https://github.com/llvm/llvm-project/pull/196467
 - GCC (reviewing)
   - Upstream patchset: <20261014093604.829234-3-jiawei@iscas.ac.cn>

References:
 - riscv-isa-manual PR: https://github.com/riscv/riscv-isa-manual/pull/2618

rnax

Max Chou (38):
  fpu/softfloat: Support OCP(Open Compute Project) OFP8 checking
    functions
  target/riscv: Introduce riscv_init_fp_status
  target/riscv: rvv: Introduce RVBNA algorithm for Zvdota/Zvbdota
    extensions
  target/riscv: Add cfg property for Zvqwdota8i extension
  target/riscv: Add implied rules for Zvqwdota8i extension
  target/riscv: rvv: Implement Zvqwdota8i instructions
  disas/riscv: Support Zvqwdota8i extension
  target/riscv: Add Zvqwdota16i cpu property
  target/riscv: Add Zvqwdota16i dependency imply rule
  target/riscv: rvv: Implement Zvqwdota16i instructions
  target/riscv: Add cfg property for Zvfwdota16bf extension
  target/riscv: Add implied rules for Zvfwdota16bf extension
  target/riscv: rvv: Implement Zvfwdota16bf instruction
  disas/riscv: Support Zvfwdota16bf extension
  target/riscv: Add cfg property for Zvfqwdota8f extension
  target/riscv: Add implied rules for Zvfqwdota8f extension
  target/riscv: rvv: Implement Zvfqwdota8f instructions
  disas/riscv: Support Zvfqwdota8f extension
  target/riscv: Add cfg property for Zvqwbdota8i extension
  target/riscv: Add implied rules for Zvqwbdota8i extension
  target/riscv: rvv: Implement Zvqwbdota8i instructions
  disas/riscv: Support Zvqwbdota8i extension
  target/riscv: Add cfg property for Zvqwbdota16i extension
  target/riscv: Add implied rules for Zvqwbdota16i extension
  target/riscv: rvv: Implement Zvqwbdota16i instructions
  target/riscv: Add cfg property for Zvfwbdota16bf extension
  target/riscv: Add implied rules for Zvfwbdota16bf extension
  target/riscv: rvv: Implement Zvfwbdota16bf instruction
  disas/riscv: Support Zvfwbdota16bf extension
  target/riscv: Add cfg property for Zvfqwbdota8f extension
  target/riscv: Add implied rules for Zvfqwbdota8f extension
  target/riscv: rvv: Implement Zvfqwbdota8f instructions
  disas/riscv: Support Zvfqwbdota8f extension
  target/riscv: Add cfg property for Zvfbdota32f extension
  target/riscv: Add implied rules for Zvfbdota32f extension
  target/riscv: rvv: Implement Zvfbdota32f instructions
  disas/riscv: Support Zvfbdota32f extension
  tests/tcg/riscv64: Add test for Zvdota/Zvbdota extensions

 MAINTAINERS                                 |   6 +
 disas/riscv-op.c.inc                        |  12 +
 disas/riscv.c                               |  26 ++
 disas/riscv.h                               |   2 +
 fpu/softfloat-specialize.c.inc              |  55 +++
 include/fpu/softfloat.h                     |  70 ++++
 target/riscv/cpu.c                          | 121 +++++-
 target/riscv/cpu_cfg_fields.h.inc           |   9 +
 target/riscv/helper.h                       |  28 ++
 target/riscv/insn32.decode                  |  25 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 305 ++++++++++++++
 target/riscv/tcg/meson.build                |   2 +-
 target/riscv/tcg/rvbna.c                    | 185 +++++++++
 target/riscv/tcg/rvbna.h                    |  40 ++
 target/riscv/tcg/tcg-cpu.c                  |  45 +++
 target/riscv/tcg/vector_helper.c            | 424 +++++++++++++++++++-
 tests/tcg/riscv64/system/meson.build        |  12 +
 tests/tcg/riscv64/test-zvdota.S             | 343 ++++++++++++++++
 18 files changed, 1703 insertions(+), 7 deletions(-)
 create mode 100644 target/riscv/tcg/rvbna.c
 create mode 100644 target/riscv/tcg/rvbna.h
 create mode 100644 tests/tcg/riscv64/test-zvdota.S

-- 
2.56.0

[RFC PATCH 01/38] fpu/softfloat: Support OCP(Open Compute Project) OFP8 checking functions

[Max Chou]

Include following checking functions liked other fp types:
- *_nan_is_snan
- *_is_quiet_nan
- *_is_signaling_nan
- *_is_any_nan
- *_is_neg
- *_is_infinity
- *_is_zero
- *_is_zero_or_denormal
- *_is_normal

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++++++++
 include/fpu/softfloat.h        | 70 ++++++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+)

diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index 8b765ef623f..22a3188f99b 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -255,6 +255,61 @@ floatx80 floatx80_default_inf(bool zSign, float_status *status)
     return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63));
 }
 
+/*----------------------------------------------------------------------------
+| Determine if a OCP FP8 E4M3 NaN is signaling NaN.
+| E4M3 has only one NaN encoding, so classification is policy-based.
+*----------------------------------------------------------------------------*/
+
+static bool float8_e4m3_nan_is_snan(float8_e4m3 a, float_status *status)
+{
+    return get_float_e4m3_nan_is_snan(status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the OCP FP8 E4M3 value `a' is a quiet NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8_e4m3_is_quiet_nan(float8_e4m3 a_, float_status *status)
+{
+    return float8_e4m3_is_any_nan(a_) && !float8_e4m3_nan_is_snan(a_, status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the OCP FP8 E4M3 value `a' is a signaling NaN; otherwise 0.
+*----------------------------------------------------------------------------*/
+
+bool float8_e4m3_is_signaling_nan(float8_e4m3 a_, float_status *status)
+{
+    return float8_e4m3_is_any_nan(a_) && float8_e4m3_nan_is_snan(a_, status);
+}
+
+/*----------------------------------------------------------------------------
+| Determine if a OCP FP8 E5M2 NaN is signaling NaN.
+*----------------------------------------------------------------------------*/
+
+static bool float8_e5m2_nan_is_snan(float8_e5m2 a, float_status *status)
+{
+    return frac_msb_is_snan((a >> 1) & 1, status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the OCP FP8 E5M2 value `a' is a quiet NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8_e5m2_is_quiet_nan(float8_e5m2 a_, float_status *status)
+{
+    return float8_e5m2_is_any_nan(a_) && !float8_e5m2_nan_is_snan(a_, status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the OCP FP8 E5M2 value `a' is a signaling NaN; otherwise 0.
+*----------------------------------------------------------------------------*/
+
+bool float8_e5m2_is_signaling_nan(float8_e5m2 a_, float_status *status)
+{
+    return float8_e5m2_is_any_nan(a_) && float8_e5m2_nan_is_snan(a_, status);
+}
+
 /*----------------------------------------------------------------------------
 | Determine if a float16 NaN is signaling NaN.
 *----------------------------------------------------------------------------*/
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d48fc6b0437..4d91599e25d 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -222,6 +222,76 @@ bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status);
 float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool sat, float_status *status);
 float8_e5m2 float32_to_float8_e5m2(float32, bool sat, float_status *status);
 
+/*----------------------------------------------------------------------------
+| OCP FP{4,8} classify operations.
+*----------------------------------------------------------------------------*/
+
+bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status);
+bool float8_e4m3_is_signaling_nan(float8_e4m3, float_status *status);
+bool float8_e5m2_is_quiet_nan(float8_e5m2, float_status *status);
+bool float8_e5m2_is_signaling_nan(float8_e5m2, float_status *status);
+
+static inline bool float8_e4m3_is_any_nan(float8_e4m3 a)
+{
+    return ((a & ~0x80) == 0x7f);
+}
+
+static inline bool float8_e5m2_is_any_nan(float8_e5m2 a)
+{
+    return ((a & ~0x80) > 0x7c);
+}
+
+static inline bool float8_e4m3_is_neg(float8_e4m3 a)
+{
+    return a >> 7;
+}
+
+static inline bool float8_e5m2_is_neg(float8_e5m2 a)
+{
+    return a >> 7;
+}
+
+static inline bool float8_e4m3_is_infinity(float8_e4m3 a)
+{
+    return false;
+}
+
+static inline bool float8_e5m2_is_infinity(float8_e5m2 a)
+{
+    return (a & 0x7f) == 0x7c;
+}
+
+static inline bool float8_e4m3_is_zero(float8_e4m3 a)
+{
+    return (a & 0x7f) == 0;
+}
+
+static inline bool float8_e5m2_is_zero(float8_e5m2 a)
+{
+    return (a & 0x7f) == 0;
+}
+
+static inline bool float8_e4m3_is_zero_or_denormal(float8_e4m3 a)
+{
+    return (a & 0x78) == 0;
+}
+
+static inline bool float8_e5m2_is_zero_or_denormal(float8_e5m2 a)
+{
+    return (a & 0x7c) == 0;
+}
+
+static inline bool float8_e4m3_is_normal(float8_e4m3 a)
+{
+    uint8_t em = a & 0x7f;
+    return em >= 0x8 && em <= 0x7e;
+}
+
+static inline bool float8_e5m2_is_normal(float8_e5m2 a)
+{
+    return (((a >> 2) + 1) & 0x1f) >= 2;
+}
+
 /*----------------------------------------------------------------------------
 | Software half-precision conversion routines.
 *----------------------------------------------------------------------------*/
-- 
2.56.0

Re: [RFC PATCH 01/38] fpu/softfloat: Support OCP(Open Compute Project) OFP8 checking functions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Include following checking functions liked other fp types:

typo: s/liked/like

> - *_nan_is_snan
> - *_is_quiet_nan
> - *_is_signaling_nan
> - *_is_any_nan
> - *_is_neg
> - *_is_infinity
> - *_is_zero
> - *_is_zero_or_denormal
> - *_is_normal
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++++++++
>   include/fpu/softfloat.h        | 70 ++++++++++++++++++++++++++++++++++
>   2 files changed, 125 insertions(+)
> 
> diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
> index 8b765ef623f..22a3188f99b 100644
> --- a/fpu/softfloat-specialize.c.inc
> +++ b/fpu/softfloat-specialize.c.inc
> @@ -255,6 +255,61 @@ floatx80 floatx80_default_inf(bool zSign, float_status *status)
>       return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63));
>   }
>   
> +/*----------------------------------------------------------------------------
> +| Determine if a OCP FP8 E4M3 NaN is signaling NaN.
> +| E4M3 has only one NaN encoding, so classification is policy-based.
> +*----------------------------------------------------------------------------*/
> +
> +static bool float8_e4m3_nan_is_snan(float8_e4m3 a, float_status *status)
> +{
> +    return get_float_e4m3_nan_is_snan(status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E4M3 value `a' is a quiet NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_quiet_nan(float8_e4m3 a_, float_status *status)
> +{
> +    return float8_e4m3_is_any_nan(a_) && !float8_e4m3_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E4M3 value `a' is a signaling NaN; otherwise 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_signaling_nan(float8_e4m3 a_, float_status *status)
> +{
> +    return float8_e4m3_is_any_nan(a_) && float8_e4m3_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Determine if a OCP FP8 E5M2 NaN is signaling NaN.
> +*----------------------------------------------------------------------------*/
> +
> +static bool float8_e5m2_nan_is_snan(float8_e5m2 a, float_status *status)
> +{
> +    return frac_msb_is_snan((a >> 1) & 1, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E5M2 value `a' is a quiet NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e5m2_is_quiet_nan(float8_e5m2 a_, float_status *status)
> +{
> +    return float8_e5m2_is_any_nan(a_) && !float8_e5m2_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E5M2 value `a' is a signaling NaN; otherwise 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e5m2_is_signaling_nan(float8_e5m2 a_, float_status *status)
> +{
> +    return float8_e5m2_is_any_nan(a_) && float8_e5m2_nan_is_snan(a_, status);
> +}
> +
>   /*----------------------------------------------------------------------------
>   | Determine if a float16 NaN is signaling NaN.
>   *----------------------------------------------------------------------------*/
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index d48fc6b0437..4d91599e25d 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -222,6 +222,76 @@ bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status);
>   float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool sat, float_status *status);
>   float8_e5m2 float32_to_float8_e5m2(float32, bool sat, float_status *status);
>   
> +/*----------------------------------------------------------------------------
> +| OCP FP{4,8} classify operations.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status);
> +bool float8_e4m3_is_signaling_nan(float8_e4m3, float_status *status);
> +bool float8_e5m2_is_quiet_nan(float8_e5m2, float_status *status);
> +bool float8_e5m2_is_signaling_nan(float8_e5m2, float_status *status);
> +
> +static inline bool float8_e4m3_is_any_nan(float8_e4m3 a)
> +{
> +    return ((a & ~0x80) == 0x7f);
> +}
> +
> +static inline bool float8_e5m2_is_any_nan(float8_e5m2 a)
> +{
> +    return ((a & ~0x80) > 0x7c);
> +}
> +
> +static inline bool float8_e4m3_is_neg(float8_e4m3 a)
> +{
> +    return a >> 7;
> +}
> +
> +static inline bool float8_e5m2_is_neg(float8_e5m2 a)
> +{
> +    return a >> 7;
> +}
> +
> +static inline bool float8_e4m3_is_infinity(float8_e4m3 a)
> +{
> +    return false;
> +}
> +
> +static inline bool float8_e5m2_is_infinity(float8_e5m2 a)
> +{
> +    return (a & 0x7f) == 0x7c;
> +}
> +
> +static inline bool float8_e4m3_is_zero(float8_e4m3 a)
> +{
> +    return (a & 0x7f) == 0;
> +}
> +
> +static inline bool float8_e5m2_is_zero(float8_e5m2 a)
> +{
> +    return (a & 0x7f) == 0;
> +}
> +
> +static inline bool float8_e4m3_is_zero_or_denormal(float8_e4m3 a)
> +{
> +    return (a & 0x78) == 0;
> +}
> +
> +static inline bool float8_e5m2_is_zero_or_denormal(float8_e5m2 a)
> +{
> +    return (a & 0x7c) == 0;
> +}
> +
> +static inline bool float8_e4m3_is_normal(float8_e4m3 a)
> +{
> +    uint8_t em = a & 0x7f;
> +    return em >= 0x8 && em <= 0x7e;
> +}
> +
> +static inline bool float8_e5m2_is_normal(float8_e5m2 a)
> +{
> +    return (((a >> 2) + 1) & 0x1f) >= 2;
> +}
> +
>   /*----------------------------------------------------------------------------
>   | Software half-precision conversion routines.
>   *----------------------------------------------------------------------------*/

Re: [RFC PATCH 01/38] fpu/softfloat: Support OCP(Open Compute Project) OFP8 checking functions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:16 +0800 Max Chou <max.chou@sifive.com> wrote:

> Include following checking functions liked other fp types:
> - *_nan_is_snan
> - *_is_quiet_nan
> - *_is_signaling_nan
> - *_is_any_nan
> - *_is_neg
> - *_is_infinity
> - *_is_zero
> - *_is_zero_or_denormal
> - *_is_normal
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++++++++
>  include/fpu/softfloat.h        | 70 ++++++++++++++++++++++++++++++++++
>  2 files changed, 125 insertions(+)
> 
> diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
> index 8b765ef623f..22a3188f99b 100644
> --- a/fpu/softfloat-specialize.c.inc
> +++ b/fpu/softfloat-specialize.c.inc
> @@ -255,6 +255,61 @@ floatx80 floatx80_default_inf(bool zSign, float_status *status)
>      return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63));
>  }
>  
> +/*----------------------------------------------------------------------------
> +| Determine if a OCP FP8 E4M3 NaN is signaling NaN.
> +| E4M3 has only one NaN encoding, so classification is policy-based.
> +*----------------------------------------------------------------------------*/
> +
> +static bool float8_e4m3_nan_is_snan(float8_e4m3 a, float_status *status)
> +{
> +    return get_float_e4m3_nan_is_snan(status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E4M3 value `a' is a quiet NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_quiet_nan(float8_e4m3 a_, float_status *status)
> +{
> +    return float8_e4m3_is_any_nan(a_) && !float8_e4m3_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E4M3 value `a' is a signaling NaN; otherwise 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_signaling_nan(float8_e4m3 a_, float_status *status)
> +{
> +    return float8_e4m3_is_any_nan(a_) && float8_e4m3_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Determine if a OCP FP8 E5M2 NaN is signaling NaN.
> +*----------------------------------------------------------------------------*/
> +
> +static bool float8_e5m2_nan_is_snan(float8_e5m2 a, float_status *status)
> +{
> +    return frac_msb_is_snan((a >> 1) & 1, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E5M2 value `a' is a quiet NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e5m2_is_quiet_nan(float8_e5m2 a_, float_status *status)
> +{
> +    return float8_e5m2_is_any_nan(a_) && !float8_e5m2_nan_is_snan(a_, status);
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the OCP FP8 E5M2 value `a' is a signaling NaN; otherwise 0.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e5m2_is_signaling_nan(float8_e5m2 a_, float_status *status)
> +{
> +    return float8_e5m2_is_any_nan(a_) && float8_e5m2_nan_is_snan(a_, status);
> +}
> +
>  /*----------------------------------------------------------------------------
>  | Determine if a float16 NaN is signaling NaN.
>  *----------------------------------------------------------------------------*/
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index d48fc6b0437..4d91599e25d 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -222,6 +222,76 @@ bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status);
>  float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool sat, float_status *status);
>  float8_e5m2 float32_to_float8_e5m2(float32, bool sat, float_status *status);
>  
> +/*----------------------------------------------------------------------------
> +| OCP FP{4,8} classify operations.
> +*----------------------------------------------------------------------------*/
> +
> +bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status);
> +bool float8_e4m3_is_signaling_nan(float8_e4m3, float_status *status);
> +bool float8_e5m2_is_quiet_nan(float8_e5m2, float_status *status);
> +bool float8_e5m2_is_signaling_nan(float8_e5m2, float_status *status);
> +
> +static inline bool float8_e4m3_is_any_nan(float8_e4m3 a)
> +{
> +    return ((a & ~0x80) == 0x7f);
> +}
> +
> +static inline bool float8_e5m2_is_any_nan(float8_e5m2 a)
> +{
> +    return ((a & ~0x80) > 0x7c);
> +}
> +
> +static inline bool float8_e4m3_is_neg(float8_e4m3 a)
> +{
> +    return a >> 7;
> +}
> +
> +static inline bool float8_e5m2_is_neg(float8_e5m2 a)
> +{
> +    return a >> 7;
> +}
> +
> +static inline bool float8_e4m3_is_infinity(float8_e4m3 a)
> +{
> +    return false;
> +}
> +
> +static inline bool float8_e5m2_is_infinity(float8_e5m2 a)
> +{
> +    return (a & 0x7f) == 0x7c;
> +}
> +
> +static inline bool float8_e4m3_is_zero(float8_e4m3 a)
> +{
> +    return (a & 0x7f) == 0;
> +}
> +
> +static inline bool float8_e5m2_is_zero(float8_e5m2 a)
> +{
> +    return (a & 0x7f) == 0;
> +}
> +
> +static inline bool float8_e4m3_is_zero_or_denormal(float8_e4m3 a)
> +{
> +    return (a & 0x78) == 0;
> +}
> +
> +static inline bool float8_e5m2_is_zero_or_denormal(float8_e5m2 a)
> +{
> +    return (a & 0x7c) == 0;
> +}
> +
> +static inline bool float8_e4m3_is_normal(float8_e4m3 a)
> +{
> +    uint8_t em = a & 0x7f;
> +    return em >= 0x8 && em <= 0x7e;
> +}
> +
> +static inline bool float8_e5m2_is_normal(float8_e5m2 a)
> +{
> +    return (((a >> 2) + 1) & 0x1f) >= 2;
> +}
> +
>  /*----------------------------------------------------------------------------
>  | Software half-precision conversion routines.
>  *----------------------------------------------------------------------------*/
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 02/38] target/riscv: Introduce riscv_init_fp_status

[Max Chou]

Create a function to set all default controls for the float_status.
And set e4m3_nan_is_snan to false to follow the RISC-V isa extensions.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 362e5618091..53ecce8c398 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -978,6 +978,14 @@ static bool riscv_cpu_has_work(CPUState *cs)
 }
 #endif /* !CONFIG_USER_ONLY */
 
+static void riscv_init_fp_status(float_status *s)
+{
+    set_default_nan_mode(1, s);
+    /* Default NaN value: sign bit clear, frac msb set */
+    set_float_default_nan_pattern(0b01000000, s);
+    set_float_e4m3_nan_is_snan(false, s);
+}
+
 static void riscv_cpu_reset_hold(Object *obj, ResetType type)
 {
     CPUState *cs = CPU(obj);
@@ -1095,11 +1103,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     env->xl = riscv_cpu_mxl(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
-    set_default_nan_mode(1, &env->fp_status);
-    /* Default NaN value: sign bit clear, frac msb set */
-    set_float_default_nan_pattern(0b01000000, &env->fp_status);
     env->vill = true;
 
+    riscv_init_fp_status(&env->fp_status);
+
 #ifndef CONFIG_USER_ONLY
 #ifdef CONFIG_TCG
     env->debug_mode = false;
-- 
2.56.0

Re: [RFC PATCH 02/38] target/riscv: Introduce riscv_init_fp_status

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Create a function to set all default controls for the float_status.
> And set e4m3_nan_is_snan to false to follow the RISC-V isa extensions.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 13 ++++++++++---
>   1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 362e5618091..53ecce8c398 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -978,6 +978,14 @@ static bool riscv_cpu_has_work(CPUState *cs)
>   }
>   #endif /* !CONFIG_USER_ONLY */
>   
> +static void riscv_init_fp_status(float_status *s)
> +{
> +    set_default_nan_mode(1, s);
> +    /* Default NaN value: sign bit clear, frac msb set */
> +    set_float_default_nan_pattern(0b01000000, s);
> +    set_float_e4m3_nan_is_snan(false, s);
> +}
> +
>   static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>   {
>       CPUState *cs = CPU(obj);
> @@ -1095,11 +1103,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>       env->xl = riscv_cpu_mxl(env);
>       cs->exception_index = RISCV_EXCP_NONE;
>       env->load_res = -1;
> -    set_default_nan_mode(1, &env->fp_status);
> -    /* Default NaN value: sign bit clear, frac msb set */
> -    set_float_default_nan_pattern(0b01000000, &env->fp_status);
>       env->vill = true;
>   
> +    riscv_init_fp_status(&env->fp_status);
> +
>   #ifndef CONFIG_USER_ONLY
>   #ifdef CONFIG_TCG
>       env->debug_mode = false;

Re: [RFC PATCH 02/38] target/riscv: Introduce riscv_init_fp_status

[Chao Liu]

On Thu,  5 Nov 2026 03:41:17 +0800 Max Chou <max.chou@sifive.com> wrote:

> Create a function to set all default controls for the float_status.
> And set e4m3_nan_is_snan to false to follow the RISC-V isa extensions.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 362e5618091..53ecce8c398 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -978,6 +978,14 @@ static bool riscv_cpu_has_work(CPUState *cs)
>  }
>  #endif /* !CONFIG_USER_ONLY */
>  
> +static void riscv_init_fp_status(float_status *s)
> +{
> +    set_default_nan_mode(1, s);
> +    /* Default NaN value: sign bit clear, frac msb set */
> +    set_float_default_nan_pattern(0b01000000, s);
> +    set_float_e4m3_nan_is_snan(false, s);
> +}
> +
>  static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>  {
>      CPUState *cs = CPU(obj);
> @@ -1095,11 +1103,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>      env->xl = riscv_cpu_mxl(env);
>      cs->exception_index = RISCV_EXCP_NONE;
>      env->load_res = -1;
> -    set_default_nan_mode(1, &env->fp_status);
> -    /* Default NaN value: sign bit clear, frac msb set */
> -    set_float_default_nan_pattern(0b01000000, &env->fp_status);
>      env->vill = true;
>  
> +    riscv_init_fp_status(&env->fp_status);
> +
>  #ifndef CONFIG_USER_ONLY
>  #ifdef CONFIG_TCG
>      env->debug_mode = false;
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 03/38] target/riscv: rvv: Introduce RVBNA algorithm for Zvdota/Zvbdota extensions

[Max Chou]

The RISC-V Bulk Normalization Algorithm (RVBNA) is a scheme employed by
multiple RISC-V extensions (e.g. Zvdota/Zvbdota family) for efficient
computation of floating-point dot products.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 MAINTAINERS                      |   6 +
 target/riscv/tcg/meson.build     |   2 +-
 target/riscv/tcg/rvbna.c         | 185 +++++++++++++++++++++++++++++++
 target/riscv/tcg/rvbna.h         |  40 +++++++
 target/riscv/tcg/vector_helper.c |   1 +
 5 files changed, 233 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/tcg/rvbna.c
 create mode 100644 target/riscv/tcg/rvbna.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 55463103ff1..b91e5925344 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -416,6 +416,12 @@ F: target/riscv/tcg/xsf_helper.c
 F: disas/riscv-xsf*
 F: tests/tcg/riscv64/test-xsfvqmacc.S
 
+RISC-V Bulk Normalization Algorithm (RVBNA)
+M: Max Chou <max.chou@sifive.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/tcg/rvbna.*
+
 RENESAS RX CPUs
 R: Yoshinori Sato <yoshinori.sato@nifty.com>
 S: Orphan
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
index 86805b30cbc..3b7821178fc 100644
--- a/target/riscv/tcg/meson.build
+++ b/target/riscv/tcg/meson.build
@@ -10,6 +10,7 @@ riscv_ss.add(files(
   'fpu_helper.c',
   'm128_helper.c',
   'op_helper.c',
+  'rvbna.c',
   'translate.c',
   'tcg-cpu.c',
   'vcrypto_helper.c',
@@ -27,4 +28,3 @@ riscv_system_ss.add(files(
   'th_csr.c',
 ))
 
-
diff --git a/target/riscv/tcg/rvbna.c b/target/riscv/tcg/rvbna.c
new file mode 100644
index 00000000000..f6150e4976d
--- /dev/null
+++ b/target/riscv/tcg/rvbna.c
@@ -0,0 +1,185 @@
+/*
+ * RISC-V Bulk Normalization Algorithm (RVBNA)
+ *
+ * Copyright (c) 2026 SiFive, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/host-utils.h"
+#include "fpu/softfloat.h"
+#include "fpu/softfloat-macros.h"
+#include "rvbna.h"
+
+static inline int rvbna_guard_bits(uint32_t n_prod)
+{
+    g_assert(n_prod > 0);
+    return 32 - clz32(n_prod - 1);
+}
+
+float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
+                            float_status *fp_status)
+{
+    FloatRoundMode old_rm = get_float_rounding_mode(fp_status);
+    int old_flags = get_float_exception_flags(fp_status);
+    int new_flags;
+    float32 result;
+
+    set_float_rounding_mode(float_round_to_odd_inf, fp_status);
+    set_float_exception_flags(0, fp_status);
+    result = float32_add(partial, accumulator, fp_status);
+    new_flags = get_float_exception_flags(fp_status) &
+                (float_flag_invalid | float_flag_overflow);
+    set_float_rounding_mode(old_rm, fp_status);
+    set_float_exception_flags(old_flags | new_flags, fp_status);
+
+    return result;
+}
+
+#define RVBNA_STACK_THRESHOLD 8
+
+#define GEN_RVBNA(TA, TB, TO, A_E, A_M, B_E, B_M, OUT_E, OUT_M)              \
+TO rvbna_dot_##TA##_##TB(const TA a[], const TB b[], uint32_t n_prod,        \
+                         float_status *fp_status)                            \
+{                                                                            \
+    int32_t stack_ref_exps[RVBNA_STACK_THRESHOLD];                           \
+    bool stack_signs[RVBNA_STACK_THRESHOLD];                                 \
+    uint64_t stack_sigs[RVBNA_STACK_THRESHOLD];                              \
+    int32_t *prod_ref_exps = stack_ref_exps;                                 \
+    bool *prod_signs = stack_signs;                                          \
+    uint64_t *prod_sigs = stack_sigs;                                        \
+    g_autofree int32_t *heap_ref_exps = NULL;                                \
+    g_autofree bool *heap_signs = NULL;                                      \
+    g_autofree uint64_t *heap_sigs = NULL;                                   \
+    int guard_bits = rvbna_guard_bits(n_prod);                               \
+    int pad = OUT_M - (A_M + B_M) + guard_bits;                              \
+    int output_bias = (1 << (OUT_E - 1)) - 1;                                \
+    int a_exp_bias = (1 << (A_E - 1)) - 1;                                   \
+    int b_exp_bias = (1 << (B_E - 1)) - 1;                                   \
+    int ref_bias = output_bias - (a_exp_bias + b_exp_bias);                  \
+    int max_prod_ref_exp = ref_bias;                                         \
+    int overflow_exp = (1 << OUT_E) - 1;                                     \
+    int64_t acc = 0;                                                         \
+    bool nan_result = false;                                                 \
+    bool inf_result = false;                                                 \
+    bool inf_sign = false;                                                   \
+    bool any_pos_inf = false;                                                \
+    bool any_neg_inf = false;                                                \
+    bool any_invalid_prod = false;                                           \
+    bool any_signan = false;                                                 \
+    bool op_sign_inf, sign, overflow;                                        \
+    uint32_t i;                                                              \
+    uint64_t sig;                                                            \
+    int lead, exp, sig_bits;                                                 \
+                                                                             \
+    g_assert(pad >= 0);                                                      \
+    if (n_prod > RVBNA_STACK_THRESHOLD) {                                    \
+        heap_ref_exps = g_new(int32_t, n_prod);                              \
+        heap_signs = g_new(bool, n_prod);                                    \
+        heap_sigs = g_new(uint64_t, n_prod);                                 \
+        prod_ref_exps = heap_ref_exps;                                       \
+        prod_signs = heap_signs;                                             \
+        prod_sigs = heap_sigs;                                               \
+    }                                                                        \
+                                                                             \
+    for (i = 0; i < n_prod; i++) {                                           \
+        bool a_sign = TA##_is_neg(a[i]);                                     \
+        bool b_sign = TB##_is_neg(b[i]);                                     \
+        bool a_sub = TA##_is_zero_or_denormal(a[i]);                         \
+        bool b_sub = TB##_is_zero_or_denormal(b[i]);                         \
+        bool a_zero = TA##_is_zero(a[i]);                                    \
+        bool b_zero = TB##_is_zero(b[i]);                                    \
+        bool a_inf = TA##_is_infinity(a[i]);                                 \
+        bool b_inf = TB##_is_infinity(b[i]);                                 \
+        bool a_nan = TA##_is_any_nan(a[i]);                                  \
+        bool b_nan = TB##_is_any_nan(b[i]);                                  \
+        bool prod_sign = a_sign ^ b_sign;                                    \
+        bool invalid_prod = (a_inf && b_zero) || (b_inf && a_zero);          \
+        bool inf_prod_lhs = a_inf && !b_nan && !b_zero;                      \
+        bool inf_prod_rhs = b_inf && !a_nan && !a_zero;                      \
+        bool inf_prod = inf_prod_lhs || inf_prod_rhs;                        \
+        bool invalid_sum = inf_result && inf_prod &&                         \
+                           (inf_sign != prod_sign);                          \
+        uint32_t a_mant = extract32(a[i], 0, A_M);                           \
+        uint32_t b_mant = extract32(b[i], 0, B_M);                           \
+        bool a_signan = a_nan && TA##_is_signaling_nan(a[i], fp_status);     \
+        bool b_signan = b_nan && TB##_is_signaling_nan(b[i], fp_status);     \
+        uint64_t a_sig = a_mant | (!a_sub << A_M);                           \
+        uint64_t b_sig = b_mant | (!b_sub << B_M);                           \
+        bool prod_is_zero = a_zero || b_zero;                                \
+        bool either_inf = a_inf || b_inf;                                    \
+        bool either_nan = a_nan || b_nan;                                    \
+                                                                             \
+        any_invalid_prod |= invalid_prod;                                    \
+        nan_result |= a_nan || b_nan || any_invalid_prod || invalid_sum;     \
+        inf_result |= inf_prod;                                              \
+        inf_sign = inf_prod ? prod_sign : inf_sign;                          \
+                                                                             \
+        prod_signs[i] = prod_sign;                                           \
+        prod_sigs[i] = (uint64_t)(a_sig * b_sig) << pad;                     \
+        prod_ref_exps[i] = ref_bias;                                         \
+        if (!prod_is_zero) {                                                 \
+            prod_ref_exps[i] += (a_sub ? 1 : extract32(a[i], A_M, A_E)) +    \
+                                (b_sub ? 1 : extract32(b[i], B_M, B_E));     \
+        }                                                                    \
+        max_prod_ref_exp = MAX(prod_ref_exps[i], max_prod_ref_exp);          \
+                                                                             \
+        any_pos_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
+                        (a_sign == b_sign));                                 \
+        any_neg_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
+                        (a_sign != b_sign));                                 \
+        any_signan |= a_signan || b_signan;                                  \
+    }                                                                        \
+                                                                             \
+    op_sign_inf = any_pos_inf && any_neg_inf;                                \
+                                                                             \
+    if (nan_result) {                                                        \
+        if (any_signan || any_invalid_prod || op_sign_inf) {                 \
+            float_raise(float_flag_invalid, fp_status);                      \
+        }                                                                    \
+        return TO##_default_nan(fp_status);                                  \
+    } else if (inf_result) {                                                 \
+        return TO##_set_sign(TO##_infinity, inf_sign);                       \
+    }                                                                        \
+                                                                             \
+    for (i = 0; i < n_prod; i++) {                                           \
+        shift64RightJamming(prod_sigs[i],                                    \
+                            max_prod_ref_exp - prod_ref_exps[i], &sig);      \
+        acc += prod_signs[i] ? -(int64_t)sig : (int64_t)sig;                 \
+    }                                                                        \
+                                                                             \
+    sign = acc < 0;                                                          \
+    sig = sign ? -(uint64_t)acc : acc;                                       \
+    if (sig == 0) {                                                          \
+        return 0;                                                            \
+    }                                                                        \
+                                                                             \
+    lead = 63 - clz64(sig);                                                  \
+    exp = max_prod_ref_exp - OUT_M - guard_bits + lead;                      \
+    overflow = exp >= overflow_exp;                                          \
+    if (overflow) {                                                          \
+        float_raise(float_flag_overflow, fp_status);                         \
+        sig = 0;                                                             \
+        exp = overflow_exp;                                                  \
+    } else {                                                                 \
+        sig_bits = MAX(0, exp <= 0 ? OUT_M - (1 - exp) : OUT_M);             \
+        if (lead > sig_bits) {                                               \
+            shift64RightJamming(sig, lead - sig_bits, &sig);                 \
+        } else {                                                             \
+            sig <<= (sig_bits - lead);                                       \
+        }                                                                    \
+        exp = MAX(exp, 0);                                                   \
+    }                                                                        \
+    return (TO)deposit64(deposit64(sig, OUT_M, OUT_E, exp),                  \
+                         OUT_M + OUT_E,                                      \
+                         1, sign);                                           \
+}
+
+GEN_RVBNA(float8_e4m3, float8_e4m3, float32, 4, 3, 4, 3, 8, 23)
+GEN_RVBNA(float8_e4m3, float8_e5m2, float32, 4, 3, 5, 2, 8, 23)
+GEN_RVBNA(float8_e5m2, float8_e4m3, float32, 5, 2, 4, 3, 8, 23)
+GEN_RVBNA(float8_e5m2, float8_e5m2, float32, 5, 2, 5, 2, 8, 23)
+GEN_RVBNA(float16, float16, float32, 5, 10, 5, 10, 8, 23)
+GEN_RVBNA(bfloat16, bfloat16, float32, 8, 7, 8, 7, 8, 23)
diff --git a/target/riscv/tcg/rvbna.h b/target/riscv/tcg/rvbna.h
new file mode 100644
index 00000000000..d4d3eced952
--- /dev/null
+++ b/target/riscv/tcg/rvbna.h
@@ -0,0 +1,40 @@
+/*
+ * RISC-V Bulk Normalization Algorithm (RVBNA)
+ *
+ * Copyright (c) 2026 SiFive, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_RISCV_TCG_RVBNA_H
+#define TARGET_RISCV_TCG_RVBNA_H
+
+#include "fpu/softfloat.h"
+
+float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
+                            float_status *fp_status);
+
+float32 rvbna_dot_float8_e4m3_float8_e4m3(const float8_e4m3 a[],
+                                          const float8_e4m3 b[],
+                                          uint32_t n_prod,
+                                          float_status *fp_status);
+float32 rvbna_dot_float8_e4m3_float8_e5m2(const float8_e4m3 a[],
+                                          const float8_e5m2 b[],
+                                          uint32_t n_prod,
+                                          float_status *fp_status);
+float32 rvbna_dot_float8_e5m2_float8_e4m3(const float8_e5m2 a[],
+                                          const float8_e4m3 b[],
+                                          uint32_t n_prod,
+                                          float_status *fp_status);
+float32 rvbna_dot_float8_e5m2_float8_e5m2(const float8_e5m2 a[],
+                                          const float8_e5m2 b[],
+                                          uint32_t n_prod,
+                                          float_status *fp_status);
+float32 rvbna_dot_float16_float16(const float16 a[], const float16 b[],
+                                  uint32_t n_prod,
+                                  float_status *fp_status);
+float32 rvbna_dot_bfloat16_bfloat16(const bfloat16 a[], const bfloat16 b[],
+                                    uint32_t n_prod,
+                                    float_status *fp_status);
+
+#endif
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 917a48b5106..172ae0f11dc 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -31,6 +31,7 @@
 #include "tcg/tcg-gvec-desc.h"
 #include "internals.h"
 #include "vector_internals.h"
+#include "rvbna.h"
 #include <math.h>
 
 static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
-- 
2.56.0

Re: [RFC PATCH 03/38] target/riscv: rvv: Introduce RVBNA algorithm for Zvdota/Zvbdota extensions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> The RISC-V Bulk Normalization Algorithm (RVBNA) is a scheme employed by
> multiple RISC-V extensions (e.g. Zvdota/Zvbdota family) for efficient
> computation of floating-point dot products.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   MAINTAINERS                      |   6 +
>   target/riscv/tcg/meson.build     |   2 +-
>   target/riscv/tcg/rvbna.c         | 185 +++++++++++++++++++++++++++++++
>   target/riscv/tcg/rvbna.h         |  40 +++++++
>   target/riscv/tcg/vector_helper.c |   1 +
>   5 files changed, 233 insertions(+), 1 deletion(-)
>   create mode 100644 target/riscv/tcg/rvbna.c
>   create mode 100644 target/riscv/tcg/rvbna.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 55463103ff1..b91e5925344 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -416,6 +416,12 @@ F: target/riscv/tcg/xsf_helper.c
>   F: disas/riscv-xsf*
>   F: tests/tcg/riscv64/test-xsfvqmacc.S
>   
> +RISC-V Bulk Normalization Algorithm (RVBNA)
> +M: Max Chou <max.chou@sifive.com>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: target/riscv/tcg/rvbna.*
> +
>   RENESAS RX CPUs
>   R: Yoshinori Sato <yoshinori.sato@nifty.com>
>   S: Orphan
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> index 86805b30cbc..3b7821178fc 100644
> --- a/target/riscv/tcg/meson.build
> +++ b/target/riscv/tcg/meson.build
> @@ -10,6 +10,7 @@ riscv_ss.add(files(
>     'fpu_helper.c',
>     'm128_helper.c',
>     'op_helper.c',
> +  'rvbna.c',
>     'translate.c',
>     'tcg-cpu.c',
>     'vcrypto_helper.c',
> @@ -27,4 +28,3 @@ riscv_system_ss.add(files(
>     'th_csr.c',
>   ))
>   
> -
> diff --git a/target/riscv/tcg/rvbna.c b/target/riscv/tcg/rvbna.c
> new file mode 100644
> index 00000000000..f6150e4976d
> --- /dev/null
> +++ b/target/riscv/tcg/rvbna.c
> @@ -0,0 +1,185 @@
> +/*
> + * RISC-V Bulk Normalization Algorithm (RVBNA)
> + *
> + * Copyright (c) 2026 SiFive, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/host-utils.h"
> +#include "fpu/softfloat.h"
> +#include "fpu/softfloat-macros.h"
> +#include "rvbna.h"
> +
> +static inline int rvbna_guard_bits(uint32_t n_prod)
> +{
> +    g_assert(n_prod > 0);
> +    return 32 - clz32(n_prod - 1);
> +}
> +
> +float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
> +                            float_status *fp_status)
> +{
> +    FloatRoundMode old_rm = get_float_rounding_mode(fp_status);
> +    int old_flags = get_float_exception_flags(fp_status);
> +    int new_flags;
> +    float32 result;
> +
> +    set_float_rounding_mode(float_round_to_odd_inf, fp_status);
> +    set_float_exception_flags(0, fp_status);
> +    result = float32_add(partial, accumulator, fp_status);
> +    new_flags = get_float_exception_flags(fp_status) &
> +                (float_flag_invalid | float_flag_overflow);
> +    set_float_rounding_mode(old_rm, fp_status);
> +    set_float_exception_flags(old_flags | new_flags, fp_status);
> +
> +    return result;
> +}
> +
> +#define RVBNA_STACK_THRESHOLD 8
> +
> +#define GEN_RVBNA(TA, TB, TO, A_E, A_M, B_E, B_M, OUT_E, OUT_M)              \
> +TO rvbna_dot_##TA##_##TB(const TA a[], const TB b[], uint32_t n_prod,        \
> +                         float_status *fp_status)                            \
> +{                                                                            \
> +    int32_t stack_ref_exps[RVBNA_STACK_THRESHOLD];                           \
> +    bool stack_signs[RVBNA_STACK_THRESHOLD];                                 \
> +    uint64_t stack_sigs[RVBNA_STACK_THRESHOLD];                              \
> +    int32_t *prod_ref_exps = stack_ref_exps;                                 \
> +    bool *prod_signs = stack_signs;                                          \
> +    uint64_t *prod_sigs = stack_sigs;                                        \
> +    g_autofree int32_t *heap_ref_exps = NULL;                                \
> +    g_autofree bool *heap_signs = NULL;                                      \
> +    g_autofree uint64_t *heap_sigs = NULL;                                   \
> +    int guard_bits = rvbna_guard_bits(n_prod);                               \
> +    int pad = OUT_M - (A_M + B_M) + guard_bits;                              \
> +    int output_bias = (1 << (OUT_E - 1)) - 1;                                \
> +    int a_exp_bias = (1 << (A_E - 1)) - 1;                                   \
> +    int b_exp_bias = (1 << (B_E - 1)) - 1;                                   \
> +    int ref_bias = output_bias - (a_exp_bias + b_exp_bias);                  \
> +    int max_prod_ref_exp = ref_bias;                                         \
> +    int overflow_exp = (1 << OUT_E) - 1;                                     \
> +    int64_t acc = 0;                                                         \
> +    bool nan_result = false;                                                 \
> +    bool inf_result = false;                                                 \
> +    bool inf_sign = false;                                                   \
> +    bool any_pos_inf = false;                                                \
> +    bool any_neg_inf = false;                                                \
> +    bool any_invalid_prod = false;                                           \
> +    bool any_signan = false;                                                 \
> +    bool op_sign_inf, sign, overflow;                                        \
> +    uint32_t i;                                                              \
> +    uint64_t sig;                                                            \
> +    int lead, exp, sig_bits;                                                 \
> +                                                                             \
> +    g_assert(pad >= 0);                                                      \
> +    if (n_prod > RVBNA_STACK_THRESHOLD) {                                    \
> +        heap_ref_exps = g_new(int32_t, n_prod);                              \
> +        heap_signs = g_new(bool, n_prod);                                    \
> +        heap_sigs = g_new(uint64_t, n_prod);                                 \
> +        prod_ref_exps = heap_ref_exps;                                       \
> +        prod_signs = heap_signs;                                             \
> +        prod_sigs = heap_sigs;                                               \
> +    }                                                                        \
> +                                                                             \
> +    for (i = 0; i < n_prod; i++) {                                           \
> +        bool a_sign = TA##_is_neg(a[i]);                                     \
> +        bool b_sign = TB##_is_neg(b[i]);                                     \
> +        bool a_sub = TA##_is_zero_or_denormal(a[i]);                         \
> +        bool b_sub = TB##_is_zero_or_denormal(b[i]);                         \
> +        bool a_zero = TA##_is_zero(a[i]);                                    \
> +        bool b_zero = TB##_is_zero(b[i]);                                    \
> +        bool a_inf = TA##_is_infinity(a[i]);                                 \
> +        bool b_inf = TB##_is_infinity(b[i]);                                 \
> +        bool a_nan = TA##_is_any_nan(a[i]);                                  \
> +        bool b_nan = TB##_is_any_nan(b[i]);                                  \
> +        bool prod_sign = a_sign ^ b_sign;                                    \
> +        bool invalid_prod = (a_inf && b_zero) || (b_inf && a_zero);          \
> +        bool inf_prod_lhs = a_inf && !b_nan && !b_zero;                      \
> +        bool inf_prod_rhs = b_inf && !a_nan && !a_zero;                      \
> +        bool inf_prod = inf_prod_lhs || inf_prod_rhs;                        \
> +        bool invalid_sum = inf_result && inf_prod &&                         \
> +                           (inf_sign != prod_sign);                          \
> +        uint32_t a_mant = extract32(a[i], 0, A_M);                           \
> +        uint32_t b_mant = extract32(b[i], 0, B_M);                           \
> +        bool a_signan = a_nan && TA##_is_signaling_nan(a[i], fp_status);     \
> +        bool b_signan = b_nan && TB##_is_signaling_nan(b[i], fp_status);     \
> +        uint64_t a_sig = a_mant | (!a_sub << A_M);                           \
> +        uint64_t b_sig = b_mant | (!b_sub << B_M);                           \
> +        bool prod_is_zero = a_zero || b_zero;                                \
> +        bool either_inf = a_inf || b_inf;                                    \
> +        bool either_nan = a_nan || b_nan;                                    \
> +                                                                             \
> +        any_invalid_prod |= invalid_prod;                                    \
> +        nan_result |= a_nan || b_nan || any_invalid_prod || invalid_sum;     \
> +        inf_result |= inf_prod;                                              \
> +        inf_sign = inf_prod ? prod_sign : inf_sign;                          \
> +                                                                             \
> +        prod_signs[i] = prod_sign;                                           \
> +        prod_sigs[i] = (uint64_t)(a_sig * b_sig) << pad;                     \
> +        prod_ref_exps[i] = ref_bias;                                         \
> +        if (!prod_is_zero) {                                                 \
> +            prod_ref_exps[i] += (a_sub ? 1 : extract32(a[i], A_M, A_E)) +    \
> +                                (b_sub ? 1 : extract32(b[i], B_M, B_E));     \
> +        }                                                                    \
> +        max_prod_ref_exp = MAX(prod_ref_exps[i], max_prod_ref_exp);          \
> +                                                                             \
> +        any_pos_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
> +                        (a_sign == b_sign));                                 \
> +        any_neg_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
> +                        (a_sign != b_sign));                                 \
> +        any_signan |= a_signan || b_signan;                                  \
> +    }                                                                        \
> +                                                                             \
> +    op_sign_inf = any_pos_inf && any_neg_inf;                                \
> +                                                                             \
> +    if (nan_result) {                                                        \
> +        if (any_signan || any_invalid_prod || op_sign_inf) {                 \
> +            float_raise(float_flag_invalid, fp_status);                      \
> +        }                                                                    \
> +        return TO##_default_nan(fp_status);                                  \
> +    } else if (inf_result) {                                                 \
> +        return TO##_set_sign(TO##_infinity, inf_sign);                       \
> +    }                                                                        \
> +                                                                             \
> +    for (i = 0; i < n_prod; i++) {                                           \
> +        shift64RightJamming(prod_sigs[i],                                    \
> +                            max_prod_ref_exp - prod_ref_exps[i], &sig);      \
> +        acc += prod_signs[i] ? -(int64_t)sig : (int64_t)sig;                 \
> +    }                                                                        \
> +                                                                             \
> +    sign = acc < 0;                                                          \
> +    sig = sign ? -(uint64_t)acc : acc;                                       \
> +    if (sig == 0) {                                                          \
> +        return 0;                                                            \
> +    }                                                                        \
> +                                                                             \
> +    lead = 63 - clz64(sig);                                                  \
> +    exp = max_prod_ref_exp - OUT_M - guard_bits + lead;                      \
> +    overflow = exp >= overflow_exp;                                          \
> +    if (overflow) {                                                          \
> +        float_raise(float_flag_overflow, fp_status);                         \
> +        sig = 0;                                                             \
> +        exp = overflow_exp;                                                  \
> +    } else {                                                                 \
> +        sig_bits = MAX(0, exp <= 0 ? OUT_M - (1 - exp) : OUT_M);             \
> +        if (lead > sig_bits) {                                               \
> +            shift64RightJamming(sig, lead - sig_bits, &sig);                 \
> +        } else {                                                             \
> +            sig <<= (sig_bits - lead);                                       \
> +        }                                                                    \
> +        exp = MAX(exp, 0);                                                   \
> +    }                                                                        \
> +    return (TO)deposit64(deposit64(sig, OUT_M, OUT_E, exp),                  \
> +                         OUT_M + OUT_E,                                      \
> +                         1, sign);                                           \
> +}
> +
> +GEN_RVBNA(float8_e4m3, float8_e4m3, float32, 4, 3, 4, 3, 8, 23)
> +GEN_RVBNA(float8_e4m3, float8_e5m2, float32, 4, 3, 5, 2, 8, 23)
> +GEN_RVBNA(float8_e5m2, float8_e4m3, float32, 5, 2, 4, 3, 8, 23)
> +GEN_RVBNA(float8_e5m2, float8_e5m2, float32, 5, 2, 5, 2, 8, 23)
> +GEN_RVBNA(float16, float16, float32, 5, 10, 5, 10, 8, 23)
> +GEN_RVBNA(bfloat16, bfloat16, float32, 8, 7, 8, 7, 8, 23)
> diff --git a/target/riscv/tcg/rvbna.h b/target/riscv/tcg/rvbna.h
> new file mode 100644
> index 00000000000..d4d3eced952
> --- /dev/null
> +++ b/target/riscv/tcg/rvbna.h
> @@ -0,0 +1,40 @@
> +/*
> + * RISC-V Bulk Normalization Algorithm (RVBNA)
> + *
> + * Copyright (c) 2026 SiFive, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef TARGET_RISCV_TCG_RVBNA_H
> +#define TARGET_RISCV_TCG_RVBNA_H
> +
> +#include "fpu/softfloat.h"
> +
> +float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
> +                            float_status *fp_status);
> +
> +float32 rvbna_dot_float8_e4m3_float8_e4m3(const float8_e4m3 a[],
> +                                          const float8_e4m3 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e4m3_float8_e5m2(const float8_e4m3 a[],
> +                                          const float8_e5m2 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e5m2_float8_e4m3(const float8_e5m2 a[],
> +                                          const float8_e4m3 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e5m2_float8_e5m2(const float8_e5m2 a[],
> +                                          const float8_e5m2 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float16_float16(const float16 a[], const float16 b[],
> +                                  uint32_t n_prod,
> +                                  float_status *fp_status);
> +float32 rvbna_dot_bfloat16_bfloat16(const bfloat16 a[], const bfloat16 b[],
> +                                    uint32_t n_prod,
> +                                    float_status *fp_status);
> +
> +#endif
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 917a48b5106..172ae0f11dc 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -31,6 +31,7 @@
>   #include "tcg/tcg-gvec-desc.h"
>   #include "internals.h"
>   #include "vector_internals.h"
> +#include "rvbna.h"
>   #include <math.h>
>   
>   static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)

Re: [RFC PATCH 03/38] target/riscv: rvv: Introduce RVBNA algorithm for Zvdota/Zvbdota extensions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:18 +0800 Max Chou <max.chou@sifive.com> wrote:

> The RISC-V Bulk Normalization Algorithm (RVBNA) is a scheme employed by
> multiple RISC-V extensions (e.g. Zvdota/Zvbdota family) for efficient
> computation of floating-point dot products.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  MAINTAINERS                      |   6 +
>  target/riscv/tcg/meson.build     |   2 +-
>  target/riscv/tcg/rvbna.c         | 185 +++++++++++++++++++++++++++++++
>  target/riscv/tcg/rvbna.h         |  40 +++++++
>  target/riscv/tcg/vector_helper.c |   1 +
>  5 files changed, 233 insertions(+), 1 deletion(-)
>  create mode 100644 target/riscv/tcg/rvbna.c
>  create mode 100644 target/riscv/tcg/rvbna.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 55463103ff1..b91e5925344 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -416,6 +416,12 @@ F: target/riscv/tcg/xsf_helper.c
>  F: disas/riscv-xsf*
>  F: tests/tcg/riscv64/test-xsfvqmacc.S
>  
> +RISC-V Bulk Normalization Algorithm (RVBNA)
> +M: Max Chou <max.chou@sifive.com>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: target/riscv/tcg/rvbna.*
> +
>  RENESAS RX CPUs
>  R: Yoshinori Sato <yoshinori.sato@nifty.com>
>  S: Orphan
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> index 86805b30cbc..3b7821178fc 100644
> --- a/target/riscv/tcg/meson.build
> +++ b/target/riscv/tcg/meson.build
> @@ -10,6 +10,7 @@ riscv_ss.add(files(
>    'fpu_helper.c',
>    'm128_helper.c',
>    'op_helper.c',
> +  'rvbna.c',
>    'translate.c',
>    'tcg-cpu.c',
>    'vcrypto_helper.c',
> @@ -27,4 +28,3 @@ riscv_system_ss.add(files(
>    'th_csr.c',
>  ))
>  
> -
> diff --git a/target/riscv/tcg/rvbna.c b/target/riscv/tcg/rvbna.c
> new file mode 100644
> index 00000000000..f6150e4976d
> --- /dev/null
> +++ b/target/riscv/tcg/rvbna.c
> @@ -0,0 +1,185 @@
> +/*
> + * RISC-V Bulk Normalization Algorithm (RVBNA)
> + *
> + * Copyright (c) 2026 SiFive, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/host-utils.h"
> +#include "fpu/softfloat.h"
> +#include "fpu/softfloat-macros.h"
> +#include "rvbna.h"
> +
> +static inline int rvbna_guard_bits(uint32_t n_prod)
> +{
> +    g_assert(n_prod > 0);
> +    return 32 - clz32(n_prod - 1);
> +}
> +
> +float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
> +                            float_status *fp_status)
> +{
> +    FloatRoundMode old_rm = get_float_rounding_mode(fp_status);
> +    int old_flags = get_float_exception_flags(fp_status);
> +    int new_flags;
> +    float32 result;
> +
> +    set_float_rounding_mode(float_round_to_odd_inf, fp_status);
> +    set_float_exception_flags(0, fp_status);
Why are we adding this exception flag clear operation?

> +    result = float32_add(partial, accumulator, fp_status);
> +    new_flags = get_float_exception_flags(fp_status) &
> +                (float_flag_invalid | float_flag_overflow);
We can simplify the variable definitions. Using a 'flags' instead of
'old_flags' and 'new_flags' is enough.


Otherwise, looks good to me.

Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> +    set_float_rounding_mode(old_rm, fp_status);
> +    set_float_exception_flags(old_flags | new_flags, fp_status);
> +
> +    return result;
> +}
> +
> +#define RVBNA_STACK_THRESHOLD 8
> +
> +#define GEN_RVBNA(TA, TB, TO, A_E, A_M, B_E, B_M, OUT_E, OUT_M)              \
> +TO rvbna_dot_##TA##_##TB(const TA a[], const TB b[], uint32_t n_prod,        \
> +                         float_status *fp_status)                            \
> +{                                                                            \
> +    int32_t stack_ref_exps[RVBNA_STACK_THRESHOLD];                           \
> +    bool stack_signs[RVBNA_STACK_THRESHOLD];                                 \
> +    uint64_t stack_sigs[RVBNA_STACK_THRESHOLD];                              \
> +    int32_t *prod_ref_exps = stack_ref_exps;                                 \
> +    bool *prod_signs = stack_signs;                                          \
> +    uint64_t *prod_sigs = stack_sigs;                                        \
> +    g_autofree int32_t *heap_ref_exps = NULL;                                \
> +    g_autofree bool *heap_signs = NULL;                                      \
> +    g_autofree uint64_t *heap_sigs = NULL;                                   \
> +    int guard_bits = rvbna_guard_bits(n_prod);                               \
> +    int pad = OUT_M - (A_M + B_M) + guard_bits;                              \
> +    int output_bias = (1 << (OUT_E - 1)) - 1;                                \
> +    int a_exp_bias = (1 << (A_E - 1)) - 1;                                   \
> +    int b_exp_bias = (1 << (B_E - 1)) - 1;                                   \
> +    int ref_bias = output_bias - (a_exp_bias + b_exp_bias);                  \
> +    int max_prod_ref_exp = ref_bias;                                         \
> +    int overflow_exp = (1 << OUT_E) - 1;                                     \
> +    int64_t acc = 0;                                                         \
> +    bool nan_result = false;                                                 \
> +    bool inf_result = false;                                                 \
> +    bool inf_sign = false;                                                   \
> +    bool any_pos_inf = false;                                                \
> +    bool any_neg_inf = false;                                                \
> +    bool any_invalid_prod = false;                                           \
> +    bool any_signan = false;                                                 \
> +    bool op_sign_inf, sign, overflow;                                        \
> +    uint32_t i;                                                              \
> +    uint64_t sig;                                                            \
> +    int lead, exp, sig_bits;                                                 \
> +                                                                             \
> +    g_assert(pad >= 0);                                                      \
> +    if (n_prod > RVBNA_STACK_THRESHOLD) {                                    \
> +        heap_ref_exps = g_new(int32_t, n_prod);                              \
> +        heap_signs = g_new(bool, n_prod);                                    \
> +        heap_sigs = g_new(uint64_t, n_prod);                                 \
> +        prod_ref_exps = heap_ref_exps;                                       \
> +        prod_signs = heap_signs;                                             \
> +        prod_sigs = heap_sigs;                                               \
> +    }                                                                        \
> +                                                                             \
> +    for (i = 0; i < n_prod; i++) {                                           \
> +        bool a_sign = TA##_is_neg(a[i]);                                     \
> +        bool b_sign = TB##_is_neg(b[i]);                                     \
> +        bool a_sub = TA##_is_zero_or_denormal(a[i]);                         \
> +        bool b_sub = TB##_is_zero_or_denormal(b[i]);                         \
> +        bool a_zero = TA##_is_zero(a[i]);                                    \
> +        bool b_zero = TB##_is_zero(b[i]);                                    \
> +        bool a_inf = TA##_is_infinity(a[i]);                                 \
> +        bool b_inf = TB##_is_infinity(b[i]);                                 \
> +        bool a_nan = TA##_is_any_nan(a[i]);                                  \
> +        bool b_nan = TB##_is_any_nan(b[i]);                                  \
> +        bool prod_sign = a_sign ^ b_sign;                                    \
> +        bool invalid_prod = (a_inf && b_zero) || (b_inf && a_zero);          \
> +        bool inf_prod_lhs = a_inf && !b_nan && !b_zero;                      \
> +        bool inf_prod_rhs = b_inf && !a_nan && !a_zero;                      \
> +        bool inf_prod = inf_prod_lhs || inf_prod_rhs;                        \
> +        bool invalid_sum = inf_result && inf_prod &&                         \
> +                           (inf_sign != prod_sign);                          \
> +        uint32_t a_mant = extract32(a[i], 0, A_M);                           \
> +        uint32_t b_mant = extract32(b[i], 0, B_M);                           \
> +        bool a_signan = a_nan && TA##_is_signaling_nan(a[i], fp_status);     \
> +        bool b_signan = b_nan && TB##_is_signaling_nan(b[i], fp_status);     \
> +        uint64_t a_sig = a_mant | (!a_sub << A_M);                           \
> +        uint64_t b_sig = b_mant | (!b_sub << B_M);                           \
> +        bool prod_is_zero = a_zero || b_zero;                                \
> +        bool either_inf = a_inf || b_inf;                                    \
> +        bool either_nan = a_nan || b_nan;                                    \
> +                                                                             \
> +        any_invalid_prod |= invalid_prod;                                    \
> +        nan_result |= a_nan || b_nan || any_invalid_prod || invalid_sum;     \
> +        inf_result |= inf_prod;                                              \
> +        inf_sign = inf_prod ? prod_sign : inf_sign;                          \
> +                                                                             \
> +        prod_signs[i] = prod_sign;                                           \
> +        prod_sigs[i] = (uint64_t)(a_sig * b_sig) << pad;                     \
> +        prod_ref_exps[i] = ref_bias;                                         \
> +        if (!prod_is_zero) {                                                 \
> +            prod_ref_exps[i] += (a_sub ? 1 : extract32(a[i], A_M, A_E)) +    \
> +                                (b_sub ? 1 : extract32(b[i], B_M, B_E));     \
> +        }                                                                    \
> +        max_prod_ref_exp = MAX(prod_ref_exps[i], max_prod_ref_exp);          \
> +                                                                             \
> +        any_pos_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
> +                        (a_sign == b_sign));                                 \
> +        any_neg_inf |= (either_inf && !either_nan && !prod_is_zero &&        \
> +                        (a_sign != b_sign));                                 \
> +        any_signan |= a_signan || b_signan;                                  \
> +    }                                                                        \
> +                                                                             \
> +    op_sign_inf = any_pos_inf && any_neg_inf;                                \
> +                                                                             \
> +    if (nan_result) {                                                        \
> +        if (any_signan || any_invalid_prod || op_sign_inf) {                 \
> +            float_raise(float_flag_invalid, fp_status);                      \
> +        }                                                                    \
> +        return TO##_default_nan(fp_status);                                  \
> +    } else if (inf_result) {                                                 \
> +        return TO##_set_sign(TO##_infinity, inf_sign);                       \
> +    }                                                                        \
> +                                                                             \
> +    for (i = 0; i < n_prod; i++) {                                           \
> +        shift64RightJamming(prod_sigs[i],                                    \
> +                            max_prod_ref_exp - prod_ref_exps[i], &sig);      \
> +        acc += prod_signs[i] ? -(int64_t)sig : (int64_t)sig;                 \
> +    }                                                                        \
> +                                                                             \
> +    sign = acc < 0;                                                          \
> +    sig = sign ? -(uint64_t)acc : acc;                                       \
> +    if (sig == 0) {                                                          \
> +        return 0;                                                            \
> +    }                                                                        \
> +                                                                             \
> +    lead = 63 - clz64(sig);                                                  \
> +    exp = max_prod_ref_exp - OUT_M - guard_bits + lead;                      \
> +    overflow = exp >= overflow_exp;                                          \
> +    if (overflow) {                                                          \
> +        float_raise(float_flag_overflow, fp_status);                         \
> +        sig = 0;                                                             \
> +        exp = overflow_exp;                                                  \
> +    } else {                                                                 \
> +        sig_bits = MAX(0, exp <= 0 ? OUT_M - (1 - exp) : OUT_M);             \
> +        if (lead > sig_bits) {                                               \
> +            shift64RightJamming(sig, lead - sig_bits, &sig);                 \
> +        } else {                                                             \
> +            sig <<= (sig_bits - lead);                                       \
> +        }                                                                    \
> +        exp = MAX(exp, 0);                                                   \
> +    }                                                                        \
> +    return (TO)deposit64(deposit64(sig, OUT_M, OUT_E, exp),                  \
> +                         OUT_M + OUT_E,                                      \
> +                         1, sign);                                           \
> +}
> +
> +GEN_RVBNA(float8_e4m3, float8_e4m3, float32, 4, 3, 4, 3, 8, 23)
> +GEN_RVBNA(float8_e4m3, float8_e5m2, float32, 4, 3, 5, 2, 8, 23)
> +GEN_RVBNA(float8_e5m2, float8_e4m3, float32, 5, 2, 4, 3, 8, 23)
> +GEN_RVBNA(float8_e5m2, float8_e5m2, float32, 5, 2, 5, 2, 8, 23)
> +GEN_RVBNA(float16, float16, float32, 5, 10, 5, 10, 8, 23)
> +GEN_RVBNA(bfloat16, bfloat16, float32, 8, 7, 8, 7, 8, 23)
> diff --git a/target/riscv/tcg/rvbna.h b/target/riscv/tcg/rvbna.h
> new file mode 100644
> index 00000000000..d4d3eced952
> --- /dev/null
> +++ b/target/riscv/tcg/rvbna.h
> @@ -0,0 +1,40 @@
> +/*
> + * RISC-V Bulk Normalization Algorithm (RVBNA)
> + *
> + * Copyright (c) 2026 SiFive, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef TARGET_RISCV_TCG_RVBNA_H
> +#define TARGET_RISCV_TCG_RVBNA_H
> +
> +#include "fpu/softfloat.h"
> +
> +float32 rvbna_final_f32_add(float32 partial, float32 accumulator,
> +                            float_status *fp_status);
> +
> +float32 rvbna_dot_float8_e4m3_float8_e4m3(const float8_e4m3 a[],
> +                                          const float8_e4m3 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e4m3_float8_e5m2(const float8_e4m3 a[],
> +                                          const float8_e5m2 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e5m2_float8_e4m3(const float8_e5m2 a[],
> +                                          const float8_e4m3 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float8_e5m2_float8_e5m2(const float8_e5m2 a[],
> +                                          const float8_e5m2 b[],
> +                                          uint32_t n_prod,
> +                                          float_status *fp_status);
> +float32 rvbna_dot_float16_float16(const float16 a[], const float16 b[],
> +                                  uint32_t n_prod,
> +                                  float_status *fp_status);
> +float32 rvbna_dot_bfloat16_bfloat16(const bfloat16 a[], const bfloat16 b[],
> +                                    uint32_t n_prod,
> +                                    float_status *fp_status);
> +
> +#endif
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 917a48b5106..172ae0f11dc 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -31,6 +31,7 @@
>  #include "tcg/tcg-gvec-desc.h"
>  #include "internals.h"
>  #include "vector_internals.h"
> +#include "rvbna.h"
>  #include <math.h>
>  
>  static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 04/38] target/riscv: Add cfg property for Zvqwdota8i extension

[Max Chou]

Add CPU configuration for the Zvqwdota8i extension which depends on the
Zve32x extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 6 ++++--
 4 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 53ecce8c398..96a1d76c5a2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
+                                    ext_zvqwdota8i),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 85fc3ad8bb8..0c08d688ac1 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_zvqwdota8i)
 BOOL_FIELD(ext_sdext)
 BOOL_FIELD(ext_sdtrig)
 BOOL_FIELD(ext_smaia)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 5834ec1524f..1c51ea94489 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -691,6 +691,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         }
     }
 
+    if (cpu->cfg.ext_zvqwdota8i && !cpu->cfg.ext_zve32x) {
+        error_setg(errp, "Zvqwdota8i extension depends on Zve32x extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 172ae0f11dc..4ba0a89f4b5 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -39,7 +39,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     int xlen = riscv_cpu_xlen(env);
     target_ulong reserved = 0;
 
-    if (riscv_cpu_cfg(env)->ext_zvfbfa) {
+    if (riscv_cpu_cfg(env)->ext_zvfbfa ||
+        riscv_cpu_cfg(env)->ext_zvqwdota8i) {
         reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
     } else {
@@ -88,7 +89,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
 
     switch (vsew) {
     case MO_8:
-        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
+        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvqwdota8i);
         break;
     case MO_16:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
-- 
2.56.0

Re: [RFC PATCH 04/38] target/riscv: Add cfg property for Zvqwdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration for the Zvqwdota8i extension which depends on the
> Zve32x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 6 ++++--
>   4 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 53ecce8c398..96a1d76c5a2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>       ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>       ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwdota8i),
>       ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>       ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>       ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 85fc3ad8bb8..0c08d688ac1 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvqwdota8i)
>   BOOL_FIELD(ext_sdext)
>   BOOL_FIELD(ext_sdtrig)
>   BOOL_FIELD(ext_smaia)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 5834ec1524f..1c51ea94489 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -691,6 +691,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           }
>       }
>   
> +    if (cpu->cfg.ext_zvqwdota8i && !cpu->cfg.ext_zve32x) {
> +        error_setg(errp, "Zvqwdota8i extension depends on Zve32x extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 172ae0f11dc..4ba0a89f4b5 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -39,7 +39,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       int xlen = riscv_cpu_xlen(env);
>       target_ulong reserved = 0;
>   
> -    if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> +    if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>           reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                              xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>       } else {
> @@ -88,7 +89,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>   
>       switch (vsew) {
>       case MO_8:
> -        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
> +        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvqwdota8i);
>           break;
>       case MO_16:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa);

Re: [RFC PATCH 04/38] target/riscv: Add cfg property for Zvqwdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:19 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration for the Zvqwdota8i extension which depends on the
> Zve32x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 6 ++++--
>  4 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 53ecce8c398..96a1d76c5a2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>      ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwdota8i),
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>      ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 85fc3ad8bb8..0c08d688ac1 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvqwdota8i)
>  BOOL_FIELD(ext_sdext)
>  BOOL_FIELD(ext_sdtrig)
>  BOOL_FIELD(ext_smaia)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 5834ec1524f..1c51ea94489 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -691,6 +691,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          }
>      }
>  
> +    if (cpu->cfg.ext_zvqwdota8i && !cpu->cfg.ext_zve32x) {
> +        error_setg(errp, "Zvqwdota8i extension depends on Zve32x extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 172ae0f11dc..4ba0a89f4b5 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -39,7 +39,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      int xlen = riscv_cpu_xlen(env);
>      target_ulong reserved = 0;
>  
> -    if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> +    if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>          reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>      } else {
> @@ -88,7 +89,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>  
>      switch (vsew) {
>      case MO_8:
> -        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
> +        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvqwdota8i);
>          break;
>      case MO_16:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 05/38] target/riscv: Add implied rules for Zvqwdota8i extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvqwdota8i
extension.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 96a1d76c5a2..08b14782451 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2851,6 +2851,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvkn),
     .implied_multi_exts = {
@@ -3055,6 +3064,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVKS_IMPLIED,
     &ZVKSC_IMPLIED,
     &ZVKSG_IMPLIED,
+    &ZVQWDOTA8I_IMPLIED,
     &SHA_IMPLIED,
     &SSCFG_IMPLIED,
     &SUPM_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 05/38] target/riscv: Add implied rules for Zvqwdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvqwdota8i
> extension.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 96a1d76c5a2..08b14782451 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2851,6 +2851,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvkn),
>       .implied_multi_exts = {
> @@ -3055,6 +3064,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVKS_IMPLIED,
>       &ZVKSC_IMPLIED,
>       &ZVKSG_IMPLIED,
> +    &ZVQWDOTA8I_IMPLIED,
>       &SHA_IMPLIED,
>       &SSCFG_IMPLIED,
>       &SUPM_IMPLIED,

Re: [RFC PATCH 05/38] target/riscv: Add implied rules for Zvqwdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:20 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvqwdota8i
> extension.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 96a1d76c5a2..08b14782451 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2851,6 +2851,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvkn),
>      .implied_multi_exts = {
> @@ -3055,6 +3064,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVKS_IMPLIED,
>      &ZVKSC_IMPLIED,
>      &ZVKSG_IMPLIED,
> +    &ZVQWDOTA8I_IMPLIED,
>      &SHA_IMPLIED,
>      &SSCFG_IMPLIED,
>      &SUPM_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 06/38] target/riscv: rvv: Implement Zvqwdota8i instructions

[Max Chou]

Implement the vqwdotau.vv and vqwdotas.vv instructions from the
Zvqwdota8i extension. These instructions compute a dot product between
two 8-bit integer vectors, accumulating into a 32-bit scalar in vd[0].

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  4 ++
 target/riscv/insn32.decode                  |  4 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 63 +++++++++++++++++++++
 target/riscv/tcg/vector_helper.c            | 49 ++++++++++++++++
 4 files changed, 120 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1cffcad580c..767b04658b4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1387,6 +1387,10 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
 /* Zalrsc SC write probe */
 DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
 
+/* Zvqwdota8i - 8-bit Integer Dot Product */
+DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
 DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 795badc8a7d..cc7d639ab73 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1097,3 +1097,7 @@ vwabda_vv     111101 . ..... ..... 000 ..... 1010111 @r_vm
 vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
 vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
 vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
+
+# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
+vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
+vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index 7e1295f33e7..befdbf273e5 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4132,7 +4132,70 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
     return false;                                                       \
 }
 
+/* Zvqwdota8i 8-bit Integer Dot-Product Extension */
+static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
+{
+    return require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           s->vstart_eq_zero &&
+           require_align(a->rs1, s->lmul) &&
+           require_align(a->rs2, s->lmul) &&
+           require_vm(a->vm, a->rd) &&
+           require_noover(a->rd, 0, a->rs1, s->lmul) &&
+           require_noover(a->rd, 0, a->rs2, s->lmul) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm);
+}
+
+static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
+{
+    return vext_zvdota_base_check(s, a) &&
+           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
+}
+
+typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+                                   TCGv_env, TCGv_i32);
+
+#define GEN_ZVDOTA_INT_TRANS(NAME, CHECK)                               \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
+{                                                                       \
+    static gen_helper_zvdota_int * const fns[2] = {                     \
+        gen_helper_##NAME##_b, NULL,                                    \
+    };                                                                  \
+    if (CHECK(s, a)) {                                                  \
+        TCGv_ptr dest, src1, src2, mask;                                \
+        TCGv_i32 desc;                                                  \
+        uint32_t data = 0;                                              \
+                                                                        \
+        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
+                                                                        \
+        dest = tcg_temp_new_ptr();                                      \
+        mask = tcg_temp_new_ptr();                                      \
+        src1 = tcg_temp_new_ptr();                                      \
+        src2 = tcg_temp_new_ptr();                                      \
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
+                                          s->cfg_ptr->vlenb, data));    \
+                                                                        \
+        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
+        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
+                                                                        \
+        fns[s->sew](dest, mask, src1, src2, tcg_env, desc);             \
+                                                                        \
+        finalize_rvv_inst(s);                                           \
+                                                                        \
+        return true;                                                    \
+    }                                                                   \
+    return false;                                                       \
+}
+
 GEN_ABD_OPIVV_WIDEN_TRANS(vwabda_vv, vwabd_vv_check)
 GEN_ABD_OPIVX_WIDEN_TRANS(vwabda_vx, vwabd_vx_check)
 GEN_ABD_OPIVV_WIDEN_TRANS(vwabdau_vv, vwabd_vv_check)
 GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
+
+GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
+GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 4ba0a89f4b5..6abcf522648 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -5970,3 +5970,52 @@ GEN_VEXT_VV(vwabdau_vv_b, 2)
 GEN_VEXT_VV(vwabdau_vv_h, 4)
 GEN_VEXT_VX(vwabdau_vx_b, 2)
 GEN_VEXT_VX(vwabdau_vx_h, 4)
+
+/*
+ * Zvqwdota8i: 8-bit Integer Dot Product with Accumulation
+ */
+#define GEN_VEXT_ZVDOTA_INT(NAME, WD, W1, T2, HD, HS)            \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
+                  CPURISCVState *env, uint32_t desc)             \
+{                                                                \
+    uint32_t vm = vext_vm(desc);                                 \
+    uint32_t vl = env->vl;                                       \
+    uint32_t vta = vext_vta(desc);                               \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                 \
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;                  \
+    uint32_t total_elems = vlenb >> ctzl(sizeof(uint##WD##_t));  \
+    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);      \
+    uint32_t i;                                                  \
+    uint##WD##_t acc, dot_result, a;                             \
+                                                                 \
+    VSTART_CHECK_EARLY_EXIT(env, vl);                            \
+                                                                 \
+    acc = *((uint##WD##_t *)vd + HD(0));                         \
+    dot_result = 0;                                              \
+                                                                 \
+    for (i = 0; i < vl; i++) {                                   \
+        if (!vm && !vext_elem_mask(v0, i)) {                     \
+            continue;                                            \
+        }                                                        \
+                                                                 \
+        uint##WD##_t b = *((T2 *)vs2 + HS(i));                   \
+        if (altfmt) {                                            \
+            a = *((int##W1##_t *)vs1 + HS(i));                   \
+        } else {                                                 \
+            a = *((uint##W1##_t *)vs1 + HS(i));                  \
+        }                                                        \
+        dot_result += (a * b);                                   \
+    }                                                            \
+                                                                 \
+    *((uint##WD##_t *)vd + HD(0)) = acc + dot_result;            \
+                                                                 \
+    env->vstart = 0;                                             \
+                                                                 \
+    if (vta_all_1s) {                                            \
+        vext_set_elems_1s(vd, vta, sizeof(int##WD##_t),          \
+                          total_elems * sizeof(int##WD##_t));    \
+    }                                                            \
+}
+
+GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
+GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
-- 
2.56.0

Re: [RFC PATCH 06/38] target/riscv: rvv: Implement Zvqwdota8i instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Implement the vqwdotau.vv and vqwdotas.vv instructions from the
> Zvqwdota8i extension. These instructions compute a dot product between
> two 8-bit integer vectors, accumulating into a 32-bit scalar in vd[0].
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/helper.h                       |  4 ++
>   target/riscv/insn32.decode                  |  4 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 63 +++++++++++++++++++++
>   target/riscv/tcg/vector_helper.c            | 49 ++++++++++++++++
>   4 files changed, 120 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1cffcad580c..767b04658b4 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1387,6 +1387,10 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
>   /* Zalrsc SC write probe */
>   DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
>   
> +/* Zvqwdota8i - 8-bit Integer Dot Product */
> +DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 795badc8a7d..cc7d639ab73 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1097,3 +1097,7 @@ vwabda_vv     111101 . ..... ..... 000 ..... 1010111 @r_vm
>   vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
>   vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
>   vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
> +
> +# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
> +vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
> +vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 7e1295f33e7..befdbf273e5 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4132,7 +4132,70 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>       return false;                                                       \
>   }
>   
> +/* Zvqwdota8i 8-bit Integer Dot-Product Extension */
> +static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
> +{
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           s->vstart_eq_zero &&
> +           require_align(a->rs1, s->lmul) &&
> +           require_align(a->rs2, s->lmul) &&
> +           require_vm(a->vm, a->rd) &&
> +           require_noover(a->rd, 0, a->rs1, s->lmul) &&
> +           require_noover(a->rd, 0, a->rs2, s->lmul) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm);
> +}
> +
> +static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
> +}
> +
> +typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                   TCGv_env, TCGv_i32);
> +
> +#define GEN_ZVDOTA_INT_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
> +{                                                                       \
> +    static gen_helper_zvdota_int * const fns[2] = {                     \
> +        gen_helper_##NAME##_b, NULL,                                    \
> +    };                                                                  \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 desc;                                                  \
> +        uint32_t data = 0;                                              \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        fns[s->sew](dest, mask, src1, src2, tcg_env, desc);             \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
>   GEN_ABD_OPIVV_WIDEN_TRANS(vwabda_vv, vwabd_vv_check)
>   GEN_ABD_OPIVX_WIDEN_TRANS(vwabda_vx, vwabd_vx_check)
>   GEN_ABD_OPIVV_WIDEN_TRANS(vwabdau_vv, vwabd_vv_check)
>   GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
> +
> +GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
> +GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 4ba0a89f4b5..6abcf522648 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -5970,3 +5970,52 @@ GEN_VEXT_VV(vwabdau_vv_b, 2)
>   GEN_VEXT_VV(vwabdau_vv_h, 4)
>   GEN_VEXT_VX(vwabdau_vx_b, 2)
>   GEN_VEXT_VX(vwabdau_vx_h, 4)
> +
> +/*
> + * Zvqwdota8i: 8-bit Integer Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVDOTA_INT(NAME, WD, W1, T2, HD, HS)            \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
> +                  CPURISCVState *env, uint32_t desc)             \
> +{                                                                \
> +    uint32_t vm = vext_vm(desc);                                 \
> +    uint32_t vl = env->vl;                                       \
> +    uint32_t vta = vext_vta(desc);                               \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                 \
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;                  \
> +    uint32_t total_elems = vlenb >> ctzl(sizeof(uint##WD##_t));  \
> +    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);      \
> +    uint32_t i;                                                  \
> +    uint##WD##_t acc, dot_result, a;                             \
> +                                                                 \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                            \
> +                                                                 \
> +    acc = *((uint##WD##_t *)vd + HD(0));                         \
> +    dot_result = 0;                                              \
> +                                                                 \
> +    for (i = 0; i < vl; i++) {                                   \
> +        if (!vm && !vext_elem_mask(v0, i)) {                     \
> +            continue;                                            \
> +        }                                                        \
> +                                                                 \
> +        uint##WD##_t b = *((T2 *)vs2 + HS(i));                   \
> +        if (altfmt) {                                            \
> +            a = *((int##W1##_t *)vs1 + HS(i));                   \
> +        } else {                                                 \
> +            a = *((uint##W1##_t *)vs1 + HS(i));                  \
> +        }                                                        \
> +        dot_result += (a * b);                                   \
> +    }                                                            \
> +                                                                 \
> +    *((uint##WD##_t *)vd + HD(0)) = acc + dot_result;            \
> +                                                                 \
> +    env->vstart = 0;                                             \
> +                                                                 \
> +    if (vta_all_1s) {                                            \
> +        vext_set_elems_1s(vd, vta, sizeof(int##WD##_t),          \
> +                          total_elems * sizeof(int##WD##_t));    \
> +    }                                                            \
> +}
> +
> +GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
> +GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)

Re: [RFC PATCH 06/38] target/riscv: rvv: Implement Zvqwdota8i instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:21 +0800 Max Chou <max.chou@sifive.com> wrote:

> Implement the vqwdotau.vv and vqwdotas.vv instructions from the
> Zvqwdota8i extension. These instructions compute a dot product between
> two 8-bit integer vectors, accumulating into a 32-bit scalar in vd[0].
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/helper.h                       |  4 ++
>  target/riscv/insn32.decode                  |  4 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 63 +++++++++++++++++++++
>  target/riscv/tcg/vector_helper.c            | 49 ++++++++++++++++
>  4 files changed, 120 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1cffcad580c..767b04658b4 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1387,6 +1387,10 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
>  /* Zalrsc SC write probe */
>  DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
>  
> +/* Zvqwdota8i - 8-bit Integer Dot Product */
> +DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 795badc8a7d..cc7d639ab73 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1097,3 +1097,7 @@ vwabda_vv     111101 . ..... ..... 000 ..... 1010111 @r_vm
>  vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
>  vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
>  vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
> +
> +# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
> +vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
> +vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 7e1295f33e7..befdbf273e5 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4132,7 +4132,70 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>      return false;                                                       \
>  }
>  
> +/* Zvqwdota8i 8-bit Integer Dot-Product Extension */
> +static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
> +{
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           s->vstart_eq_zero &&
> +           require_align(a->rs1, s->lmul) &&
> +           require_align(a->rs2, s->lmul) &&
> +           require_vm(a->vm, a->rd) &&
> +           require_noover(a->rd, 0, a->rs1, s->lmul) &&
> +           require_noover(a->rd, 0, a->rs2, s->lmul) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm);
> +}
> +
> +static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
> +}
> +
> +typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                   TCGv_env, TCGv_i32);
> +
> +#define GEN_ZVDOTA_INT_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
> +{                                                                       \
> +    static gen_helper_zvdota_int * const fns[2] = {                     \
> +        gen_helper_##NAME##_b, NULL,                                    \
> +    };                                                                  \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 desc;                                                  \
> +        uint32_t data = 0;                                              \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        fns[s->sew](dest, mask, src1, src2, tcg_env, desc);             \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
>  GEN_ABD_OPIVV_WIDEN_TRANS(vwabda_vv, vwabd_vv_check)
>  GEN_ABD_OPIVX_WIDEN_TRANS(vwabda_vx, vwabd_vx_check)
>  GEN_ABD_OPIVV_WIDEN_TRANS(vwabdau_vv, vwabd_vv_check)
>  GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
> +
> +GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
> +GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 4ba0a89f4b5..6abcf522648 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -5970,3 +5970,52 @@ GEN_VEXT_VV(vwabdau_vv_b, 2)
>  GEN_VEXT_VV(vwabdau_vv_h, 4)
>  GEN_VEXT_VX(vwabdau_vx_b, 2)
>  GEN_VEXT_VX(vwabdau_vx_h, 4)
> +
> +/*
> + * Zvqwdota8i: 8-bit Integer Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVDOTA_INT(NAME, WD, W1, T2, HD, HS)            \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
> +                  CPURISCVState *env, uint32_t desc)             \
> +{                                                                \
> +    uint32_t vm = vext_vm(desc);                                 \
> +    uint32_t vl = env->vl;                                       \
> +    uint32_t vta = vext_vta(desc);                               \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                 \
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;                  \
> +    uint32_t total_elems = vlenb >> ctzl(sizeof(uint##WD##_t));  \
> +    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);      \
> +    uint32_t i;                                                  \
> +    uint##WD##_t acc, dot_result, a;                             \
> +                                                                 \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                            \
> +                                                                 \
> +    acc = *((uint##WD##_t *)vd + HD(0));                         \
> +    dot_result = 0;                                              \
> +                                                                 \
> +    for (i = 0; i < vl; i++) {                                   \
> +        if (!vm && !vext_elem_mask(v0, i)) {                     \
> +            continue;                                            \
> +        }                                                        \
> +                                                                 \
> +        uint##WD##_t b = *((T2 *)vs2 + HS(i));                   \
> +        if (altfmt) {                                            \
> +            a = *((int##W1##_t *)vs1 + HS(i));                   \
> +        } else {                                                 \
> +            a = *((uint##W1##_t *)vs1 + HS(i));                  \
> +        }                                                        \
> +        dot_result += (a * b);                                   \
> +    }                                                            \
> +                                                                 \
> +    *((uint##WD##_t *)vd + HD(0)) = acc + dot_result;            \
> +                                                                 \
> +    env->vstart = 0;                                             \
> +                                                                 \
> +    if (vta_all_1s) {                                            \
> +        vext_set_elems_1s(vd, vta, sizeof(int##WD##_t),          \
> +                          total_elems * sizeof(int##WD##_t));    \
> +    }                                                            \
> +}
> +
> +GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
> +GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 07/38] disas/riscv: Support Zvqwdota8i extension

[Max Chou]

Adds support of Zvqwdota8i extensions:
- vqwdotau.vv
- vqwdotas.vv

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 2 ++
 disas/riscv.c        | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 425473ee61b..ec767ccbf8b 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -770,6 +770,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
 OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
 OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index ca0d6e90b37..2acded0c915 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2634,6 +2634,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
             }
             break;
         case 29:
+            if (((inst >> 12) & 0b111) == 0) {
+                switch ((inst >> 26) & 0b111111) {
+                case 38: return &op_vqwdotau_vv;
+                case 39: return &op_vqwdotas_vv;
+                }
+            }
             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
                 switch ((inst >> 26) & 0b111111) {
                 case 32: return &op_vsm3me_vv;
-- 
2.56.0

Re: [RFC PATCH 07/38] disas/riscv: Support Zvqwdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support of Zvqwdota8i extensions:
> - vqwdotau.vv
> - vqwdotas.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 2 ++
>   disas/riscv.c        | 6 ++++++
>   2 files changed, 8 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 425473ee61b..ec767ccbf8b 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -770,6 +770,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>   OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
>   OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ca0d6e90b37..2acded0c915 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2634,6 +2634,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>               }
>               break;
>           case 29:
> +            if (((inst >> 12) & 0b111) == 0) {
> +                switch ((inst >> 26) & 0b111111) {
> +                case 38: return &op_vqwdotau_vv;
> +                case 39: return &op_vqwdotas_vv;
> +                }
> +            }
>               if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                   switch ((inst >> 26) & 0b111111) {
>                   case 32: return &op_vsm3me_vv;

Re: [RFC PATCH 07/38] disas/riscv: Support Zvqwdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:22 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support of Zvqwdota8i extensions:
> - vqwdotau.vv
> - vqwdotas.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  disas/riscv-op.c.inc | 2 ++
>  disas/riscv.c        | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 425473ee61b..ec767ccbf8b 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -770,6 +770,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>  OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
>  OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ca0d6e90b37..2acded0c915 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2634,6 +2634,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>              }
>              break;
>          case 29:
> +            if (((inst >> 12) & 0b111) == 0) {
> +                switch ((inst >> 26) & 0b111111) {
> +                case 38: return &op_vqwdotau_vv;
> +                case 39: return &op_vqwdotas_vv;
> +                }
> +            }
>              if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                  switch ((inst >> 26) & 0b111111) {
>                  case 32: return &op_vsm3me_vv;
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 08/38] target/riscv: Add Zvqwdota16i cpu property

[Max Chou]

Add CPU configuration property of Zvqwdota16i extension which depends on
the Zve64x extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 4 +++-
 4 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 08b14782451..7873e67c053 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
+                                    ext_zvqwdota16i),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
                                     ext_zvqwdota8i),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 0c08d688ac1..8bac69a17f7 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_zvqwdota16i)
 BOOL_FIELD(ext_zvqwdota8i)
 BOOL_FIELD(ext_sdext)
 BOOL_FIELD(ext_sdtrig)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 1c51ea94489..54749125acf 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -696,6 +696,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvqwdota16i && !cpu->cfg.ext_zve64x) {
+        error_setg(errp, "Zvqwdota16i extension depends on Zve64x extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 6abcf522648..6d79fb5d299 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     target_ulong reserved = 0;
 
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
+        riscv_cpu_cfg(env)->ext_zvqwdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwdota8i) {
         reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
@@ -93,7 +94,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
                         cpu->cfg.ext_zvqwdota8i);
         break;
     case MO_16:
-        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
+        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvqwdota16i);
         break;
     default:
         break;
-- 
2.56.0

Re: [RFC PATCH 08/38] target/riscv: Add Zvqwdota16i cpu property

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvqwdota16i extension which depends on
> the Zve64x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 4 +++-
>   4 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 08b14782451..7873e67c053 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>       ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>       ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwdota16i),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
>                                       ext_zvqwdota8i),
>       ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 0c08d688ac1..8bac69a17f7 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvqwdota16i)
>   BOOL_FIELD(ext_zvqwdota8i)
>   BOOL_FIELD(ext_sdext)
>   BOOL_FIELD(ext_sdtrig)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 1c51ea94489..54749125acf 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -696,6 +696,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvqwdota16i && !cpu->cfg.ext_zve64x) {
> +        error_setg(errp, "Zvqwdota16i extension depends on Zve64x extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6abcf522648..6d79fb5d299 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       target_ulong reserved = 0;
>   
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>           reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                              xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> @@ -93,7 +94,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>                           cpu->cfg.ext_zvqwdota8i);
>           break;
>       case MO_16:
> -        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
> +        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvqwdota16i);
>           break;
>       default:
>           break;

Re: [RFC PATCH 08/38] target/riscv: Add Zvqwdota16i cpu property

[Chao Liu]

On Thu,  5 Nov 2026 03:41:23 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvqwdota16i extension which depends on
> the Zve64x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 4 +++-
>  4 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 08b14782451..7873e67c053 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -250,6 +250,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>      ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwdota16i),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
>                                      ext_zvqwdota8i),
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 0c08d688ac1..8bac69a17f7 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvqwdota16i)
>  BOOL_FIELD(ext_zvqwdota8i)
>  BOOL_FIELD(ext_sdext)
>  BOOL_FIELD(ext_sdtrig)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 1c51ea94489..54749125acf 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -696,6 +696,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvqwdota16i && !cpu->cfg.ext_zve64x) {
> +        error_setg(errp, "Zvqwdota16i extension depends on Zve64x extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6abcf522648..6d79fb5d299 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      target_ulong reserved = 0;
>  
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>          reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
>                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> @@ -93,7 +94,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>                          cpu->cfg.ext_zvqwdota8i);
>          break;
>      case MO_16:
> -        ill_altfmt &= !(cpu->cfg.ext_zvfbfa);
> +        ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvqwdota16i);
>          break;
>      default:
>          break;
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 09/38] target/riscv: Add Zvqwdota16i dependency imply rule

[Max Chou]

According to the Zvbdota isa spec, Zvqwdota16i requires Zve64x.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7873e67c053..ae859128d30 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2853,6 +2853,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVQWDOTA16I_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvqwdota16i),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve64x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
     .implied_multi_exts = {
@@ -3066,6 +3075,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVKS_IMPLIED,
     &ZVKSC_IMPLIED,
     &ZVKSG_IMPLIED,
+    &ZVQWDOTA16I_IMPLIED,
     &ZVQWDOTA8I_IMPLIED,
     &SHA_IMPLIED,
     &SSCFG_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 09/38] target/riscv: Add Zvqwdota16i dependency imply rule

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> According to the Zvbdota isa spec, Zvqwdota16i requires Zve64x.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7873e67c053..ae859128d30 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2853,6 +2853,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVQWDOTA16I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwdota16i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve64x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
>       .implied_multi_exts = {
> @@ -3066,6 +3075,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVKS_IMPLIED,
>       &ZVKSC_IMPLIED,
>       &ZVKSG_IMPLIED,
> +    &ZVQWDOTA16I_IMPLIED,
>       &ZVQWDOTA8I_IMPLIED,
>       &SHA_IMPLIED,
>       &SSCFG_IMPLIED,

Re: [RFC PATCH 09/38] target/riscv: Add Zvqwdota16i dependency imply rule

[Chao Liu]

On Thu,  5 Nov 2026 03:41:24 +0800 Max Chou <max.chou@sifive.com> wrote:

> According to the Zvbdota isa spec, Zvqwdota16i requires Zve64x.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7873e67c053..ae859128d30 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2853,6 +2853,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVQWDOTA16I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwdota16i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve64x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvqwdota8i),
>      .implied_multi_exts = {
> @@ -3066,6 +3075,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVKS_IMPLIED,
>      &ZVKSC_IMPLIED,
>      &ZVKSG_IMPLIED,
> +    &ZVQWDOTA16I_IMPLIED,
>      &ZVQWDOTA8I_IMPLIED,
>      &SHA_IMPLIED,
>      &SSCFG_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 10/38] target/riscv: rvv: Implement Zvqwdota16i instructions

[Max Chou]

Extend existing vqwdota* instructions to support both SEW=8
(Zvqwdota8i) and SEW=16 (Zvqwdota16i).

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       | 4 +++-
 target/riscv/insn32.decode                  | 2 +-
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
 target/riscv/tcg/vector_helper.c            | 2 ++
 4 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 767b04658b4..23d3e9b3c43 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1387,9 +1387,11 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
 /* Zalrsc SC write probe */
 DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
 
-/* Zvqwdota8i - 8-bit Integer Dot Product */
+/* Zvqwdota8i/Zvqwdota16i - 8/16-bit Integer Dot Product */
 DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cc7d639ab73..b8a5d0567b1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1098,6 +1098,6 @@ vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
 vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
 vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
 
-# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
+# *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
 vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
 vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index befdbf273e5..fcff472a2ea 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4149,7 +4149,8 @@ static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
 static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
 {
     return vext_zvdota_base_check(s, a) &&
-           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
+           ((s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8) ||
+            (s->cfg_ptr->ext_zvqwdota16i && s->sew == MO_16));
 }
 
 typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
@@ -4159,7 +4160,7 @@ typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
 {                                                                       \
     static gen_helper_zvdota_int * const fns[2] = {                     \
-        gen_helper_##NAME##_b, NULL,                                    \
+        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                   \
     };                                                                  \
     if (CHECK(s, a)) {                                                  \
         TCGv_ptr dest, src1, src2, mask;                                \
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 6d79fb5d299..57a381098f6 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6021,3 +6021,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
 
 GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
 GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
+GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
+GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)
-- 
2.56.0

Re: [RFC PATCH 10/38] target/riscv: rvv: Implement Zvqwdota16i instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Extend existing vqwdota* instructions to support both SEW=8
> (Zvqwdota8i) and SEW=16 (Zvqwdota16i).
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/helper.h                       | 4 +++-
>   target/riscv/insn32.decode                  | 2 +-
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
>   target/riscv/tcg/vector_helper.c            | 2 ++
>   4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 767b04658b4..23d3e9b3c43 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1387,9 +1387,11 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
>   /* Zalrsc SC write probe */
>   DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
>   
> -/* Zvqwdota8i - 8-bit Integer Dot Product */
> +/* Zvqwdota8i/Zvqwdota16i - 8/16-bit Integer Dot Product */
>   DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>   
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index cc7d639ab73..b8a5d0567b1 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1098,6 +1098,6 @@ vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
>   vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
>   vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
>   
> -# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
> +# *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
>   vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
>   vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index befdbf273e5..fcff472a2ea 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4149,7 +4149,8 @@ static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
>   static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
>   {
>       return vext_zvdota_base_check(s, a) &&
> -           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
> +           ((s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8) ||
> +            (s->cfg_ptr->ext_zvqwdota16i && s->sew == MO_16));
>   }
>   
>   typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> @@ -4159,7 +4160,7 @@ typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>   {                                                                       \
>       static gen_helper_zvdota_int * const fns[2] = {                     \
> -        gen_helper_##NAME##_b, NULL,                                    \
> +        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                   \
>       };                                                                  \
>       if (CHECK(s, a)) {                                                  \
>           TCGv_ptr dest, src1, src2, mask;                                \
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6d79fb5d299..57a381098f6 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6021,3 +6021,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
>   
>   GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
>   GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
> +GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
> +GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)

Re: [RFC PATCH 10/38] target/riscv: rvv: Implement Zvqwdota16i instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:25 +0800 Max Chou <max.chou@sifive.com> wrote:

> Extend existing vqwdota* instructions to support both SEW=8
> (Zvqwdota8i) and SEW=16 (Zvqwdota16i).
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/helper.h                       | 4 +++-
>  target/riscv/insn32.decode                  | 2 +-
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
>  target/riscv/tcg/vector_helper.c            | 2 ++
>  4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 767b04658b4..23d3e9b3c43 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1387,9 +1387,11 @@ DEF_HELPER_1(ssamoswap_disabled, void, env)
>  /* Zalrsc SC write probe */
>  DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)
>  
> -/* Zvqwdota8i - 8-bit Integer Dot Product */
> +/* Zvqwdota8i/Zvqwdota16i - 8/16-bit Integer Dot Product */
>  DEF_HELPER_6(vqwdotau_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>  
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index cc7d639ab73..b8a5d0567b1 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1098,6 +1098,6 @@ vwabda_vx     111101 . ..... ..... 100 ..... 1010111 @r_vm
>  vwabdau_vv    111110 . ..... ..... 000 ..... 1010111 @r_vm
>  vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
>  
> -# *** Zvqwdota8i 8-bit Integer Dot-Product Extension ***
> +# *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
>  vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
>  vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index befdbf273e5..fcff472a2ea 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4149,7 +4149,8 @@ static bool vext_zvdota_base_check(DisasContext *s, arg_rmrr * a)
>  static bool vext_vqwdota_check(DisasContext *s, arg_rmrr *a)
>  {
>      return vext_zvdota_base_check(s, a) &&
> -           (s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8);
> +           ((s->cfg_ptr->ext_zvqwdota8i && s->sew == MO_8) ||
> +            (s->cfg_ptr->ext_zvqwdota16i && s->sew == MO_16));
>  }
>  
>  typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> @@ -4159,7 +4160,7 @@ typedef void gen_helper_zvdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
>  static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>  {                                                                       \
>      static gen_helper_zvdota_int * const fns[2] = {                     \
> -        gen_helper_##NAME##_b, NULL,                                    \
> +        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                   \
>      };                                                                  \
>      if (CHECK(s, a)) {                                                  \
>          TCGv_ptr dest, src1, src2, mask;                                \
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6d79fb5d299..57a381098f6 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6021,3 +6021,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,      \
>  
>  GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
>  GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
> +GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
> +GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 11/38] target/riscv: Add cfg property for Zvfwdota16bf extension

[Max Chou]

Add CPU configuration property of Zvfwdota16bf extension which depends on
the Zve32f extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ae859128d30..d6e2b07c401 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
+                                    ext_zvfwdota16bf),
     ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
     ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
     ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 8bac69a17f7..30c404863c8 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_zvfwdota16bf)
 BOOL_FIELD(ext_zvqwdota16i)
 BOOL_FIELD(ext_zvqwdota8i)
 BOOL_FIELD(ext_sdext)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 54749125acf..91e009072e6 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -701,6 +701,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfwdota16bf && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfwdota16bf extension depends on Zve32f extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 57a381098f6..41b526d25ef 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     target_ulong reserved = 0;
 
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
+        riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
         riscv_cpu_cfg(env)->ext_zvqwdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwdota8i) {
         reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
@@ -95,6 +96,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
         break;
     case MO_16:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvfwdota16bf ||
                         cpu->cfg.ext_zvqwdota16i);
         break;
     default:
-- 
2.56.0

Re: [RFC PATCH 11/38] target/riscv: Add cfg property for Zvfwdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvfwdota16bf extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ae859128d30..d6e2b07c401 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>       ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>       ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
> +                                    ext_zvfwdota16bf),
>       ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
>       ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
>       ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 8bac69a17f7..30c404863c8 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfwdota16bf)
>   BOOL_FIELD(ext_zvqwdota16i)
>   BOOL_FIELD(ext_zvqwdota8i)
>   BOOL_FIELD(ext_sdext)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 54749125acf..91e009072e6 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -701,6 +701,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfwdota16bf && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfwdota16bf extension depends on Zve32f extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 57a381098f6..41b526d25ef 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       target_ulong reserved = 0;
>   
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>           riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>           reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> @@ -95,6 +96,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>           break;
>       case MO_16:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfwdota16bf ||
>                           cpu->cfg.ext_zvqwdota16i);
>           break;
>       default:

Re: [RFC PATCH 11/38] target/riscv: Add cfg property for Zvfwdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:26 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvfwdota16bf extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ae859128d30..d6e2b07c401 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>      ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
> +                                    ext_zvfwdota16bf),
>      ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
>      ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
>      ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 8bac69a17f7..30c404863c8 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfwdota16bf)
>  BOOL_FIELD(ext_zvqwdota16i)
>  BOOL_FIELD(ext_zvqwdota8i)
>  BOOL_FIELD(ext_sdext)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 54749125acf..91e009072e6 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -701,6 +701,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvfwdota16bf && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfwdota16bf extension depends on Zve32f extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 57a381098f6..41b526d25ef 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      target_ulong reserved = 0;
>  
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>          riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>          reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> @@ -95,6 +96,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>          break;
>      case MO_16:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfwdota16bf ||
>                          cpu->cfg.ext_zvqwdota16i);
>          break;
>      default:
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 12/38] target/riscv: Add implied rules for Zvfwdota16bf extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvfwdota16bf
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d6e2b07c401..2d905a99d68 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2873,6 +2873,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32f),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvkn),
     .implied_multi_exts = {
@@ -3070,6 +3079,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVFBFWMA_IMPLIED,
     &ZVFH_IMPLIED,
     &ZVFHMIN_IMPLIED,
+    &ZVFWDOTA16BF_IMPLIED,
     &ZVKN_IMPLIED,
     &ZVKNC_IMPLIED,
     &ZVKNG_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 12/38] target/riscv: Add implied rules for Zvfwdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfwdota16bf
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d6e2b07c401..2d905a99d68 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2873,6 +2873,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvkn),
>       .implied_multi_exts = {
> @@ -3070,6 +3079,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVFBFWMA_IMPLIED,
>       &ZVFH_IMPLIED,
>       &ZVFHMIN_IMPLIED,
> +    &ZVFWDOTA16BF_IMPLIED,
>       &ZVKN_IMPLIED,
>       &ZVKNC_IMPLIED,
>       &ZVKNG_IMPLIED,

Re: [RFC PATCH 12/38] target/riscv: Add implied rules for Zvfwdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:27 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvfwdota16bf
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d6e2b07c401..2d905a99d68 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2873,6 +2873,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvkn),
>      .implied_multi_exts = {
> @@ -3070,6 +3079,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVFBFWMA_IMPLIED,
>      &ZVFH_IMPLIED,
>      &ZVFHMIN_IMPLIED,
> +    &ZVFWDOTA16BF_IMPLIED,
>      &ZVKN_IMPLIED,
>      &ZVKNC_IMPLIED,
>      &ZVKNG_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 13/38] target/riscv: rvv: Implement Zvfwdota16bf instruction

[Max Chou]

Implement the vfwdota.vv instruction from the Zvfwdota16bf extension.
This instruction computes a dot product between two BF16 vectors,
accumulating into an FP32 scalar in vd[0].

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  2 +
 target/riscv/insn32.decode                  |  3 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++++
 target/riscv/tcg/vector_helper.c            | 48 +++++++++++++++++++++
 4 files changed, 95 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 23d3e9b3c43..918ff21b3e2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1393,6 +1393,8 @@ DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 
+/* Zvfwdota16bf - BF16 Dot Product */
+DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
 DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b8a5d0567b1..d800ad99451 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1101,3 +1101,6 @@ vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
 # *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
 vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
 vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
+
+# *** Zvfwdota16bf BF16 Dot-Product Extension ***
+vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index fcff472a2ea..c50f863ea0b 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4200,3 +4200,45 @@ GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
 
 GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
 GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
+
+static bool vext_vfwdota_check(DisasContext *s, arg_rmrr * a)
+{
+    return s->mstatus_fs != EXT_STATUS_DISABLED &&
+           vext_zvdota_base_check(s, a) &&
+           (s->cfg_ptr->ext_zvfwdota16bf && s->sew == MO_16 && s->altfmt == 1);
+}
+
+static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
+{
+    if (vext_vfwdota_check(s, a)) {
+        TCGv_ptr dest, src1, src2, mask;
+        TCGv_i32 desc;
+        uint32_t data = 0;
+
+        gen_set_rm(s, RISCV_FRM_DYN);
+
+        data = FIELD_DP32(data, VDATA, VM, a->vm);
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+
+        dest = tcg_temp_new_ptr();
+        mask = tcg_temp_new_ptr();
+        src1 = tcg_temp_new_ptr();
+        src2 = tcg_temp_new_ptr();
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,
+                                          data));
+
+        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
+        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
+
+        gen_helper_vfwdota_vv(dest, mask, src1, src2, tcg_env, desc);
+
+        finalize_rvv_inst(s);
+
+        return true;
+    }
+    return false;
+}
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 41b526d25ef..5947427b6b4 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6025,3 +6025,51 @@ GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
 GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
 GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
 GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)
+
+/*
+ * Zvfwdota16bf: BF16 Dot Product with Accumulation
+ */
+void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
+                        CPURISCVState *env, uint32_t desc)
+{
+    uint32_t vlmax = vext_max_elems(desc, 1);
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    uint32_t vta = vext_vta(desc);
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);
+    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;
+    uint32_t i;
+    bfloat16 *a_vec, *b_vec;
+    uint32_t dot_result, acc;
+
+    VSTART_CHECK_EARLY_EXIT(env, vl);
+
+    a_vec = g_new0(bfloat16, vlmax);
+    b_vec = g_new0(bfloat16, vlmax);
+
+    for (i = 0; i < vl; i++) {
+        if (!vm && !vext_elem_mask(v0, i)) {
+            continue;
+        }
+        a_vec[i] = *((uint16_t *)vs1 + H2(i));
+        b_vec[i] = *((uint16_t *)vs2 + H2(i));
+    }
+
+    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
+    dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
+                                             &env->fp_status);
+
+    acc = *((uint32_t *)vd + H4(0));
+    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,
+                                                    &env->fp_status);
+    riscv_cpu_check_fflags(env, pre_fflag);
+
+    g_free(a_vec);
+    g_free(b_vec);
+
+    env->vstart = 0;
+
+    if (vta_all_1s) {
+        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
+    }
+}
-- 
2.56.0

Re: [RFC PATCH 13/38] target/riscv: rvv: Implement Zvfwdota16bf instruction

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Implement the vfwdota.vv instruction from the Zvfwdota16bf extension.
> This instruction computes a dot product between two BF16 vectors,
> accumulating into an FP32 scalar in vd[0].
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/helper.h                       |  2 +
>   target/riscv/insn32.decode                  |  3 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++++
>   target/riscv/tcg/vector_helper.c            | 48 +++++++++++++++++++++
>   4 files changed, 95 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 23d3e9b3c43..918ff21b3e2 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1393,6 +1393,8 @@ DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>   
> +/* Zvfwdota16bf - BF16 Dot Product */
> +DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index b8a5d0567b1..d800ad99451 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1101,3 +1101,6 @@ vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
>   # *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
>   vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
>   vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> +
> +# *** Zvfwdota16bf BF16 Dot-Product Extension ***
> +vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index fcff472a2ea..c50f863ea0b 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4200,3 +4200,45 @@ GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
>   
>   GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
>   GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
> +
> +static bool vext_vfwdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvfwdota16bf && s->sew == MO_16 && s->altfmt == 1);
> +}
> +
> +static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
> +{
> +    if (vext_vfwdota_check(s, a)) {
> +        TCGv_ptr dest, src1, src2, mask;
> +        TCGv_i32 desc;
> +        uint32_t data = 0;
> +
> +        gen_set_rm(s, RISCV_FRM_DYN);
> +
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> +
> +        dest = tcg_temp_new_ptr();
> +        mask = tcg_temp_new_ptr();
> +        src1 = tcg_temp_new_ptr();
> +        src2 = tcg_temp_new_ptr();
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,
> +                                          data));
> +
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> +
> +        gen_helper_vfwdota_vv(dest, mask, src1, src2, tcg_env, desc);
> +
> +        finalize_rvv_inst(s);
> +
> +        return true;
> +    }
> +    return false;
> +}
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 41b526d25ef..5947427b6b4 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6025,3 +6025,51 @@ GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
>   GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
>   GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
>   GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)
> +
> +/*
> + * Zvfwdota16bf: BF16 Dot Product with Accumulation
> + */
> +void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
> +                        CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vlmax = vext_max_elems(desc, 1);
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;
> +    uint32_t i;
> +    bfloat16 *a_vec, *b_vec;

Although we don't have any existing instances of it in the code, it is perfectly
fine to do:

+    g_autofree bfloat16 *a_vec = NULL;
+    g_autofree bfloat16 *b_vec = NULL;


Sparing us from calling g_free() on both arrays later.


LGTM otherwise.  Thanks,
Daniel


> +    uint32_t dot_result, acc;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(bfloat16, vlmax);
> +    b_vec = g_new0(bfloat16, vlmax);
> +
> +    for (i = 0; i < vl; i++) {
> +        if (!vm && !vext_elem_mask(v0, i)) {
> +            continue;
> +        }
> +        a_vec[i] = *((uint16_t *)vs1 + H2(i));
> +        b_vec[i] = *((uint16_t *)vs2 + H2(i));
> +    }
> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
> +                                             &env->fp_status);
> +
> +    acc = *((uint32_t *)vd + H4(0));
> +    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,
> +                                                    &env->fp_status);
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (vta_all_1s) {
> +        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
> +    }
> +}

Re: [RFC PATCH 13/38] target/riscv: rvv: Implement Zvfwdota16bf instruction

[Max Chou]

On 2026-11-09 17:15, Daniel Henrique Barboza wrote:
> On 11/4/2026 4:41 PM, Max Chou wrote:
> > ---
> > +    bfloat16 *a_vec, *b_vec;
> 
> Although we don't have any existing instances of it in the code, it is perfectly
> fine to do:
> 
> +    g_autofree bfloat16 *a_vec = NULL;
> +    g_autofree bfloat16 *b_vec = NULL;
> 
> 
> Sparing us from calling g_free() on both arrays later.
> 
> 
> LGTM otherwise.  Thanks,
> Daniel
> 

Hi Daniel,

Thanks for the suggestion. Will provide v2 for this.

rnax

Re: [RFC PATCH 13/38] target/riscv: rvv: Implement Zvfwdota16bf instruction

[Chao Liu]

On Thu,  5 Nov 2026 03:41:28 +0800 Max Chou <max.chou@sifive.com> wrote:

> Implement the vfwdota.vv instruction from the Zvfwdota16bf extension.
> This instruction computes a dot product between two BF16 vectors,
> accumulating into an FP32 scalar in vd[0].
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  target/riscv/helper.h                       |  2 +
>  target/riscv/insn32.decode                  |  3 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++++
>  target/riscv/tcg/vector_helper.c            | 48 +++++++++++++++++++++
>  4 files changed, 95 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 23d3e9b3c43..918ff21b3e2 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1393,6 +1393,8 @@ DEF_HELPER_6(vqwdotas_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vqwdotau_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>  
> +/* Zvfwdota16bf - BF16 Dot Product */
> +DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index b8a5d0567b1..d800ad99451 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1101,3 +1101,6 @@ vwabdau_vx    111110 . ..... ..... 100 ..... 1010111 @r_vm
>  # *** Zvqwdota8i/Zvqwdota16i Integer Dot-Product Extension ***
>  vqwdotau_vv  100110 . ..... ..... 000 ..... 1110111 @r_vm
>  vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
> +
> +# *** Zvfwdota16bf BF16 Dot-Product Extension ***
> +vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index fcff472a2ea..c50f863ea0b 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4200,3 +4200,45 @@ GEN_ABD_OPIVX_WIDEN_TRANS(vwabdau_vx, vwabd_vx_check)
>  
>  GEN_ZVDOTA_INT_TRANS(vqwdotau_vv, vext_vqwdota_check)
>  GEN_ZVDOTA_INT_TRANS(vqwdotas_vv, vext_vqwdota_check)
> +
> +static bool vext_vfwdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvfwdota16bf && s->sew == MO_16 && s->altfmt == 1);

altfmt is bool type, Just `&& s->altfmt` is enough.

Otherwise, LGTM.


Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> +}
> +
> +static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
> +{
> +    if (vext_vfwdota_check(s, a)) {
> +        TCGv_ptr dest, src1, src2, mask;
> +        TCGv_i32 desc;
> +        uint32_t data = 0;
> +
> +        gen_set_rm(s, RISCV_FRM_DYN);
> +
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> +
> +        dest = tcg_temp_new_ptr();
> +        mask = tcg_temp_new_ptr();
> +        src1 = tcg_temp_new_ptr();
> +        src2 = tcg_temp_new_ptr();
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,
> +                                          data));
> +
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> +
> +        gen_helper_vfwdota_vv(dest, mask, src1, src2, tcg_env, desc);
> +
> +        finalize_rvv_inst(s);
> +
> +        return true;
> +    }
> +    return false;
> +}
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 41b526d25ef..5947427b6b4 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6025,3 +6025,51 @@ GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_b, 32, 8, uint8_t, H4, H1)
>  GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_b, 32, 8, int8_t, H4, H1)
>  GEN_VEXT_ZVDOTA_INT(vqwdotau_vv_h, 64, 16, uint16_t, H8, H2)
>  GEN_VEXT_ZVDOTA_INT(vqwdotas_vv_h, 64, 16, int16_t, H8, H2)
> +
> +/*
> + * Zvfwdota16bf: BF16 Dot Product with Accumulation
> + */
> +void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
> +                        CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vlmax = vext_max_elems(desc, 1);
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;
> +    uint32_t i;
> +    bfloat16 *a_vec, *b_vec;
> +    uint32_t dot_result, acc;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(bfloat16, vlmax);
> +    b_vec = g_new0(bfloat16, vlmax);
> +
> +    for (i = 0; i < vl; i++) {
> +        if (!vm && !vext_elem_mask(v0, i)) {
> +            continue;
> +        }
> +        a_vec[i] = *((uint16_t *)vs1 + H2(i));
> +        b_vec[i] = *((uint16_t *)vs2 + H2(i));
> +    }
> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
> +                                             &env->fp_status);
> +
> +    acc = *((uint32_t *)vd + H4(0));
> +    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,
> +                                                    &env->fp_status);
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (vta_all_1s) {
> +        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
> +    }
> +}
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 14/38] disas/riscv: Support Zvfwdota16bf extension

[Max Chou]

Add disassembler support for the vfwdota.vv instruction from the
Zvfwdota16bf extension.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 1 +
 disas/riscv.c        | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index ec767ccbf8b..aeb9423f130 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -614,6 +614,7 @@ OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwdota_vv, "vfwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
 OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
 OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2acded0c915..62feb4c653e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2640,6 +2640,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 39: return &op_vqwdotas_vv;
                 }
             }
+            if (((inst >> 12) & 0b111) == 1 &&
+                ((inst >> 26) & 0b111111) == 36) {
+                return &op_vfwdota_vv;
+            }
             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
                 switch ((inst >> 26) & 0b111111) {
                 case 32: return &op_vsm3me_vv;
-- 
2.56.0

Re: [RFC PATCH 14/38] disas/riscv: Support Zvfwdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add disassembler support for the vfwdota.vv instruction from the
> Zvfwdota16bf extension.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 1 +
>   disas/riscv.c        | 4 ++++
>   2 files changed, 5 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index ec767ccbf8b..aeb9423f130 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -614,6 +614,7 @@ OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwdota_vv, "vfwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>   OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>   OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 2acded0c915..62feb4c653e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2640,6 +2640,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   case 39: return &op_vqwdotas_vv;
>                   }
>               }
> +            if (((inst >> 12) & 0b111) == 1 &&
> +                ((inst >> 26) & 0b111111) == 36) {
> +                return &op_vfwdota_vv;
> +            }
>               if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                   switch ((inst >> 26) & 0b111111) {
>                   case 32: return &op_vsm3me_vv;

Re: [RFC PATCH 14/38] disas/riscv: Support Zvfwdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:29 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add disassembler support for the vfwdota.vv instruction from the
> Zvfwdota16bf extension.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 1 +
>  disas/riscv.c        | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index ec767ccbf8b..aeb9423f130 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -614,6 +614,7 @@ OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwdota_vv, "vfwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>  OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>  OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 2acded0c915..62feb4c653e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2640,6 +2640,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  case 39: return &op_vqwdotas_vv;
>                  }
>              }
> +            if (((inst >> 12) & 0b111) == 1 &&
> +                ((inst >> 26) & 0b111111) == 36) {
> +                return &op_vfwdota_vv;
> +            }
>              if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                  switch ((inst >> 26) & 0b111111) {
>                  case 32: return &op_vsm3me_vv;
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 15/38] target/riscv: Add cfg property for Zvfqwdota8f extension

[Max Chou]

Add CPU configuration property of Zvfqwdota8f extension which depends on
the Zve32f extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2d905a99d68..4f2e7a8faa9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
+                                    ext_zvfqwdota8f),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
                                     ext_zvfwdota16bf),
     ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 30c404863c8..b18abdd8b9b 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_zvfqwdota8f)
 BOOL_FIELD(ext_zvfwdota16bf)
 BOOL_FIELD(ext_zvqwdota16i)
 BOOL_FIELD(ext_zvqwdota8i)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 91e009072e6..72ce0b4fbd0 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -706,6 +706,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfqwdota8f && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfqwdota8f extension depends on Zve32f extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 5947427b6b4..a4c52ed296a 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     target_ulong reserved = 0;
 
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
+        riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
         riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
         riscv_cpu_cfg(env)->ext_zvqwdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwdota8i) {
@@ -92,6 +93,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     switch (vsew) {
     case MO_8:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvfqwdota8f ||
                         cpu->cfg.ext_zvqwdota8i);
         break;
     case MO_16:
-- 
2.56.0

Re: [RFC PATCH 15/38] target/riscv: Add cfg property for Zvfqwdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvfqwdota8f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2d905a99d68..4f2e7a8faa9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>       ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>       ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfqwdota8f),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
>                                       ext_zvfwdota16bf),
>       ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 30c404863c8..b18abdd8b9b 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfqwdota8f)
>   BOOL_FIELD(ext_zvfwdota16bf)
>   BOOL_FIELD(ext_zvqwdota16i)
>   BOOL_FIELD(ext_zvqwdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 91e009072e6..72ce0b4fbd0 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -706,6 +706,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfqwdota8f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfqwdota8f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5947427b6b4..a4c52ed296a 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       target_ulong reserved = 0;
>   
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>           riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>           riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota8i) {
> @@ -92,6 +93,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       switch (vsew) {
>       case MO_8:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfqwdota8f ||
>                           cpu->cfg.ext_zvqwdota8i);
>           break;
>       case MO_16:

Re: [RFC PATCH 15/38] target/riscv: Add cfg property for Zvfqwdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:30 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvfqwdota8f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2d905a99d68..4f2e7a8faa9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>      ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfqwdota8f),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
>                                      ext_zvfwdota16bf),
>      ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 30c404863c8..b18abdd8b9b 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfqwdota8f)
>  BOOL_FIELD(ext_zvfwdota16bf)
>  BOOL_FIELD(ext_zvqwdota16i)
>  BOOL_FIELD(ext_zvqwdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 91e009072e6..72ce0b4fbd0 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -706,6 +706,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvfqwdota8f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfqwdota8f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5947427b6b4..a4c52ed296a 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      target_ulong reserved = 0;
>  
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>          riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>          riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota8i) {
> @@ -92,6 +93,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      switch (vsew) {
>      case MO_8:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfqwdota8f ||
>                          cpu->cfg.ext_zvqwdota8i);
>          break;
>      case MO_16:
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 16/38] target/riscv: Add implied rules for Zvfqwdota8f extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvfqwdota8f
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4f2e7a8faa9..6c09685bd4b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2875,6 +2875,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvfqwdota8f),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32f),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
     .implied_multi_exts = {
@@ -3081,6 +3090,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVFBFWMA_IMPLIED,
     &ZVFH_IMPLIED,
     &ZVFHMIN_IMPLIED,
+    &ZVFQWDOTA8F_IMPLIED,
     &ZVFWDOTA16BF_IMPLIED,
     &ZVKN_IMPLIED,
     &ZVKNC_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 16/38] target/riscv: Add implied rules for Zvfqwdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfqwdota8f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4f2e7a8faa9..6c09685bd4b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2875,6 +2875,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfqwdota8f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
>       .implied_multi_exts = {
> @@ -3081,6 +3090,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVFBFWMA_IMPLIED,
>       &ZVFH_IMPLIED,
>       &ZVFHMIN_IMPLIED,
> +    &ZVFQWDOTA8F_IMPLIED,
>       &ZVFWDOTA16BF_IMPLIED,
>       &ZVKN_IMPLIED,
>       &ZVKNC_IMPLIED,

Re: [RFC PATCH 16/38] target/riscv: Add implied rules for Zvfqwdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:31 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvfqwdota8f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4f2e7a8faa9..6c09685bd4b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2875,6 +2875,15 @@ static RISCVCPUImpliedExtsRule ZVQWDOTA8I_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfqwdota8f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
>      .implied_multi_exts = {
> @@ -3081,6 +3090,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVFBFWMA_IMPLIED,
>      &ZVFH_IMPLIED,
>      &ZVFHMIN_IMPLIED,
> +    &ZVFQWDOTA8F_IMPLIED,
>      &ZVFWDOTA16BF_IMPLIED,
>      &ZVKN_IMPLIED,
>      &ZVKNC_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 17/38] target/riscv: rvv: Implement Zvfqwdota8f instructions

[Max Chou]

Implements the Zvfqwdota8f OCP FP8 dot-product instructions:
- vfqwdota.vv: vs2 is E4M3, vs1 format selected by altfmt (0=E4M3, 1=E5M2)
- vfqwdota.alt.vv: vs2 is E5M2, vs1 format selected by altfmt (0=E4M3, 1=E5M2)

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  5 ++
 target/riscv/insn32.decode                  |  4 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 47 ++++++++++++++++
 target/riscv/tcg/vector_helper.c            | 62 +++++++++++++++++++++
 4 files changed, 118 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 918ff21b3e2..48c64f45748 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1395,6 +1395,11 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 
 /* Zvfwdota16bf - BF16 Dot Product */
 DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
+
+/* Zvfqwdota8f - OCP FP8 Dot Product */
+DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
+
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
 DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d800ad99451..def5785f8e2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1104,3 +1104,7 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
 
 # *** Zvfwdota16bf BF16 Dot-Product Extension ***
 vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
+
+# *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
+vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
+vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index c50f863ea0b..6eb22494838 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4242,3 +4242,50 @@ static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
     }
     return false;
 }
+
+/* Zvfqwdota8f OCP FP8 Dot-Product Extension */
+static bool vext_vfqwdota_check(DisasContext *s, arg_rmrr *a)
+{
+    return s->mstatus_fs != EXT_STATUS_DISABLED &&
+           vext_zvdota_base_check(s, a) &&
+           (s->cfg_ptr->ext_zvfqwdota8f && s->sew == MO_8);
+}
+
+#define GEN_ZVDOTA_FP8_TRANS(NAME, CHECK)                               \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
+{                                                                       \
+    if (CHECK(s, a)) {                                                  \
+        TCGv_ptr dest, src1, src2, mask;                                \
+        TCGv_i32 desc;                                                  \
+        uint32_t data = 0;                                              \
+                                                                        \
+        gen_set_rm(s, RISCV_FRM_DYN);                                   \
+                                                                        \
+        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
+                                                                        \
+        dest = tcg_temp_new_ptr();                                      \
+        mask = tcg_temp_new_ptr();                                      \
+        src1 = tcg_temp_new_ptr();                                      \
+        src2 = tcg_temp_new_ptr();                                      \
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
+                                          s->cfg_ptr->vlenb, data));    \
+                                                                        \
+        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
+        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
+                                                                        \
+        gen_helper_##NAME(dest, mask, src1, src2, tcg_env, desc);       \
+                                                                        \
+        finalize_rvv_inst(s);                                           \
+                                                                        \
+        return true;                                                    \
+    }                                                                   \
+    return false;                                                       \
+}
+
+GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
+GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index a4c52ed296a..5cb44326200 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6075,3 +6075,65 @@ void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
         vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
     }
 }
+
+/*
+ * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
+ */
+#define GEN_VEXT_ZVDOTA_FP8(NAME, TYPE_VS2)                              \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
+                  CPURISCVState *env, uint32_t desc)                     \
+{                                                                        \
+    uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(uint8_t)));        \
+    uint32_t vm = vext_vm(desc);                                         \
+    uint32_t vl = env->vl;                                               \
+    uint32_t vta = vext_vta(desc);                                       \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
+    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;               \
+    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
+    uint32_t i;                                                          \
+    uint8_t *a_vec, *b_vec;                                              \
+    uint32_t dot_result, acc;                                            \
+                                                                         \
+    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
+                                                                         \
+    a_vec = g_new0(uint8_t, vlmax);                                      \
+    b_vec = g_new0(uint8_t, vlmax);                                      \
+                                                                         \
+    for (i = 0; i < vl; i++) {                                           \
+        if (!vm && !vext_elem_mask(v0, i)) {                             \
+            continue;                                                    \
+        }                                                                \
+        a_vec[i] = *((uint8_t *)vs2 + H1(i));                            \
+        b_vec[i] = *((uint8_t *)vs1 + H1(i));                            \
+    }                                                                    \
+                                                                         \
+    FloatExceptionFlags pre_fflag =                                      \
+        get_float_exception_flags(&env->fp_status);                      \
+    FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);        \
+    set_snan_rule(float_snan_never, &env->fp_status);                    \
+    if (altfmt == 0) {                                                   \
+        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(          \
+            a_vec, b_vec, vlmax, &env->fp_status);                       \
+    } else {                                                             \
+        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(          \
+            a_vec, b_vec, vlmax, &env->fp_status);                       \
+    }                                                                    \
+    set_snan_rule(pre_snan_rule, &env->fp_status);                       \
+                                                                         \
+    acc = *((uint32_t *)vd + H4(0));                                     \
+    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,     \
+                                                    &env->fp_status);    \
+    riscv_cpu_check_fflags(env, pre_fflag);                              \
+                                                                         \
+    g_free(a_vec);                                                       \
+    g_free(b_vec);                                                       \
+                                                                         \
+    env->vstart = 0;                                                     \
+                                                                         \
+    if (vta_all_1s) {                                                    \
+        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);              \
+    }                                                                    \
+}
+
+GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
+GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)
-- 
2.56.0

Re: [RFC PATCH 17/38] target/riscv: rvv: Implement Zvfqwdota8f instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Implements the Zvfqwdota8f OCP FP8 dot-product instructions:
> - vfqwdota.vv: vs2 is E4M3, vs1 format selected by altfmt (0=E4M3, 1=E5M2)
> - vfqwdota.alt.vv: vs2 is E5M2, vs1 format selected by altfmt (0=E4M3, 1=E5M2)
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/helper.h                       |  5 ++
>   target/riscv/insn32.decode                  |  4 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 47 ++++++++++++++++
>   target/riscv/tcg/vector_helper.c            | 62 +++++++++++++++++++++
>   4 files changed, 118 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 918ff21b3e2..48c64f45748 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1395,6 +1395,11 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>   
>   /* Zvfwdota16bf - BF16 Dot Product */
>   DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +
> +/* Zvfqwdota8f - OCP FP8 Dot Product */
> +DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index d800ad99451..def5785f8e2 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1104,3 +1104,7 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
>   
>   # *** Zvfwdota16bf BF16 Dot-Product Extension ***
>   vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
> +
> +# *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
> +vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
> +vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index c50f863ea0b..6eb22494838 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4242,3 +4242,50 @@ static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
>       }
>       return false;
>   }
> +
> +/* Zvfqwdota8f OCP FP8 Dot-Product Extension */
> +static bool vext_vfqwdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvfqwdota8f && s->sew == MO_8);
> +}
> +
> +#define GEN_ZVDOTA_FP8_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
> +{                                                                       \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 desc;                                                  \
> +        uint32_t data = 0;                                              \
> +                                                                        \
> +        gen_set_rm(s, RISCV_FRM_DYN);                                   \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        gen_helper_##NAME(dest, mask, src1, src2, tcg_env, desc);       \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
> +GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
> +GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index a4c52ed296a..5cb44326200 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6075,3 +6075,65 @@ void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
>           vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
>       }
>   }
> +
> +/*
> + * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVDOTA_FP8(NAME, TYPE_VS2)                              \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
> +                  CPURISCVState *env, uint32_t desc)                     \
> +{                                                                        \
> +    uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(uint8_t)));        \
> +    uint32_t vm = vext_vm(desc);                                         \
> +    uint32_t vl = env->vl;                                               \
> +    uint32_t vta = vext_vta(desc);                                       \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
> +    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;               \
> +    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
> +    uint32_t i;                                                          \
> +    uint8_t *a_vec, *b_vec;                                              \
> +    uint32_t dot_result, acc;                                            \
> +                                                                         \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
> +                                                                         \
> +    a_vec = g_new0(uint8_t, vlmax);                                      \
> +    b_vec = g_new0(uint8_t, vlmax);                                      \

Same comment I made in an earlier patch about using g_autofree on these arrays.

With this changed:


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>


> +                                                                         \
> +    for (i = 0; i < vl; i++) {                                           \
> +        if (!vm && !vext_elem_mask(v0, i)) {                             \
> +            continue;                                                    \
> +        }                                                                \
> +        a_vec[i] = *((uint8_t *)vs2 + H1(i));                            \
> +        b_vec[i] = *((uint8_t *)vs1 + H1(i));                            \
> +    }                                                                    \
> +                                                                         \
> +    FloatExceptionFlags pre_fflag =                                      \
> +        get_float_exception_flags(&env->fp_status);                      \
> +    FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);        \
> +    set_snan_rule(float_snan_never, &env->fp_status);                    \
> +    if (altfmt == 0) {                                                   \
> +        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(          \
> +            a_vec, b_vec, vlmax, &env->fp_status);                       \
> +    } else {                                                             \
> +        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(          \
> +            a_vec, b_vec, vlmax, &env->fp_status);                       \
> +    }                                                                    \
> +    set_snan_rule(pre_snan_rule, &env->fp_status);                       \
> +                                                                         \
> +    acc = *((uint32_t *)vd + H4(0));                                     \
> +    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,     \
> +                                                    &env->fp_status);    \
> +    riscv_cpu_check_fflags(env, pre_fflag);                              \
> +                                                                         \
> +    g_free(a_vec);                                                       \
> +    g_free(b_vec);                                                       \
> +                                                                         \
> +    env->vstart = 0;                                                     \
> +                                                                         \
> +    if (vta_all_1s) {                                                    \
> +        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);              \
> +    }                                                                    \
> +}
> +
> +GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
> +GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)

Re: [RFC PATCH 17/38] target/riscv: rvv: Implement Zvfqwdota8f instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:32 +0800 Max Chou <max.chou@sifive.com> wrote:

> Implements the Zvfqwdota8f OCP FP8 dot-product instructions:
> - vfqwdota.vv: vs2 is E4M3, vs1 format selected by altfmt (0=E4M3, 1=E5M2)
> - vfqwdota.alt.vv: vs2 is E5M2, vs1 format selected by altfmt (0=E4M3, 1=E5M2)
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  target/riscv/helper.h                       |  5 ++
>  target/riscv/insn32.decode                  |  4 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 47 ++++++++++++++++
>  target/riscv/tcg/vector_helper.c            | 62 +++++++++++++++++++++
>  4 files changed, 118 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 918ff21b3e2..48c64f45748 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1395,6 +1395,11 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>  
>  /* Zvfwdota16bf - BF16 Dot Product */
>  DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +
> +/* Zvfqwdota8f - OCP FP8 Dot Product */
> +DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index d800ad99451..def5785f8e2 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1104,3 +1104,7 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
>  
>  # *** Zvfwdota16bf BF16 Dot-Product Extension ***
>  vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
> +
> +# *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
> +vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
> +vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index c50f863ea0b..6eb22494838 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4242,3 +4242,50 @@ static bool trans_vfwdota_vv(DisasContext *s, arg_rmrr * a)
>      }
>      return false;
>  }
> +
> +/* Zvfqwdota8f OCP FP8 Dot-Product Extension */
> +static bool vext_vfqwdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvdota_base_check(s, a) &&
> +           (s->cfg_ptr->ext_zvfqwdota8f && s->sew == MO_8);
> +}
> +
> +#define GEN_ZVDOTA_FP8_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
> +{                                                                       \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 desc;                                                  \
> +        uint32_t data = 0;                                              \
> +                                                                        \
> +        gen_set_rm(s, RISCV_FRM_DYN);                                   \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);                  \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));           \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        gen_helper_##NAME(dest, mask, src1, src2, tcg_env, desc);       \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
> +GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
> +GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index a4c52ed296a..5cb44326200 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6075,3 +6075,65 @@ void HELPER(vfwdota_vv)(void *vd, void *v0, void *vs1, void *vs2,
>          vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);
>      }
>  }
> +
> +/*
> + * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVDOTA_FP8(NAME, TYPE_VS2)                              \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
> +                  CPURISCVState *env, uint32_t desc)                     \
> +{                                                                        \
> +    uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(uint8_t)));        \
> +    uint32_t vm = vext_vm(desc);                                         \
> +    uint32_t vl = env->vl;                                               \
> +    uint32_t vta = vext_vta(desc);                                       \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
> +    uint32_t total_elems = riscv_cpu_cfg(env)->vlenb >> 2;               \
> +    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
> +    uint32_t i;                                                          \
> +    uint8_t *a_vec, *b_vec;                                              \
> +    uint32_t dot_result, acc;                                            \
> +                                                                         \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
> +                                                                         \
> +    a_vec = g_new0(uint8_t, vlmax);                                      \
> +    b_vec = g_new0(uint8_t, vlmax);                                      \
Please use g_autofree here and initialize both pointers to NULL, as Daniel
suggested in the earlier patch.

LGTM, Otherwise.


Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> +                                                                         \
> +    for (i = 0; i < vl; i++) {                                           \
> +        if (!vm && !vext_elem_mask(v0, i)) {                             \
> +            continue;                                                    \
> +        }                                                                \
> +        a_vec[i] = *((uint8_t *)vs2 + H1(i));                            \
> +        b_vec[i] = *((uint8_t *)vs1 + H1(i));                            \
> +    }                                                                    \
> +                                                                         \
> +    FloatExceptionFlags pre_fflag =                                      \
> +        get_float_exception_flags(&env->fp_status);                      \
> +    FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);        \
> +    set_snan_rule(float_snan_never, &env->fp_status);                    \
> +    if (altfmt == 0) {                                                   \
> +        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(          \
> +            a_vec, b_vec, vlmax, &env->fp_status);                       \
> +    } else {                                                             \
> +        dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(          \
> +            a_vec, b_vec, vlmax, &env->fp_status);                       \
> +    }                                                                    \
> +    set_snan_rule(pre_snan_rule, &env->fp_status);                       \
> +                                                                         \
> +    acc = *((uint32_t *)vd + H4(0));                                     \
> +    *((uint32_t *)vd + H4(0)) = rvbna_final_f32_add(dot_result, acc,     \
> +                                                    &env->fp_status);    \
> +    riscv_cpu_check_fflags(env, pre_fflag);                              \
> +                                                                         \
> +    g_free(a_vec);                                                       \
> +    g_free(b_vec);                                                       \
> +                                                                         \
> +    env->vstart = 0;                                                     \
> +                                                                         \
> +    if (vta_all_1s) {                                                    \
> +        vext_set_elems_1s(vd, vta, 1 * 4, total_elems * 4);              \
> +    }                                                                    \
> +}
> +
> +GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
> +GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 18/38] disas/riscv: Support Zvfqwdota8f extension

[Max Chou]

Adds support to disassemble Zvfqwdota8f instructions.
- vfqwdota.vv
- vfqwdota.alt.vv

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 2 ++
 disas/riscv.c        | 9 ++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index aeb9423f130..5ba29f52976 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -583,6 +583,8 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
 OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
 OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
 OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
 OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
 OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index 62feb4c653e..0f609cc06b4 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2640,9 +2640,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 39: return &op_vqwdotas_vv;
                 }
             }
-            if (((inst >> 12) & 0b111) == 1 &&
-                ((inst >> 26) & 0b111111) == 36) {
-                return &op_vfwdota_vv;
+            if (((inst >> 12) & 0b111) == 1) {
+                switch ((inst >> 26) & 0b111111) {
+                case 36: return &op_vfwdota_vv;
+                case 38: return &op_vfqwdota_vv;
+                case 39: return &op_vfqwdota_alt_vv;
+                }
             }
             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
                 switch ((inst >> 26) & 0b111111) {
-- 
2.56.0

Re: [RFC PATCH 18/38] disas/riscv: Support Zvfqwdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support to disassemble Zvfqwdota8f instructions.
> - vfqwdota.vv
> - vfqwdota.alt.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 2 ++
>   disas/riscv.c        | 9 ++++++---
>   2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index aeb9423f130..5ba29f52976 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -583,6 +583,8 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>   OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>   OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>   OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>   OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
>   OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 62feb4c653e..0f609cc06b4 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2640,9 +2640,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   case 39: return &op_vqwdotas_vv;
>                   }
>               }
> -            if (((inst >> 12) & 0b111) == 1 &&
> -                ((inst >> 26) & 0b111111) == 36) {
> -                return &op_vfwdota_vv;
> +            if (((inst >> 12) & 0b111) == 1) {
> +                switch ((inst >> 26) & 0b111111) {
> +                case 36: return &op_vfwdota_vv;
> +                case 38: return &op_vfqwdota_vv;
> +                case 39: return &op_vfqwdota_alt_vv;
> +                }
>               }
>               if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                   switch ((inst >> 26) & 0b111111) {

Re: [RFC PATCH 18/38] disas/riscv: Support Zvfqwdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:33 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support to disassemble Zvfqwdota8f instructions.
> - vfqwdota.vv
> - vfqwdota.alt.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 2 ++
>  disas/riscv.c        | 9 ++++++---
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index aeb9423f130..5ba29f52976 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -583,6 +583,8 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>  OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>  OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>  OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>  OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
>  OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 62feb4c653e..0f609cc06b4 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2640,9 +2640,12 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  case 39: return &op_vqwdotas_vv;
>                  }
>              }
> -            if (((inst >> 12) & 0b111) == 1 &&
> -                ((inst >> 26) & 0b111111) == 36) {
> -                return &op_vfwdota_vv;
> +            if (((inst >> 12) & 0b111) == 1) {
> +                switch ((inst >> 26) & 0b111111) {
> +                case 36: return &op_vfwdota_vv;
> +                case 38: return &op_vfqwdota_vv;
> +                case 39: return &op_vfqwdota_alt_vv;
> +                }
>              }
>              if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
>                  switch ((inst >> 26) & 0b111111) {
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 19/38] target/riscv: Add cfg property for Zvqwbdota8i extension

[Max Chou]

Add CPU configuration for the Zvqwbdota8i extension which depends on the
Zve32x extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6c09685bd4b..9271f79d1b6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
+                                    ext_zvqwbdota8i),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
                                     ext_zvqwdota16i),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index b18abdd8b9b..3d822432d48 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
 BOOL_FIELD(ext_zvfqwdota8f)
 BOOL_FIELD(ext_zvfwdota16bf)
+BOOL_FIELD(ext_zvqwbdota8i)
 BOOL_FIELD(ext_zvqwdota16i)
 BOOL_FIELD(ext_zvqwdota8i)
 BOOL_FIELD(ext_sdext)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 72ce0b4fbd0..782e38b608e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -711,6 +711,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvqwbdota8i && !cpu->cfg.ext_zve32x) {
+        error_setg(errp, "Zvqwbdota8i extension depends on Zve32x extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 5cb44326200..b1ca584f9ef 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
         riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
         riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
+        riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
         riscv_cpu_cfg(env)->ext_zvqwdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwdota8i) {
         reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
@@ -94,6 +95,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     case MO_8:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
                         cpu->cfg.ext_zvfqwdota8f ||
+                        cpu->cfg.ext_zvqwbdota8i ||
                         cpu->cfg.ext_zvqwdota8i);
         break;
     case MO_16:
-- 
2.56.0

Re: [RFC PATCH 19/38] target/riscv: Add cfg property for Zvqwbdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration for the Zvqwbdota8i extension which depends on the
> Zve32x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>


>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6c09685bd4b..9271f79d1b6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>       ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>       ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwbdota8i),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
>                                       ext_zvqwdota16i),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index b18abdd8b9b..3d822432d48 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
>   BOOL_FIELD(ext_zvfqwdota8f)
>   BOOL_FIELD(ext_zvfwdota16bf)
> +BOOL_FIELD(ext_zvqwbdota8i)
>   BOOL_FIELD(ext_zvqwdota16i)
>   BOOL_FIELD(ext_zvqwdota8i)
>   BOOL_FIELD(ext_sdext)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 72ce0b4fbd0..782e38b608e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -711,6 +711,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvqwbdota8i && !cpu->cfg.ext_zve32x) {
> +        error_setg(errp, "Zvqwbdota8i extension depends on Zve32x extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5cb44326200..b1ca584f9ef 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>           riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>           riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> +        riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>           reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> @@ -94,6 +95,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       case MO_8:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
>                           cpu->cfg.ext_zvfqwdota8f ||
> +                        cpu->cfg.ext_zvqwbdota8i ||
>                           cpu->cfg.ext_zvqwdota8i);
>           break;
>       case MO_16:

Re: [RFC PATCH 19/38] target/riscv: Add cfg property for Zvqwbdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:34 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration for the Zvqwbdota8i extension which depends on the
> Zve32x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6c09685bd4b..9271f79d1b6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>      ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwbdota8i),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
>                                      ext_zvqwdota16i),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota8i, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index b18abdd8b9b..3d822432d48 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
>  BOOL_FIELD(ext_zvfqwdota8f)
>  BOOL_FIELD(ext_zvfwdota16bf)
> +BOOL_FIELD(ext_zvqwbdota8i)
>  BOOL_FIELD(ext_zvqwdota16i)
>  BOOL_FIELD(ext_zvqwdota8i)
>  BOOL_FIELD(ext_sdext)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 72ce0b4fbd0..782e38b608e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -711,6 +711,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvqwbdota8i && !cpu->cfg.ext_zve32x) {
> +        error_setg(errp, "Zvqwbdota8i extension depends on Zve32x extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5cb44326200..b1ca584f9ef 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>          riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>          riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> +        riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota8i) {
>          reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> @@ -94,6 +95,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      case MO_8:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
>                          cpu->cfg.ext_zvfqwdota8f ||
> +                        cpu->cfg.ext_zvqwbdota8i ||
>                          cpu->cfg.ext_zvqwdota8i);
>          break;
>      case MO_16:
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 20/38] target/riscv: Add implied rules for Zvqwbdota8i extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvqwbdota8i
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9271f79d1b6..26d5ac69c75 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2895,6 +2895,15 @@ static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvqwbdota8i),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvkn),
     .implied_multi_exts = {
@@ -3101,6 +3110,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVKS_IMPLIED,
     &ZVKSC_IMPLIED,
     &ZVKSG_IMPLIED,
+    &ZVQWBDOTA8I_IMPLIED,
     &ZVQWDOTA16I_IMPLIED,
     &ZVQWDOTA8I_IMPLIED,
     &SHA_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 20/38] target/riscv: Add implied rules for Zvqwbdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvqwbdota8i
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9271f79d1b6..26d5ac69c75 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2895,6 +2895,15 @@ static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwbdota8i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvkn),
>       .implied_multi_exts = {
> @@ -3101,6 +3110,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVKS_IMPLIED,
>       &ZVKSC_IMPLIED,
>       &ZVKSG_IMPLIED,
> +    &ZVQWBDOTA8I_IMPLIED,
>       &ZVQWDOTA16I_IMPLIED,
>       &ZVQWDOTA8I_IMPLIED,
>       &SHA_IMPLIED,

Re: [RFC PATCH 20/38] target/riscv: Add implied rules for Zvqwbdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:35 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvqwbdota8i
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9271f79d1b6..26d5ac69c75 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2895,6 +2895,15 @@ static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwbdota8i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvkn),
>      .implied_multi_exts = {
> @@ -3101,6 +3110,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVKS_IMPLIED,
>      &ZVKSC_IMPLIED,
>      &ZVKSG_IMPLIED,
> +    &ZVQWBDOTA8I_IMPLIED,
>      &ZVQWDOTA16I_IMPLIED,
>      &ZVQWDOTA8I_IMPLIED,
>      &SHA_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 21/38] target/riscv: rvv: Implement Zvqwbdota8i instructions

[Max Chou]

Implements the Zvqwbdota8i INT8 dot-product instructions:
- vqwbdotau.vv
- vqwbdotas.vv

The vqwbdotau.vv and vqwbdotas.vv instructions perform batched
dot-product operations on 8-bit integer vectors, computing 8 parallel
dot products and accumulating into 32-bit integers.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  4 ++
 target/riscv/insn32.decode                  |  4 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 75 +++++++++++++++++++++
 target/riscv/tcg/vector_helper.c            | 56 +++++++++++++++
 4 files changed, 139 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 48c64f45748..e48b9b4edec 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1400,6 +1400,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
 
+/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
+DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
+DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
+
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
 DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index def5785f8e2..bf325229100 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1108,3 +1108,7 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
 # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
 vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
+
+# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
+vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
+vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index 6eb22494838..bc12bcb9b72 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4289,3 +4289,78 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
 
 GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
 GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
+
+static bool vext_zvbdota_base_check(DisasContext *s, arg_rmrr * a,
+                                    int32_t vd_eew)
+{
+    int32_t vlenb = s->cfg_ptr->vlenb;
+    int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(vlenb));
+    uint8_t ci = a->rs2 & 0b111;
+    int rs2 = a->rs2 & ~0x7;
+
+    return require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           s->vstart_eq_zero &&
+           (s->lmul == 0) &&
+           ((ci << (3 + vd_eew)) < vlenb) &&
+           require_vm(a->vm, a->rd) &&
+           require_align(a->rd, vd_emul) &&
+           !is_overlapped(a->rd, 1 << vd_emul, a->rs1, 1) &&
+           !is_overlapped(a->rd, 1 << vd_emul, rs2, 8) &&
+           vext_check_input_eew(s, a->rs1, s->sew, rs2, s->sew, a->vm);
+}
+
+static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
+{
+    int32_t sew = s->sew;
+    int32_t vd_eew = sew + 2;
+    return vext_zvbdota_base_check(s, a, vd_eew) &&
+           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
+}
+
+typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+                                    TCGv_i32, TCGv_env, TCGv_i32);
+
+#define GEN_ZVBDOTA_INT_TRANS(NAME, CHECK)                               \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
+{                                                                        \
+    static gen_helper_zvbdota_int * const fns[2] = {                     \
+        gen_helper_##NAME##_b, NULL,                                     \
+    };                                                                   \
+    if (CHECK(s, a)) {                                                   \
+        TCGv_ptr dest, src1, src2, mask;                                 \
+        TCGv_i32 ci, desc;                                               \
+        uint32_t data = 0;                                               \
+        int32_t vd_eew = s->sew + 2;                                     \
+        int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(s->cfg_ptr->vlenb));  \
+                                                                         \
+        data = FIELD_DP32(data, VDATA, VM, a->vm);                       \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);                     \
+        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                   \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);                     \
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);   \
+                                                                         \
+        dest = tcg_temp_new_ptr();                                       \
+        mask = tcg_temp_new_ptr();                                       \
+        src1 = tcg_temp_new_ptr();                                       \
+        src2 = tcg_temp_new_ptr();                                       \
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,             \
+                                          s->cfg_ptr->vlenb, data));     \
+        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                      \
+                                                                         \
+        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));             \
+        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));            \
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));     \
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                 \
+                                                                         \
+        fns[s->sew](dest, mask, src1, src2, ci, tcg_env, desc);          \
+                                                                         \
+        finalize_rvv_inst(s);                                            \
+                                                                         \
+        return true;                                                     \
+    }                                                                    \
+    return false;                                                        \
+}
+
+GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
+GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index b1ca584f9ef..9e872eccaeb 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6139,3 +6139,59 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
 
 GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
 GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)
+
+/*
+ * Zvqwbdota8i: 8-bit Integer Batched Dot Product with Accumulation
+ */
+#define GEN_VEXT_ZVBDOTA_INT(NAME, WD, W1, T2, HD, HS)                       \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
+                  uint32_t ci, CPURISCVState *env, uint32_t desc)            \
+{                                                                            \
+    uint32_t vm = vext_vm(desc);                                             \
+    uint32_t vl = env->vl;                                                   \
+    uint32_t vta = vext_vta(desc);                                           \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                             \
+    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                              \
+    uint32_t vd_emul = vext_lmul(desc);                                      \
+    uint32_t total_elems = (vlenb << vd_emul) >> ctzl(sizeof(uint##WD##_t)); \
+    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);                  \
+    uint32_t n, k;                                                           \
+    uint32_t stride = vlenb >> ctzl(sizeof(uint##W1##_t));                   \
+    uint##WD##_t acc, dot_result, a;                                         \
+                                                                             \
+    VSTART_CHECK_EARLY_EXIT(env, vl);                                        \
+                                                                             \
+    for (n = 0; n < 8; n++) {                                                \
+        if (!vm && !vext_elem_mask(v0, ci + n)) {                            \
+            continue;                                                        \
+        }                                                                    \
+                                                                             \
+        acc = *((uint##WD##_t *)vd + HD(ci + n));                            \
+        dot_result = 0;                                                      \
+                                                                             \
+        for (k = 0; k < vl; k++) {                                           \
+            uint##WD##_t b = *((T2 *)vs2 + n * stride + HS(k));              \
+            if (altfmt) {                                                    \
+                a = *((int##W1##_t *)vs1 + HS(k));                           \
+            } else {                                                         \
+                a = *((uint##W1##_t *)vs1 + HS(k));                          \
+            }                                                                \
+            dot_result += (a * b);                                           \
+        }                                                                    \
+                                                                             \
+        *((uint##WD##_t *)vd + HD(ci + n)) = acc + dot_result;               \
+    }                                                                        \
+                                                                             \
+    env->vstart = 0;                                                         \
+                                                                             \
+    if (ci + 8 < total_elems) {                                              \
+        if (vta_all_1s) {                                                    \
+            vext_set_elems_1s(vd, vta,                                       \
+                              (ci + 8) * sizeof(int##WD##_t),                \
+                              total_elems * sizeof(int##WD##_t));            \
+        }                                                                    \
+    }                                                                        \
+}
+
+GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
+GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
-- 
2.56.0

Re: [RFC PATCH 21/38] target/riscv: rvv: Implement Zvqwbdota8i instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Implements the Zvqwbdota8i INT8 dot-product instructions:
> - vqwbdotau.vv
> - vqwbdotas.vv
> 
> The vqwbdotau.vv and vqwbdotas.vv instructions perform batched
> dot-product operations on 8-bit integer vectors, computing 8 parallel
> dot products and accumulating into 32-bit integers.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/helper.h                       |  4 ++
>   target/riscv/insn32.decode                  |  4 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 75 +++++++++++++++++++++
>   target/riscv/tcg/vector_helper.c            | 56 +++++++++++++++
>   4 files changed, 139 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 48c64f45748..e48b9b4edec 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1400,6 +1400,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   
> +/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
> +DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index def5785f8e2..bf325229100 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1108,3 +1108,7 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>   # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>   vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> +
> +# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
> +vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
> +vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 6eb22494838..bc12bcb9b72 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4289,3 +4289,78 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>   
>   GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
>   GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
> +
> +static bool vext_zvbdota_base_check(DisasContext *s, arg_rmrr * a,
> +                                    int32_t vd_eew)
> +{
> +    int32_t vlenb = s->cfg_ptr->vlenb;
> +    int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(vlenb));
> +    uint8_t ci = a->rs2 & 0b111;
> +    int rs2 = a->rs2 & ~0x7;
> +
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           s->vstart_eq_zero &&
> +           (s->lmul == 0) &&
> +           ((ci << (3 + vd_eew)) < vlenb) &&
> +           require_vm(a->vm, a->rd) &&
> +           require_align(a->rd, vd_emul) &&
> +           !is_overlapped(a->rd, 1 << vd_emul, a->rs1, 1) &&
> +           !is_overlapped(a->rd, 1 << vd_emul, rs2, 8) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, rs2, s->sew, a->vm);
> +}
> +
> +static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 2;
> +    return vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
> +}
> +
> +typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                    TCGv_i32, TCGv_env, TCGv_i32);
> +
> +#define GEN_ZVBDOTA_INT_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
> +{                                                                        \
> +    static gen_helper_zvbdota_int * const fns[2] = {                     \
> +        gen_helper_##NAME##_b, NULL,                                     \
> +    };                                                                   \
> +    if (CHECK(s, a)) {                                                   \
> +        TCGv_ptr dest, src1, src2, mask;                                 \
> +        TCGv_i32 ci, desc;                                               \
> +        uint32_t data = 0;                                               \
> +        int32_t vd_eew = s->sew + 2;                                     \
> +        int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(s->cfg_ptr->vlenb));  \
> +                                                                         \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                       \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                     \
> +        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                   \
> +        data = FIELD_DP32(data, VDATA, VMA, s->vma);                     \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);   \
> +                                                                         \
> +        dest = tcg_temp_new_ptr();                                       \
> +        mask = tcg_temp_new_ptr();                                       \
> +        src1 = tcg_temp_new_ptr();                                       \
> +        src2 = tcg_temp_new_ptr();                                       \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,             \
> +                                          s->cfg_ptr->vlenb, data));     \
> +        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                      \
> +                                                                         \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));             \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));            \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));     \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                 \
> +                                                                         \
> +        fns[s->sew](dest, mask, src1, src2, ci, tcg_env, desc);          \
> +                                                                         \
> +        finalize_rvv_inst(s);                                            \
> +                                                                         \
> +        return true;                                                     \
> +    }                                                                    \
> +    return false;                                                        \
> +}
> +
> +GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
> +GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index b1ca584f9ef..9e872eccaeb 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6139,3 +6139,59 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
>   
>   GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
>   GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)
> +
> +/*
> + * Zvqwbdota8i: 8-bit Integer Batched Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVBDOTA_INT(NAME, WD, W1, T2, HD, HS)                       \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
> +                  uint32_t ci, CPURISCVState *env, uint32_t desc)            \
> +{                                                                            \
> +    uint32_t vm = vext_vm(desc);                                             \
> +    uint32_t vl = env->vl;                                                   \
> +    uint32_t vta = vext_vta(desc);                                           \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                             \
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                              \
> +    uint32_t vd_emul = vext_lmul(desc);                                      \
> +    uint32_t total_elems = (vlenb << vd_emul) >> ctzl(sizeof(uint##WD##_t)); \
> +    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);                  \
> +    uint32_t n, k;                                                           \
> +    uint32_t stride = vlenb >> ctzl(sizeof(uint##W1##_t));                   \
> +    uint##WD##_t acc, dot_result, a;                                         \
> +                                                                             \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                        \
> +                                                                             \
> +    for (n = 0; n < 8; n++) {                                                \
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {                            \
> +            continue;                                                        \
> +        }                                                                    \
> +                                                                             \
> +        acc = *((uint##WD##_t *)vd + HD(ci + n));                            \
> +        dot_result = 0;                                                      \
> +                                                                             \
> +        for (k = 0; k < vl; k++) {                                           \
> +            uint##WD##_t b = *((T2 *)vs2 + n * stride + HS(k));              \
> +            if (altfmt) {                                                    \
> +                a = *((int##W1##_t *)vs1 + HS(k));                           \
> +            } else {                                                         \
> +                a = *((uint##W1##_t *)vs1 + HS(k));                          \
> +            }                                                                \
> +            dot_result += (a * b);                                           \
> +        }                                                                    \
> +                                                                             \
> +        *((uint##WD##_t *)vd + HD(ci + n)) = acc + dot_result;               \
> +    }                                                                        \
> +                                                                             \
> +    env->vstart = 0;                                                         \
> +                                                                             \
> +    if (ci + 8 < total_elems) {                                              \
> +        if (vta_all_1s) {                                                    \
> +            vext_set_elems_1s(vd, vta,                                       \
> +                              (ci + 8) * sizeof(int##WD##_t),                \
> +                              total_elems * sizeof(int##WD##_t));            \
> +        }                                                                    \
> +    }                                                                        \
> +}
> +
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)

Re: [RFC PATCH 21/38] target/riscv: rvv: Implement Zvqwbdota8i instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:36 +0800 Max Chou <max.chou@sifive.com> wrote:

> Implements the Zvqwbdota8i INT8 dot-product instructions:
> - vqwbdotau.vv
> - vqwbdotas.vv
> 
> The vqwbdotau.vv and vqwbdotas.vv instructions perform batched
> dot-product operations on 8-bit integer vectors, computing 8 parallel
> dot products and accumulating into 32-bit integers.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/helper.h                       |  4 ++
>  target/riscv/insn32.decode                  |  4 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 75 +++++++++++++++++++++
>  target/riscv/tcg/vector_helper.c            | 56 +++++++++++++++
>  4 files changed, 139 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 48c64f45748..e48b9b4edec 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1400,6 +1400,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  
> +/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
> +DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index def5785f8e2..bf325229100 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1108,3 +1108,7 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>  # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>  vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> +
> +# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
> +vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
> +vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 6eb22494838..bc12bcb9b72 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4289,3 +4289,78 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                  \
>  
>  GEN_ZVDOTA_FP8_TRANS(vfqwdota_vv, vext_vfqwdota_check)
>  GEN_ZVDOTA_FP8_TRANS(vfqwdota_alt_vv, vext_vfqwdota_check)
> +
> +static bool vext_zvbdota_base_check(DisasContext *s, arg_rmrr * a,
> +                                    int32_t vd_eew)
> +{
> +    int32_t vlenb = s->cfg_ptr->vlenb;
> +    int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(vlenb));
> +    uint8_t ci = a->rs2 & 0b111;
> +    int rs2 = a->rs2 & ~0x7;
> +
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           s->vstart_eq_zero &&
> +           (s->lmul == 0) &&
> +           ((ci << (3 + vd_eew)) < vlenb) &&
> +           require_vm(a->vm, a->rd) &&
> +           require_align(a->rd, vd_emul) &&
> +           !is_overlapped(a->rd, 1 << vd_emul, a->rs1, 1) &&
> +           !is_overlapped(a->rd, 1 << vd_emul, rs2, 8) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, rs2, s->sew, a->vm);
> +}
> +
> +static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 2;
> +    return vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
> +}
> +
> +typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> +                                    TCGv_i32, TCGv_env, TCGv_i32);
> +
> +#define GEN_ZVBDOTA_INT_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
> +{                                                                        \
> +    static gen_helper_zvbdota_int * const fns[2] = {                     \
> +        gen_helper_##NAME##_b, NULL,                                     \
> +    };                                                                   \
> +    if (CHECK(s, a)) {                                                   \
> +        TCGv_ptr dest, src1, src2, mask;                                 \
> +        TCGv_i32 ci, desc;                                               \
> +        uint32_t data = 0;                                               \
> +        int32_t vd_eew = s->sew + 2;                                     \
> +        int32_t vd_emul = MAX(0, vd_eew + 3 - ctzl(s->cfg_ptr->vlenb));  \
> +                                                                         \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                       \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                     \
> +        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                   \
> +        data = FIELD_DP32(data, VDATA, VMA, s->vma);                     \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);   \
> +                                                                         \
> +        dest = tcg_temp_new_ptr();                                       \
> +        mask = tcg_temp_new_ptr();                                       \
> +        src1 = tcg_temp_new_ptr();                                       \
> +        src2 = tcg_temp_new_ptr();                                       \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,             \
> +                                          s->cfg_ptr->vlenb, data));     \
> +        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                      \
> +                                                                         \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));             \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));            \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));     \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                 \
> +                                                                         \
> +        fns[s->sew](dest, mask, src1, src2, ci, tcg_env, desc);          \
> +                                                                         \
> +        finalize_rvv_inst(s);                                            \
> +                                                                         \
> +        return true;                                                     \
> +    }                                                                    \
> +    return false;                                                        \
> +}
> +
> +GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
> +GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index b1ca584f9ef..9e872eccaeb 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6139,3 +6139,59 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
>  
>  GEN_VEXT_ZVDOTA_FP8(vfqwdota_vv, e4m3)
>  GEN_VEXT_ZVDOTA_FP8(vfqwdota_alt_vv, e5m2)
> +
> +/*
> + * Zvqwbdota8i: 8-bit Integer Batched Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVBDOTA_INT(NAME, WD, W1, T2, HD, HS)                       \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
> +                  uint32_t ci, CPURISCVState *env, uint32_t desc)            \
> +{                                                                            \
> +    uint32_t vm = vext_vm(desc);                                             \
> +    uint32_t vl = env->vl;                                                   \
> +    uint32_t vta = vext_vta(desc);                                           \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                             \
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                              \
> +    uint32_t vd_emul = vext_lmul(desc);                                      \
> +    uint32_t total_elems = (vlenb << vd_emul) >> ctzl(sizeof(uint##WD##_t)); \
> +    uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);                  \
> +    uint32_t n, k;                                                           \
> +    uint32_t stride = vlenb >> ctzl(sizeof(uint##W1##_t));                   \
> +    uint##WD##_t acc, dot_result, a;                                         \
> +                                                                             \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                        \
> +                                                                             \
> +    for (n = 0; n < 8; n++) {                                                \
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {                            \
> +            continue;                                                        \
> +        }                                                                    \
> +                                                                             \
> +        acc = *((uint##WD##_t *)vd + HD(ci + n));                            \
> +        dot_result = 0;                                                      \
> +                                                                             \
> +        for (k = 0; k < vl; k++) {                                           \
> +            uint##WD##_t b = *((T2 *)vs2 + n * stride + HS(k));              \
> +            if (altfmt) {                                                    \
> +                a = *((int##W1##_t *)vs1 + HS(k));                           \
> +            } else {                                                         \
> +                a = *((uint##W1##_t *)vs1 + HS(k));                          \
> +            }                                                                \
> +            dot_result += (a * b);                                           \
> +        }                                                                    \
> +                                                                             \
> +        *((uint##WD##_t *)vd + HD(ci + n)) = acc + dot_result;               \
> +    }                                                                        \
> +                                                                             \
> +    env->vstart = 0;                                                         \
> +                                                                             \
> +    if (ci + 8 < total_elems) {                                              \
> +        if (vta_all_1s) {                                                    \
> +            vext_set_elems_1s(vd, vta,                                       \
> +                              (ci + 8) * sizeof(int##WD##_t),                \
> +                              total_elems * sizeof(int##WD##_t));            \
> +        }                                                                    \
> +    }                                                                        \
> +}
> +
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 22/38] disas/riscv: Support Zvqwbdota8i extension

[Max Chou]

Adds support to disassemble Zvqwbdota8i instructions.
- vqwbdotau.vv
- vqwbdotas.vv

Zvbdota instructions encode the batch-column immediate (ci) in rs2[2:0]
and the vs2 base-register group in rs2[7:3].
Add rv_codec_v_r_ci that splits rs2 into dec->rs2 (base register) and
dec->imm (ci), and add rv_fmt_vd_vs2_vs1_ci_vm to print them separately.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 2 ++
 disas/riscv.c        | 9 +++++++++
 disas/riscv.h        | 2 ++
 3 files changed, 13 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 5ba29f52976..bb01ebb8a6c 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -773,6 +773,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
 OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
 OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vqwbdotas_vv, "vqwbdotas.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
+OP(vqwbdotau_vv, "vqwbdotau.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
 OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index 0f609cc06b4..0534b8f4d64 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2638,6 +2638,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 switch ((inst >> 26) & 0b111111) {
                 case 38: return &op_vqwdotau_vv;
                 case 39: return &op_vqwdotas_vv;
+                case 46: return &op_vqwbdotau_vv;
+                case 47: return &op_vqwbdotas_vv;
                 }
             }
             if (((inst >> 12) & 0b111) == 1) {
@@ -2999,6 +3001,13 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
         dec->rs2 = operand_rs2(inst);
         dec->vm = operand_vm(inst);
         break;
+    case rv_codec_v_r_ci:
+        dec->rd = operand_rd(inst);
+        dec->rs1 = operand_rs1(inst);
+        dec->rs2 = operand_rs2(inst) & ~0x7;
+        dec->imm = (operand_rs2(inst) & 0x7) << 3;
+        dec->vm = operand_vm(inst);
+        break;
     case rv_codec_v_ldst:
         dec->rd = operand_rd(inst);
         dec->rs1 = operand_rs1(inst);
diff --git a/disas/riscv.h b/disas/riscv.h
index 4f1ffc4ae02..34050583c96 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -138,6 +138,7 @@ typedef enum {
     rv_codec_k_bs,
     rv_codec_k_rnum,
     rv_codec_v_r,
+    rv_codec_v_r_ci,
     rv_codec_v_ldst,
     rv_codec_v_i,
     rv_codec_v_i_u,
@@ -254,6 +255,7 @@ typedef struct {
 #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
 #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
 #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
+#define rv_fmt_vd_vs2_vs1_ci_vm       "O\tD,F,E,im"
 #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
 #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
 #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
-- 
2.56.0

Re: [RFC PATCH 22/38] disas/riscv: Support Zvqwbdota8i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support to disassemble Zvqwbdota8i instructions.
> - vqwbdotau.vv
> - vqwbdotas.vv
> 
> Zvbdota instructions encode the batch-column immediate (ci) in rs2[2:0]
> and the vs2 base-register group in rs2[7:3].
> Add rv_codec_v_r_ci that splits rs2 into dec->rs2 (base register) and
> dec->imm (ci), and add rv_fmt_vd_vs2_vs1_ci_vm to print them separately.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 2 ++
>   disas/riscv.c        | 9 +++++++++
>   disas/riscv.h        | 2 ++
>   3 files changed, 13 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 5ba29f52976..bb01ebb8a6c 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -773,6 +773,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>   OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
>   OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vqwbdotas_vv, "vqwbdotas.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
> +OP(vqwbdotau_vv, "vqwbdotau.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>   OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 0f609cc06b4..0534b8f4d64 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2638,6 +2638,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   switch ((inst >> 26) & 0b111111) {
>                   case 38: return &op_vqwdotau_vv;
>                   case 39: return &op_vqwdotas_vv;
> +                case 46: return &op_vqwbdotau_vv;
> +                case 47: return &op_vqwbdotas_vv;
>                   }
>               }
>               if (((inst >> 12) & 0b111) == 1) {
> @@ -2999,6 +3001,13 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
>           dec->rs2 = operand_rs2(inst);
>           dec->vm = operand_vm(inst);
>           break;
> +    case rv_codec_v_r_ci:
> +        dec->rd = operand_rd(inst);
> +        dec->rs1 = operand_rs1(inst);
> +        dec->rs2 = operand_rs2(inst) & ~0x7;
> +        dec->imm = (operand_rs2(inst) & 0x7) << 3;
> +        dec->vm = operand_vm(inst);
> +        break;
>       case rv_codec_v_ldst:
>           dec->rd = operand_rd(inst);
>           dec->rs1 = operand_rs1(inst);
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 4f1ffc4ae02..34050583c96 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -138,6 +138,7 @@ typedef enum {
>       rv_codec_k_bs,
>       rv_codec_k_rnum,
>       rv_codec_v_r,
> +    rv_codec_v_r_ci,
>       rv_codec_v_ldst,
>       rv_codec_v_i,
>       rv_codec_v_i_u,
> @@ -254,6 +255,7 @@ typedef struct {
>   #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
>   #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
>   #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
> +#define rv_fmt_vd_vs2_vs1_ci_vm       "O\tD,F,E,im"
>   #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
>   #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
>   #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"

Re: [RFC PATCH 22/38] disas/riscv: Support Zvqwbdota8i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:37 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support to disassemble Zvqwbdota8i instructions.
> - vqwbdotau.vv
> - vqwbdotas.vv
> 
> Zvbdota instructions encode the batch-column immediate (ci) in rs2[2:0]
> and the vs2 base-register group in rs2[7:3].
> Add rv_codec_v_r_ci that splits rs2 into dec->rs2 (base register) and
> dec->imm (ci), and add rv_fmt_vd_vs2_vs1_ci_vm to print them separately.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 2 ++
>  disas/riscv.c        | 9 +++++++++
>  disas/riscv.h        | 2 ++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 5ba29f52976..bb01ebb8a6c 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -773,6 +773,8 @@ OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>  OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
>  OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vqwbdotas_vv, "vqwbdotas.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
> +OP(vqwbdotau_vv, "vqwbdotau.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>  OP(vqwdotas_vv, "vqwdotas.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vqwdotau_vv, "vqwdotau.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 0f609cc06b4..0534b8f4d64 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2638,6 +2638,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  switch ((inst >> 26) & 0b111111) {
>                  case 38: return &op_vqwdotau_vv;
>                  case 39: return &op_vqwdotas_vv;
> +                case 46: return &op_vqwbdotau_vv;
> +                case 47: return &op_vqwbdotas_vv;
>                  }
>              }
>              if (((inst >> 12) & 0b111) == 1) {
> @@ -2999,6 +3001,13 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
>          dec->rs2 = operand_rs2(inst);
>          dec->vm = operand_vm(inst);
>          break;
> +    case rv_codec_v_r_ci:
> +        dec->rd = operand_rd(inst);
> +        dec->rs1 = operand_rs1(inst);
> +        dec->rs2 = operand_rs2(inst) & ~0x7;
> +        dec->imm = (operand_rs2(inst) & 0x7) << 3;
> +        dec->vm = operand_vm(inst);
> +        break;
>      case rv_codec_v_ldst:
>          dec->rd = operand_rd(inst);
>          dec->rs1 = operand_rs1(inst);
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 4f1ffc4ae02..34050583c96 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -138,6 +138,7 @@ typedef enum {
>      rv_codec_k_bs,
>      rv_codec_k_rnum,
>      rv_codec_v_r,
> +    rv_codec_v_r_ci,
>      rv_codec_v_ldst,
>      rv_codec_v_i,
>      rv_codec_v_i_u,
> @@ -254,6 +255,7 @@ typedef struct {
>  #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
>  #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
>  #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
> +#define rv_fmt_vd_vs2_vs1_ci_vm       "O\tD,F,E,im"
>  #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
>  #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
>  #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 23/38] target/riscv: Add cfg property for Zvqwbdota16i extension

[Max Chou]

Add CPU configuration property of Zvqwbdota16i extension which depends on
the Zve64x extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 26d5ac69c75..99c82b898f0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota16i, PRIV_VERSION_1_13_0,
+                                    ext_zvqwbdota16i),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
                                     ext_zvqwbdota8i),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 3d822432d48..83a3d8a7f9d 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
 BOOL_FIELD(ext_zvfqwdota8f)
 BOOL_FIELD(ext_zvfwdota16bf)
+BOOL_FIELD(ext_zvqwbdota16i)
 BOOL_FIELD(ext_zvqwbdota8i)
 BOOL_FIELD(ext_zvqwdota16i)
 BOOL_FIELD(ext_zvqwdota8i)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 782e38b608e..8735cf94f35 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -716,6 +716,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvqwbdota16i && !cpu->cfg.ext_zve64x) {
+        error_setg(errp, "Zvqwbdota16i extension depends on Zve64x extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 9e872eccaeb..5ea073b6d76 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
         riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
         riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
+        riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
         riscv_cpu_cfg(env)->ext_zvqwdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwdota8i) {
@@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     case MO_16:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
                         cpu->cfg.ext_zvfwdota16bf ||
+                        cpu->cfg.ext_zvqwbdota16i ||
                         cpu->cfg.ext_zvqwdota16i);
         break;
     default:
-- 
2.56.0

Re: [RFC PATCH 23/38] target/riscv: Add cfg property for Zvqwbdota16i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvqwbdota16i extension which depends on
> the Zve64x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 26d5ac69c75..99c82b898f0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>       ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>       ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota16i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwbdota16i),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
>                                       ext_zvqwbdota8i),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 3d822432d48..83a3d8a7f9d 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
>   BOOL_FIELD(ext_zvfqwdota8f)
>   BOOL_FIELD(ext_zvfwdota16bf)
> +BOOL_FIELD(ext_zvqwbdota16i)
>   BOOL_FIELD(ext_zvqwbdota8i)
>   BOOL_FIELD(ext_zvqwdota16i)
>   BOOL_FIELD(ext_zvqwdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 782e38b608e..8735cf94f35 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -716,6 +716,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvqwbdota16i && !cpu->cfg.ext_zve64x) {
> +        error_setg(errp, "Zvqwbdota16i extension depends on Zve64x extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 9e872eccaeb..5ea073b6d76 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>           riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>           riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> +        riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwdota8i) {
> @@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       case MO_16:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
>                           cpu->cfg.ext_zvfwdota16bf ||
> +                        cpu->cfg.ext_zvqwbdota16i ||
>                           cpu->cfg.ext_zvqwdota16i);
>           break;
>       default:

Re: [RFC PATCH 23/38] target/riscv: Add cfg property for Zvqwbdota16i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:38 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvqwbdota16i extension which depends on
> the Zve64x extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 26d5ac69c75..99c82b898f0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -254,6 +254,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
>      ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota16i, PRIV_VERSION_1_13_0,
> +                                    ext_zvqwbdota16i),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwbdota8i, PRIV_VERSION_1_13_0,
>                                      ext_zvqwbdota8i),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvqwdota16i, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 3d822432d48..83a3d8a7f9d 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -108,6 +108,7 @@ BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
>  BOOL_FIELD(ext_zvfqwdota8f)
>  BOOL_FIELD(ext_zvfwdota16bf)
> +BOOL_FIELD(ext_zvqwbdota16i)
>  BOOL_FIELD(ext_zvqwbdota8i)
>  BOOL_FIELD(ext_zvqwdota16i)
>  BOOL_FIELD(ext_zvqwdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 782e38b608e..8735cf94f35 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -716,6 +716,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvqwbdota16i && !cpu->cfg.ext_zve64x) {
> +        error_setg(errp, "Zvqwbdota16i extension depends on Zve64x extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 9e872eccaeb..5ea073b6d76 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -42,6 +42,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>          riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>          riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> +        riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwdota8i) {
> @@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      case MO_16:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
>                          cpu->cfg.ext_zvfwdota16bf ||
> +                        cpu->cfg.ext_zvqwbdota16i ||
>                          cpu->cfg.ext_zvqwdota16i);
>          break;
>      default:
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 24/38] target/riscv: Add implied rules for Zvqwbdota16i extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvqwbdota16i
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 99c82b898f0..95bba330e06 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2906,6 +2906,15 @@ static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVQWBDOTA16I_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvqwbdota16i),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve64x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvkn),
     .implied_multi_exts = {
@@ -3112,6 +3121,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVKS_IMPLIED,
     &ZVKSC_IMPLIED,
     &ZVKSG_IMPLIED,
+    &ZVQWBDOTA16I_IMPLIED,
     &ZVQWBDOTA8I_IMPLIED,
     &ZVQWDOTA16I_IMPLIED,
     &ZVQWDOTA8I_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 24/38] target/riscv: Add implied rules for Zvqwbdota16i extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvqwbdota16i
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 99c82b898f0..95bba330e06 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2906,6 +2906,15 @@ static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVQWBDOTA16I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwbdota16i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve64x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvkn),
>       .implied_multi_exts = {
> @@ -3112,6 +3121,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVKS_IMPLIED,
>       &ZVKSC_IMPLIED,
>       &ZVKSG_IMPLIED,
> +    &ZVQWBDOTA16I_IMPLIED,
>       &ZVQWBDOTA8I_IMPLIED,
>       &ZVQWDOTA16I_IMPLIED,
>       &ZVQWDOTA8I_IMPLIED,

Re: [RFC PATCH 24/38] target/riscv: Add implied rules for Zvqwbdota16i extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:39 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvqwbdota16i
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 99c82b898f0..95bba330e06 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2906,6 +2906,15 @@ static RISCVCPUImpliedExtsRule ZVQWBDOTA8I_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVQWBDOTA16I_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvqwbdota16i),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve64x),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvkn),
>      .implied_multi_exts = {
> @@ -3112,6 +3121,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVKS_IMPLIED,
>      &ZVKSC_IMPLIED,
>      &ZVKSG_IMPLIED,
> +    &ZVQWBDOTA16I_IMPLIED,
>      &ZVQWBDOTA8I_IMPLIED,
>      &ZVQWDOTA16I_IMPLIED,
>      &ZVQWDOTA8I_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 25/38] target/riscv: rvv: Implement Zvqwbdota16i instructions

[Max Chou]

Extend the vqwbdotau.vv and vqwbdotas.vv instructions to support
both 8-bit (Zvqwbdota8i) and 16-bit (Zvqwbdota16i) batched
dot-product operations.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       | 4 +++-
 target/riscv/insn32.decode                  | 2 +-
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
 target/riscv/tcg/vector_helper.c            | 2 ++
 4 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e48b9b4edec..84571a999f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1400,9 +1400,11 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
 
-/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
+/* Zvqwbdota8i/Zvqwbdota16i - 8/16-bit Integer Batched Dot Product */
 DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
 DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
+DEF_HELPER_7(vqwbdotau_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
+DEF_HELPER_7(vqwbdotas_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
 
 /* SiFive Custom int8 Matrix-Multiply */
 DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bf325229100..8a06547a570 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1109,6 +1109,6 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
 
-# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
+# *** Zvqwbdota8i/Zvqwbdota16i Integer Batched Dot-Product Extension ***
 vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
 vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index bc12bcb9b72..650affc045b 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4315,7 +4315,8 @@ static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
     int32_t sew = s->sew;
     int32_t vd_eew = sew + 2;
     return vext_zvbdota_base_check(s, a, vd_eew) &&
-           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
+           ((s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8) ||
+            (s->cfg_ptr->ext_zvqwbdota16i && s->sew == MO_16));
 }
 
 typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
@@ -4325,7 +4326,7 @@ typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
 {                                                                        \
     static gen_helper_zvbdota_int * const fns[2] = {                     \
-        gen_helper_##NAME##_b, NULL,                                     \
+        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                    \
     };                                                                   \
     if (CHECK(s, a)) {                                                   \
         TCGv_ptr dest, src1, src2, mask;                                 \
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 5ea073b6d76..683b14f28f3 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6197,3 +6197,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
 
 GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
 GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
+GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
+GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)
-- 
2.56.0

Re: [RFC PATCH 25/38] target/riscv: rvv: Implement Zvqwbdota16i instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Extend the vqwbdotau.vv and vqwbdotas.vv instructions to support
> both 8-bit (Zvqwbdota8i) and 16-bit (Zvqwbdota16i) batched
> dot-product operations.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/helper.h                       | 4 +++-
>   target/riscv/insn32.decode                  | 2 +-
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
>   target/riscv/tcg/vector_helper.c            | 2 ++
>   4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index e48b9b4edec..84571a999f4 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1400,9 +1400,11 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   
> -/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
> +/* Zvqwbdota8i/Zvqwbdota16i - 8/16-bit Integer Batched Dot Product */
>   DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotau_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotas_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   
>   /* SiFive Custom int8 Matrix-Multiply */
>   DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index bf325229100..8a06547a570 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1109,6 +1109,6 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
>   
> -# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
> +# *** Zvqwbdota8i/Zvqwbdota16i Integer Batched Dot-Product Extension ***
>   vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
>   vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index bc12bcb9b72..650affc045b 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4315,7 +4315,8 @@ static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
>       int32_t sew = s->sew;
>       int32_t vd_eew = sew + 2;
>       return vext_zvbdota_base_check(s, a, vd_eew) &&
> -           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
> +           ((s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8) ||
> +            (s->cfg_ptr->ext_zvqwbdota16i && s->sew == MO_16));
>   }
>   
>   typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> @@ -4325,7 +4326,7 @@ typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
>   {                                                                        \
>       static gen_helper_zvbdota_int * const fns[2] = {                     \
> -        gen_helper_##NAME##_b, NULL,                                     \
> +        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                    \
>       };                                                                   \
>       if (CHECK(s, a)) {                                                   \
>           TCGv_ptr dest, src1, src2, mask;                                 \
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5ea073b6d76..683b14f28f3 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6197,3 +6197,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
>   
>   GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
>   GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)

Re: [RFC PATCH 25/38] target/riscv: rvv: Implement Zvqwbdota16i instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:40 +0800 Max Chou <max.chou@sifive.com> wrote:

> Extend the vqwbdotau.vv and vqwbdotas.vv instructions to support
> both 8-bit (Zvqwbdota8i) and 16-bit (Zvqwbdota16i) batched
> dot-product operations.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/helper.h                       | 4 +++-
>  target/riscv/insn32.decode                  | 2 +-
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 5 +++--
>  target/riscv/tcg/vector_helper.c            | 2 ++
>  4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index e48b9b4edec..84571a999f4 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1400,9 +1400,11 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  
> -/* Zvqwbdota8i - 8-bit Integer Batched Dot Product */
> +/* Zvqwbdota8i/Zvqwbdota16i - 8/16-bit Integer Batched Dot Product */
>  DEF_HELPER_7(vqwbdotau_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  DEF_HELPER_7(vqwbdotas_vv_b, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotau_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vqwbdotas_vv_h, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  
>  /* SiFive Custom int8 Matrix-Multiply */
>  DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index bf325229100..8a06547a570 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1109,6 +1109,6 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
>  
> -# *** Zvqwbdota8i 8-bit Integer Batched Dot-Product Extension ***
> +# *** Zvqwbdota8i/Zvqwbdota16i Integer Batched Dot-Product Extension ***
>  vqwbdotau_vv  101110 . ..... ..... 000 ..... 1110111 @r_vm
>  vqwbdotas_vv  101111 . ..... ..... 000 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index bc12bcb9b72..650affc045b 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4315,7 +4315,8 @@ static bool vext_vqwbdota_check(DisasContext *s, arg_rmrr *a)
>      int32_t sew = s->sew;
>      int32_t vd_eew = sew + 2;
>      return vext_zvbdota_base_check(s, a, vd_eew) &&
> -           (s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8);
> +           ((s->cfg_ptr->ext_zvqwbdota8i && sew == MO_8) ||
> +            (s->cfg_ptr->ext_zvqwbdota16i && s->sew == MO_16));
>  }
>  
>  typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
> @@ -4325,7 +4326,7 @@ typedef void gen_helper_zvbdota_int(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
>  static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
>  {                                                                        \
>      static gen_helper_zvbdota_int * const fns[2] = {                     \
> -        gen_helper_##NAME##_b, NULL,                                     \
> +        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                    \
>      };                                                                   \
>      if (CHECK(s, a)) {                                                   \
>          TCGv_ptr dest, src1, src2, mask;                                 \
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 5ea073b6d76..683b14f28f3 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6197,3 +6197,5 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,                  \
>  
>  GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
>  GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
> +GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 26/38] target/riscv: Add cfg property for Zvfwbdota16bf extension

[Max Chou]

Add CPU configuration property of Zvfwbdota16bf extension which depends on
the Zve32f extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 95bba330e06..c33885542f5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -238,6 +238,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
                                     ext_zvfqwdota8f),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
+                                    ext_zvfwbdota16bf),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
                                     ext_zvfwdota16bf),
     ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 83a3d8a7f9d..80750db1ccd 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -107,6 +107,7 @@ BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
 BOOL_FIELD(ext_zvfqwdota8f)
+BOOL_FIELD(ext_zvfwbdota16bf)
 BOOL_FIELD(ext_zvfwdota16bf)
 BOOL_FIELD(ext_zvqwbdota16i)
 BOOL_FIELD(ext_zvqwbdota8i)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 8735cf94f35..8684e4c709c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -721,6 +721,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfwbdota16bf && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfwbdota16bf extension depends on Zve32f extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 683b14f28f3..873adf4d7a6 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -41,6 +41,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
 
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
         riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
+        riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
         riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
         riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
         riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
@@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
         break;
     case MO_16:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvfwbdota16bf ||
                         cpu->cfg.ext_zvfwdota16bf ||
                         cpu->cfg.ext_zvqwbdota16i ||
                         cpu->cfg.ext_zvqwdota16i);
-- 
2.56.0

Re: [RFC PATCH 26/38] target/riscv: Add cfg property for Zvfwbdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvfwbdota16bf extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 95bba330e06..c33885542f5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -238,6 +238,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
>                                       ext_zvfqwdota8f),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
> +                                    ext_zvfwbdota16bf),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
>                                       ext_zvfwdota16bf),
>       ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 83a3d8a7f9d..80750db1ccd 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -107,6 +107,7 @@ BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
>   BOOL_FIELD(ext_zvfqwdota8f)
> +BOOL_FIELD(ext_zvfwbdota16bf)
>   BOOL_FIELD(ext_zvfwdota16bf)
>   BOOL_FIELD(ext_zvqwbdota16i)
>   BOOL_FIELD(ext_zvqwbdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8735cf94f35..8684e4c709c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -721,6 +721,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfwbdota16bf && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfwbdota16bf extension depends on Zve32f extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 683b14f28f3..873adf4d7a6 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -41,6 +41,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>   
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>           riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
> +        riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
>           riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>           riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
>           riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
> @@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>           break;
>       case MO_16:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfwbdota16bf ||
>                           cpu->cfg.ext_zvfwdota16bf ||
>                           cpu->cfg.ext_zvqwbdota16i ||
>                           cpu->cfg.ext_zvqwdota16i);

Re: [RFC PATCH 26/38] target/riscv: Add cfg property for Zvfwbdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:41 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvfwbdota16bf extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
r ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 95bba330e06..c33885542f5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -238,6 +238,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
>                                      ext_zvfqwdota8f),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
> +                                    ext_zvfwbdota16bf),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwdota16bf, PRIV_VERSION_1_13_0,
>                                      ext_zvfwdota16bf),
>      ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 83a3d8a7f9d..80750db1ccd 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -107,6 +107,7 @@ BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
>  BOOL_FIELD(ext_zvfqwdota8f)
> +BOOL_FIELD(ext_zvfwbdota16bf)
>  BOOL_FIELD(ext_zvfwdota16bf)
>  BOOL_FIELD(ext_zvqwbdota16i)
>  BOOL_FIELD(ext_zvqwbdota8i)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8735cf94f35..8684e4c709c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -721,6 +721,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvfwbdota16bf && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfwbdota16bf extension depends on Zve32f extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 683b14f28f3..873adf4d7a6 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -41,6 +41,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>  
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
>          riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
> +        riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
>          riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
>          riscv_cpu_cfg(env)->ext_zvqwbdota16i ||
>          riscv_cpu_cfg(env)->ext_zvqwbdota8i ||
> @@ -101,6 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>          break;
>      case MO_16:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfwbdota16bf ||
>                          cpu->cfg.ext_zvfwdota16bf ||
>                          cpu->cfg.ext_zvqwbdota16i ||
>                          cpu->cfg.ext_zvqwdota16i);
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 27/38] target/riscv: Add implied rules for Zvfwbdota16bf extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvfwbdota16bf
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c33885542f5..566e2e835ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2890,6 +2890,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32f),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
     .implied_multi_exts = {
@@ -3115,6 +3124,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVFH_IMPLIED,
     &ZVFHMIN_IMPLIED,
     &ZVFQWDOTA8F_IMPLIED,
+    &ZVFWBDOTA16BF_IMPLIED,
     &ZVFWDOTA16BF_IMPLIED,
     &ZVKN_IMPLIED,
     &ZVKNC_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 27/38] target/riscv: Add implied rules for Zvfwbdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfwbdota16bf
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c33885542f5..566e2e835ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2890,6 +2890,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
>       .implied_multi_exts = {
> @@ -3115,6 +3124,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVFH_IMPLIED,
>       &ZVFHMIN_IMPLIED,
>       &ZVFQWDOTA8F_IMPLIED,
> +    &ZVFWBDOTA16BF_IMPLIED,
>       &ZVFWDOTA16BF_IMPLIED,
>       &ZVKN_IMPLIED,
>       &ZVKNC_IMPLIED,

Re: [RFC PATCH 27/38] target/riscv: Add implied rules for Zvfwbdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:42 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvfwbdota16bf
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c33885542f5..566e2e835ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2890,6 +2890,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVFWDOTA16BF_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvfwdota16bf),
>      .implied_multi_exts = {
> @@ -3115,6 +3124,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVFH_IMPLIED,
>      &ZVFHMIN_IMPLIED,
>      &ZVFQWDOTA8F_IMPLIED,
> +    &ZVFWBDOTA16BF_IMPLIED,
>      &ZVFWDOTA16BF_IMPLIED,
>      &ZVKN_IMPLIED,
>      &ZVKNC_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 28/38] target/riscv: rvv: Implement Zvfwbdota16bf instruction

[Max Chou]

Implement the vfwbdota.vv instruction from the Zvfwbdota16bf
extension.
This instruction performs a batched dot-product operation on BF16
vectors, accumulating into FP32

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  2 +
 target/riscv/insn32.decode                  |  3 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 52 +++++++++++++++++++
 target/riscv/tcg/vector_helper.c            | 55 +++++++++++++++++++++
 4 files changed, 112 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 84571a999f4..1f2dfd6d557 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1395,6 +1395,8 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
 
 /* Zvfwdota16bf - BF16 Dot Product */
 DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
+/* Zvfwbdota16bf - BF16 Batched Dot Product */
+DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
 
 /* Zvfqwdota8f - OCP FP8 Dot Product */
 DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8a06547a570..00ed64b73fd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1105,6 +1105,9 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
 # *** Zvfwdota16bf BF16 Dot-Product Extension ***
 vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
 
+# *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
+vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
+
 # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
 vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index 650affc045b..d4678171ac5 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4365,3 +4365,55 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
 
 GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
 GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
+
+/* Zvfwbdota16bf BF16 Batched Dot-Product Extension */
+static bool vext_vfwbdota_check(DisasContext *s, arg_rmrr * a)
+{
+    int32_t sew = s->sew;
+    int32_t vd_eew = sew + 1;
+    return s->mstatus_fs != EXT_STATUS_DISABLED &&
+           vext_zvbdota_base_check(s, a, vd_eew) &&
+           (s->cfg_ptr->ext_zvfwbdota16bf && s->sew == MO_16 && s->altfmt == 1);
+}
+
+#define GEN_ZVBDOTA_FP_TRANS(NAME, CHECK, EEW_VD)                       \
+static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
+{                                                                       \
+    if (CHECK(s, a)) {                                                  \
+        TCGv_ptr dest, src1, src2, mask;                                \
+        TCGv_i32 ci, desc;                                              \
+        uint32_t data = 0;                                              \
+        uint32_t vlenb = s->cfg_ptr->vlenb;                             \
+        int32_t vd_emul = MAX(0, EEW_VD + 3 - ctzl(vlenb));             \
+                                                                        \
+        gen_set_rm(s, RISCV_FRM_DYN);                                   \
+                                                                        \
+        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
+        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                  \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);                    \
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
+        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
+                                                                        \
+        dest = tcg_temp_new_ptr();                                      \
+        mask = tcg_temp_new_ptr();                                      \
+        src1 = tcg_temp_new_ptr();                                      \
+        src2 = tcg_temp_new_ptr();                                      \
+        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
+                                          s->cfg_ptr->vlenb, data));    \
+        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                     \
+                                                                        \
+        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
+        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
+        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));    \
+        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
+                                                                        \
+        gen_helper_##NAME(dest, mask, src1, src2, ci, tcg_env, desc);   \
+                                                                        \
+        finalize_rvv_inst(s);                                           \
+                                                                        \
+        return true;                                                    \
+    }                                                                   \
+    return false;                                                       \
+}
+
+GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 873adf4d7a6..51170625aad 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6201,3 +6201,58 @@ GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
 GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
 GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
 GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)
+
+/*
+ * Zvfwbdota16bf: BF16 Batched Dot Product with Accumulation
+ */
+void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
+                         CPURISCVState *env, uint32_t desc)
+{
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    uint32_t vta = vext_vta(desc);
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);
+    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
+    uint32_t vd_emul = vext_lmul(desc);
+    uint32_t log_esz = 2;
+    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
+    uint32_t vlmax = vlenb >> MO_16;
+    uint32_t n, k;
+    bfloat16 *a_vec, *b_vec;
+    float32 acc, dot_result;
+
+    VSTART_CHECK_EARLY_EXIT(env, vl);
+
+    a_vec = g_new0(bfloat16, vlmax);
+    b_vec = g_new0(bfloat16, vlmax);
+
+    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
+    for (n = 0; n < 8; n++) {
+        if (!vm && !vext_elem_mask(v0, ci + n)) {
+            continue;
+        }
+
+        for (k = 0; k < vl; k++) {
+            a_vec[k] = *((bfloat16 *)vs2 + n * vlmax + H2(k));
+            b_vec[k] = *((bfloat16 *)vs1 + H2(k));
+        }
+
+        dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
+                                                 &env->fp_status);
+        acc = *((float32 *)vd + H4(ci + n));
+        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(dot_result, acc,
+                                                            &env->fp_status);
+    }
+    riscv_cpu_check_fflags(env, pre_fflag);
+
+    g_free(a_vec);
+    g_free(b_vec);
+
+    env->vstart = 0;
+
+    if (ci + 8 < total_elems) {
+        if (vta_all_1s) {
+            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
+        }
+    }
+}
-- 
2.56.0

Re: [RFC PATCH 28/38] target/riscv: rvv: Implement Zvfwbdota16bf instruction

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Implement the vfwbdota.vv instruction from the Zvfwbdota16bf
> extension.
> This instruction performs a batched dot-product operation on BF16
> vectors, accumulating into FP32
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/helper.h                       |  2 +
>   target/riscv/insn32.decode                  |  3 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 52 +++++++++++++++++++
>   target/riscv/tcg/vector_helper.c            | 55 +++++++++++++++++++++
>   4 files changed, 112 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 84571a999f4..1f2dfd6d557 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1395,6 +1395,8 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>   
>   /* Zvfwdota16bf - BF16 Dot Product */
>   DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +/* Zvfwbdota16bf - BF16 Batched Dot Product */
> +DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   
>   /* Zvfqwdota8f - OCP FP8 Dot Product */
>   DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8a06547a570..00ed64b73fd 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1105,6 +1105,9 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
>   # *** Zvfwdota16bf BF16 Dot-Product Extension ***
>   vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>   
> +# *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
> +vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
> +
>   # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>   vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 650affc045b..d4678171ac5 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4365,3 +4365,55 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
>   
>   GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
>   GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
> +
> +/* Zvfwbdota16bf BF16 Batched Dot-Product Extension */
> +static bool vext_vfwbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 1;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvfwbdota16bf && s->sew == MO_16 && s->altfmt == 1);
> +}
> +
> +#define GEN_ZVBDOTA_FP_TRANS(NAME, CHECK, EEW_VD)                       \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
> +{                                                                       \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 ci, desc;                                              \
> +        uint32_t data = 0;                                              \
> +        uint32_t vlenb = s->cfg_ptr->vlenb;                             \
> +        int32_t vd_emul = MAX(0, EEW_VD + 3 - ctzl(vlenb));             \
> +                                                                        \
> +        gen_set_rm(s, RISCV_FRM_DYN);                                   \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                  \
> +        data = FIELD_DP32(data, VDATA, VMA, s->vma);                    \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                     \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));    \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        gen_helper_##NAME(dest, mask, src1, src2, ci, tcg_env, desc);   \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 873adf4d7a6..51170625aad 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6201,3 +6201,58 @@ GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
>   GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
>   GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
>   GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)
> +
> +/*
> + * Zvfwbdota16bf: BF16 Batched Dot Product with Accumulation
> + */
> +void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
> +                         CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
> +    uint32_t vd_emul = vext_lmul(desc);
> +    uint32_t log_esz = 2;
> +    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
> +    uint32_t vlmax = vlenb >> MO_16;
> +    uint32_t n, k;
> +    bfloat16 *a_vec, *b_vec;
> +    float32 acc, dot_result;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(bfloat16, vlmax);
> +    b_vec = g_new0(bfloat16, vlmax);

Same g_autofree comment from a previous patch.  With that changed:


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>


> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    for (n = 0; n < 8; n++) {
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {
> +            continue;
> +        }
> +
> +        for (k = 0; k < vl; k++) {
> +            a_vec[k] = *((bfloat16 *)vs2 + n * vlmax + H2(k));
> +            b_vec[k] = *((bfloat16 *)vs1 + H2(k));
> +        }
> +
> +        dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
> +                                                 &env->fp_status);
> +        acc = *((float32 *)vd + H4(ci + n));
> +        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(dot_result, acc,
> +                                                            &env->fp_status);
> +    }
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (ci + 8 < total_elems) {
> +        if (vta_all_1s) {
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
> +        }
> +    }
> +}

Re: [RFC PATCH 28/38] target/riscv: rvv: Implement Zvfwbdota16bf instruction

[Chao Liu]

On Thu,  5 Nov 2026 03:41:43 +0800 Max Chou <max.chou@sifive.com> wrote:

> Implement the vfwbdota.vv instruction from the Zvfwbdota16bf
> extension.
> This instruction performs a batched dot-product operation on BF16
> vectors, accumulating into FP32
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  target/riscv/helper.h                       |  2 +
>  target/riscv/insn32.decode                  |  3 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 52 +++++++++++++++++++
>  target/riscv/tcg/vector_helper.c            | 55 +++++++++++++++++++++
>  4 files changed, 112 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 84571a999f4..1f2dfd6d557 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1395,6 +1395,8 @@ DEF_HELPER_6(vqwdotas_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
>  
>  /* Zvfwdota16bf - BF16 Dot Product */
>  DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> +/* Zvfwbdota16bf - BF16 Batched Dot Product */
> +DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  
>  /* Zvfqwdota8f - OCP FP8 Dot Product */
>  DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8a06547a570..00ed64b73fd 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1105,6 +1105,9 @@ vqwdotas_vv  100111 . ..... ..... 000 ..... 1110111 @r_vm
>  # *** Zvfwdota16bf BF16 Dot-Product Extension ***
>  vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>  
> +# *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
> +vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
> +
>  # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>  vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 650affc045b..d4678171ac5 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4365,3 +4365,55 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
>  
>  GEN_ZVBDOTA_INT_TRANS(vqwbdotau_vv, vext_vqwbdota_check)
>  GEN_ZVBDOTA_INT_TRANS(vqwbdotas_vv, vext_vqwbdota_check)
> +
> +/* Zvfwbdota16bf BF16 Batched Dot-Product Extension */
> +static bool vext_vfwbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 1;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvfwbdota16bf && s->sew == MO_16 && s->altfmt == 1);
Please use s->altfmt replace `s->altfmy == 1` as well.

Otherwise, LGTM.

Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> +}
> +
> +#define GEN_ZVBDOTA_FP_TRANS(NAME, CHECK, EEW_VD)                       \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
> +{                                                                       \
> +    if (CHECK(s, a)) {                                                  \
> +        TCGv_ptr dest, src1, src2, mask;                                \
> +        TCGv_i32 ci, desc;                                              \
> +        uint32_t data = 0;                                              \
> +        uint32_t vlenb = s->cfg_ptr->vlenb;                             \
> +        int32_t vd_emul = MAX(0, EEW_VD + 3 - ctzl(vlenb));             \
> +                                                                        \
> +        gen_set_rm(s, RISCV_FRM_DYN);                                   \
> +                                                                        \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                      \
> +        data = FIELD_DP32(data, VDATA, LMUL, vd_emul);                  \
> +        data = FIELD_DP32(data, VDATA, VMA, s->vma);                    \
> +        data = FIELD_DP32(data, VDATA, VTA, s->vta);                    \
> +        data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);  \
> +                                                                        \
> +        dest = tcg_temp_new_ptr();                                      \
> +        mask = tcg_temp_new_ptr();                                      \
> +        src1 = tcg_temp_new_ptr();                                      \
> +        src2 = tcg_temp_new_ptr();                                      \
> +        desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,            \
> +                                          s->cfg_ptr->vlenb, data));    \
> +        ci = tcg_constant_i32((a->rs2 & 0x7) << 3);                     \
> +                                                                        \
> +        tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));            \
> +        tcg_gen_addi_ptr(src1, tcg_env, vreg_ofs(s, a->rs1));           \
> +        tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2 & ~0x7));    \
> +        tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));                \
> +                                                                        \
> +        gen_helper_##NAME(dest, mask, src1, src2, ci, tcg_env, desc);   \
> +                                                                        \
> +        finalize_rvv_inst(s);                                           \
> +                                                                        \
> +        return true;                                                    \
> +    }                                                                   \
> +    return false;                                                       \
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 873adf4d7a6..51170625aad 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6201,3 +6201,58 @@ GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_b, 32, 8, uint8_t, H4, H1)
>  GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_b, 32, 8, int8_t, H4, H1)
>  GEN_VEXT_ZVBDOTA_INT(vqwbdotau_vv_h, 64, 16, uint16_t, H8, H2)
>  GEN_VEXT_ZVBDOTA_INT(vqwbdotas_vv_h, 64, 16, int16_t, H8, H2)
> +
> +/*
> + * Zvfwbdota16bf: BF16 Batched Dot Product with Accumulation
> + */
> +void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
> +                         CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
> +    uint32_t vd_emul = vext_lmul(desc);
> +    uint32_t log_esz = 2;
> +    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
> +    uint32_t vlmax = vlenb >> MO_16;
> +    uint32_t n, k;
> +    bfloat16 *a_vec, *b_vec;
> +    float32 acc, dot_result;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(bfloat16, vlmax);
> +    b_vec = g_new0(bfloat16, vlmax);
> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    for (n = 0; n < 8; n++) {
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {
> +            continue;
> +        }
> +
> +        for (k = 0; k < vl; k++) {
> +            a_vec[k] = *((bfloat16 *)vs2 + n * vlmax + H2(k));
> +            b_vec[k] = *((bfloat16 *)vs1 + H2(k));
> +        }
> +
> +        dot_result = rvbna_dot_bfloat16_bfloat16(a_vec, b_vec, vlmax,
> +                                                 &env->fp_status);
> +        acc = *((float32 *)vd + H4(ci + n));
> +        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(dot_result, acc,
> +                                                            &env->fp_status);
> +    }
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (ci + 8 < total_elems) {
> +        if (vta_all_1s) {
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
> +        }
> +    }
> +}
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 29/38] disas/riscv: Support Zvfwbdota16bf extension

[Max Chou]

Adds support to disassemble Zvfwbdota16bf instructions.
- vfwbdota.vv

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 1 +
 disas/riscv.c        | 1 +
 2 files changed, 2 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index bb01ebb8a6c..b24ffb45d8e 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -608,6 +608,7 @@ OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
 OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
 OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwbdota_vv, "vfwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
 OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index 0534b8f4d64..af41c2204f5 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 36: return &op_vfwdota_vv;
                 case 38: return &op_vfqwdota_vv;
                 case 39: return &op_vfqwdota_alt_vv;
+                case 44: return &op_vfwbdota_vv;
                 }
             }
             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
-- 
2.56.0

Re: [RFC PATCH 29/38] disas/riscv: Support Zvfwbdota16bf extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support to disassemble Zvfwbdota16bf instructions.
> - vfwbdota.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 1 +
>   disas/riscv.c        | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index bb01ebb8a6c..b24ffb45d8e 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -608,6 +608,7 @@ OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>   OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>   OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwbdota_vv, "vfwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>   OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 0534b8f4d64..af41c2204f5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   case 36: return &op_vfwdota_vv;
>                   case 38: return &op_vfqwdota_vv;
>                   case 39: return &op_vfqwdota_alt_vv;
> +                case 44: return &op_vfwbdota_vv;
>                   }
>               }
>               if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {

Re: [RFC PATCH 29/38] disas/riscv: Support Zvfwbdota16bf extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:44 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support to disassemble Zvfwbdota16bf instructions.
> - vfwbdota.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 1 +
>  disas/riscv.c        | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index bb01ebb8a6c..b24ffb45d8e 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -608,6 +608,7 @@ OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>  OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>  OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwbdota_vv, "vfwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>  OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 0534b8f4d64..af41c2204f5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  case 36: return &op_vfwdota_vv;
>                  case 38: return &op_vfqwdota_vv;
>                  case 39: return &op_vfqwdota_alt_vv;
> +                case 44: return &op_vfwbdota_vv;
>                  }
>              }
>              if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 30/38] target/riscv: Add cfg property for Zvfqwbdota8f extension

[Max Chou]

Add CPU configuration property of Zvfqwbdota8f extension which depends on
the Zve32f extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 target/riscv/tcg/vector_helper.c  | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 566e2e835ae..b4a9f2c3e30 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwbdota8f, PRIV_VERSION_1_13_0,
+                                    ext_zvfqwbdota8f),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
                                     ext_zvfqwdota8f),
     ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 80750db1ccd..0385b58de0a 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_zvfqwbdota8f)
 BOOL_FIELD(ext_zvfqwdota8f)
 BOOL_FIELD(ext_zvfwbdota16bf)
 BOOL_FIELD(ext_zvfwdota16bf)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 8684e4c709c..a52637f5ca9 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -726,6 +726,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfqwbdota8f && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfqwbdota8f extension depends on Zve32f extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 51170625aad..6f3b666784e 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
     target_ulong reserved = 0;
 
     if (riscv_cpu_cfg(env)->ext_zvfbfa ||
+        riscv_cpu_cfg(env)->ext_zvfqwbdota8f ||
         riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
         riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
         riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
@@ -96,6 +97,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     switch (vsew) {
     case MO_8:
         ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
+                        cpu->cfg.ext_zvfqwbdota8f ||
                         cpu->cfg.ext_zvfqwdota8f ||
                         cpu->cfg.ext_zvqwbdota8i ||
                         cpu->cfg.ext_zvqwdota8i);
-- 
2.56.0

Re: [RFC PATCH 30/38] target/riscv: Add cfg property for Zvfqwbdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvfqwbdota8f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   target/riscv/tcg/vector_helper.c  | 2 ++
>   4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 566e2e835ae..b4a9f2c3e30 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>       ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>       ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwbdota8f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfqwbdota8f),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
>                                       ext_zvfqwdota8f),
>       ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 80750db1ccd..0385b58de0a 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
>   BOOL_FIELD(ext_zvfh)
>   BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfqwbdota8f)
>   BOOL_FIELD(ext_zvfqwdota8f)
>   BOOL_FIELD(ext_zvfwbdota16bf)
>   BOOL_FIELD(ext_zvfwdota16bf)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8684e4c709c..a52637f5ca9 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -726,6 +726,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfqwbdota8f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfqwbdota8f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 51170625aad..6f3b666784e 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>       target_ulong reserved = 0;
>   
>       if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfqwbdota8f ||
>           riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>           riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
>           riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> @@ -96,6 +97,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>       switch (vsew) {
>       case MO_8:
>           ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfqwbdota8f ||
>                           cpu->cfg.ext_zvfqwdota8f ||
>                           cpu->cfg.ext_zvqwbdota8i ||
>                           cpu->cfg.ext_zvqwdota8i);

Re: [RFC PATCH 30/38] target/riscv: Add cfg property for Zvfqwbdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:45 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvfqwbdota8f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  target/riscv/tcg/vector_helper.c  | 2 ++
>  4 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 566e2e835ae..b4a9f2c3e30 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -236,6 +236,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
>      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
>      ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwbdota8f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfqwbdota8f),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfqwdota8f, PRIV_VERSION_1_13_0,
>                                      ext_zvfqwdota8f),
>      ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfwbdota16bf, PRIV_VERSION_1_13_0,
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 80750db1ccd..0385b58de0a 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -106,6 +106,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_zvfqwbdota8f)
>  BOOL_FIELD(ext_zvfqwdota8f)
>  BOOL_FIELD(ext_zvfwbdota16bf)
>  BOOL_FIELD(ext_zvfwdota16bf)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8684e4c709c..a52637f5ca9 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -726,6 +726,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvfqwbdota8f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfqwbdota8f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 51170625aad..6f3b666784e 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -40,6 +40,7 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
>      target_ulong reserved = 0;
>  
>      if (riscv_cpu_cfg(env)->ext_zvfbfa ||
> +        riscv_cpu_cfg(env)->ext_zvfqwbdota8f ||
>          riscv_cpu_cfg(env)->ext_zvfqwdota8f ||
>          riscv_cpu_cfg(env)->ext_zvfwbdota16bf ||
>          riscv_cpu_cfg(env)->ext_zvfwdota16bf ||
> @@ -96,6 +97,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>      switch (vsew) {
>      case MO_8:
>          ill_altfmt &= !(cpu->cfg.ext_zvfbfa ||
> +                        cpu->cfg.ext_zvfqwbdota8f ||
>                          cpu->cfg.ext_zvfqwdota8f ||
>                          cpu->cfg.ext_zvqwbdota8i ||
>                          cpu->cfg.ext_zvqwdota8i);
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 31/38] target/riscv: Add implied rules for Zvfqwbdota8f extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvfqwbdota8f
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b4a9f2c3e30..0a35bc7c416 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2892,6 +2892,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvfqwbdota8f),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32f),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
     .implied_multi_exts = {
@@ -3125,6 +3134,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVFBFWMA_IMPLIED,
     &ZVFH_IMPLIED,
     &ZVFHMIN_IMPLIED,
+    &ZVFQWBDOTA8F_IMPLIED,
     &ZVFQWDOTA8F_IMPLIED,
     &ZVFWBDOTA16BF_IMPLIED,
     &ZVFWDOTA16BF_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 31/38] target/riscv: Add implied rules for Zvfqwbdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfqwbdota8f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b4a9f2c3e30..0a35bc7c416 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2892,6 +2892,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfqwbdota8f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
>       .implied_multi_exts = {
> @@ -3125,6 +3134,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVFBFWMA_IMPLIED,
>       &ZVFH_IMPLIED,
>       &ZVFHMIN_IMPLIED,
> +    &ZVFQWBDOTA8F_IMPLIED,
>       &ZVFQWDOTA8F_IMPLIED,
>       &ZVFWBDOTA16BF_IMPLIED,
>       &ZVFWDOTA16BF_IMPLIED,

Re: [RFC PATCH 31/38] target/riscv: Add implied rules for Zvfqwbdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:46 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvfqwbdota8f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b4a9f2c3e30..0a35bc7c416 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2892,6 +2892,15 @@ static RISCVCPUImpliedExtsRule ZVFQWDOTA8F_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfqwbdota8f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
>      .implied_multi_exts = {
> @@ -3125,6 +3134,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVFBFWMA_IMPLIED,
>      &ZVFH_IMPLIED,
>      &ZVFHMIN_IMPLIED,
> +    &ZVFQWBDOTA8F_IMPLIED,
>      &ZVFQWDOTA8F_IMPLIED,
>      &ZVFWBDOTA16BF_IMPLIED,
>      &ZVFWDOTA16BF_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 32/38] target/riscv: rvv: Implement Zvfqwbdota8f instructions

[Max Chou]

Support the Zvfqwbdota8f OCP FP8 batched dot-product instructions.
These instructions perform 8 parallel dot products between OCP FP8 vectors,
accumulating into FP32 elements.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  4 ++
 target/riscv/insn32.decode                  |  4 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 13 ++++
 target/riscv/tcg/vector_helper.c            | 69 +++++++++++++++++++++
 4 files changed, 90 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1f2dfd6d557..a257436fb31 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1398,6 +1398,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 /* Zvfwbdota16bf - BF16 Batched Dot Product */
 DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
 
+/* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
+DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
+DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
+
 /* Zvfqwdota8f - OCP FP8 Dot Product */
 DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 00ed64b73fd..48597915f7b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1108,6 +1108,10 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
 # *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
 vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
 
+# *** Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension ***
+vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
+vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
+
 # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
 vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index d4678171ac5..50f0f67ea60 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4417,3 +4417,16 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
 }
 
 GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
+
+/* Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension */
+static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
+{
+    int32_t sew = s->sew;
+    int32_t vd_eew = sew + 2;
+    return s->mstatus_fs != EXT_STATUS_DISABLED &&
+           vext_zvbdota_base_check(s, a, vd_eew) &&
+           (s->cfg_ptr->ext_zvfqwbdota8f && sew == MO_8);
+}
+
+GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
+GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 6f3b666784e..e641e21d088 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6258,3 +6258,72 @@ void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
         }
     }
 }
+
+/*
+ * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
+ */
+#define GEN_VEXT_ZVBDOTA_FP8(NAME, TYPE_VS2)                             \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
+                  uint32_t ci, CPURISCVState *env, uint32_t desc)        \
+{                                                                        \
+    uint32_t vm = vext_vm(desc);                                         \
+    uint32_t vl = env->vl;                                               \
+    uint32_t vta = vext_vta(desc);                                       \
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
+    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                          \
+    uint32_t vd_emul = vext_lmul(desc);                                  \
+    uint32_t total_elems = (vlenb << vd_emul) >> 2;                      \
+    uint32_t vlmax = vlenb;                                              \
+    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
+    uint32_t n, k;                                                       \
+    uint8_t *a_vec, *b_vec;                                              \
+    float32 acc, dot_result;                                             \
+                                                                         \
+    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
+                                                                         \
+    a_vec = g_new0(uint8_t, vlmax);                                      \
+    b_vec = g_new0(uint8_t, vlmax);                                      \
+                                                                         \
+    FloatExceptionFlags pre_fflag =                                      \
+        get_float_exception_flags(&env->fp_status);                      \
+    for (n = 0; n < 8; n++) {                                            \
+        if (!vm && !vext_elem_mask(v0, ci + n)) {                        \
+            continue;                                                    \
+        }                                                                \
+                                                                         \
+        for (k = 0; k < vl; k++) {                                       \
+            a_vec[k] = *((uint8_t *)vs2 + n * vlmax + H1(k));            \
+            b_vec[k] = *((uint8_t *)vs1 + H1(k));                        \
+        }                                                                \
+                                                                         \
+        FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);    \
+        set_snan_rule(float_snan_never, &env->fp_status);                \
+        if (altfmt == 0) {                                               \
+            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(      \
+                    a_vec, b_vec, vlmax, &env->fp_status);               \
+        } else {                                                         \
+            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(      \
+                    a_vec, b_vec, vlmax, &env->fp_status);               \
+        }                                                                \
+        set_snan_rule(pre_snan_rule, &env->fp_status);                   \
+                                                                         \
+        acc = *((float32 *)vd + H4(ci + n));                             \
+        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(             \
+                dot_result, acc, &env->fp_status);                       \
+    }                                                                    \
+    riscv_cpu_check_fflags(env, pre_fflag);                              \
+                                                                         \
+    g_free(a_vec);                                                       \
+    g_free(b_vec);                                                       \
+                                                                         \
+    env->vstart = 0;                                                     \
+                                                                         \
+    if (ci + 8 < total_elems) {                                          \
+        if (vta_all_1s) {                                                \
+            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);   \
+        }                                                                \
+    }                                                                    \
+}
+
+GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
+GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)
-- 
2.56.0

Re: [RFC PATCH 32/38] target/riscv: rvv: Implement Zvfqwbdota8f instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Support the Zvfqwbdota8f OCP FP8 batched dot-product instructions.
> These instructions perform 8 parallel dot products between OCP FP8 vectors,
> accumulating into FP32 elements.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/helper.h                       |  4 ++
>   target/riscv/insn32.decode                  |  4 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 13 ++++
>   target/riscv/tcg/vector_helper.c            | 69 +++++++++++++++++++++
>   4 files changed, 90 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1f2dfd6d557..a257436fb31 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1398,6 +1398,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   /* Zvfwbdota16bf - BF16 Batched Dot Product */
>   DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   
> +/* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
> +DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>   /* Zvfqwdota8f - OCP FP8 Dot Product */
>   DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 00ed64b73fd..48597915f7b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1108,6 +1108,10 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>   # *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
>   vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
>   
> +# *** Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension ***
> +vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
> +vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
> +
>   # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>   vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index d4678171ac5..50f0f67ea60 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4417,3 +4417,16 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
>   }
>   
>   GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
> +
> +/* Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension */
> +static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 2;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvfqwbdota8f && sew == MO_8);
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
> +GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6f3b666784e..e641e21d088 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6258,3 +6258,72 @@ void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
>           }
>       }
>   }
> +
> +/*
> + * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVBDOTA_FP8(NAME, TYPE_VS2)                             \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
> +                  uint32_t ci, CPURISCVState *env, uint32_t desc)        \
> +{                                                                        \
> +    uint32_t vm = vext_vm(desc);                                         \
> +    uint32_t vl = env->vl;                                               \
> +    uint32_t vta = vext_vta(desc);                                       \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                          \
> +    uint32_t vd_emul = vext_lmul(desc);                                  \
> +    uint32_t total_elems = (vlenb << vd_emul) >> 2;                      \
> +    uint32_t vlmax = vlenb;                                              \
> +    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
> +    uint32_t n, k;                                                       \
> +    uint8_t *a_vec, *b_vec;                                              \
> +    float32 acc, dot_result;                                             \
> +                                                                         \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
> +                                                                         \
> +    a_vec = g_new0(uint8_t, vlmax);                                      \
> +    b_vec = g_new0(uint8_t, vlmax);                                      \
> +                                                                         \
> +    FloatExceptionFlags pre_fflag =                                      \
> +        get_float_exception_flags(&env->fp_status);                      \
> +    for (n = 0; n < 8; n++) {                                            \
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {                        \
> +            continue;                                                    \
> +        }                                                                \
> +                                                                         \
> +        for (k = 0; k < vl; k++) {                                       \
> +            a_vec[k] = *((uint8_t *)vs2 + n * vlmax + H1(k));            \
> +            b_vec[k] = *((uint8_t *)vs1 + H1(k));                        \
> +        }                                                                \
> +                                                                         \
> +        FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);    \
> +        set_snan_rule(float_snan_never, &env->fp_status);                \
> +        if (altfmt == 0) {                                               \
> +            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(      \
> +                    a_vec, b_vec, vlmax, &env->fp_status);               \
> +        } else {                                                         \
> +            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(      \
> +                    a_vec, b_vec, vlmax, &env->fp_status);               \
> +        }                                                                \
> +        set_snan_rule(pre_snan_rule, &env->fp_status);                   \
> +                                                                         \
> +        acc = *((float32 *)vd + H4(ci + n));                             \
> +        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(             \
> +                dot_result, acc, &env->fp_status);                       \
> +    }                                                                    \
> +    riscv_cpu_check_fflags(env, pre_fflag);                              \
> +                                                                         \
> +    g_free(a_vec);                                                       \
> +    g_free(b_vec);                                                       \
> +                                                                         \
> +    env->vstart = 0;                                                     \
> +                                                                         \
> +    if (ci + 8 < total_elems) {                                          \
> +        if (vta_all_1s) {                                                \
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);   \
> +        }                                                                \
> +    }                                                                    \
> +}
> +
> +GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
> +GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)

Re: [RFC PATCH 32/38] target/riscv: rvv: Implement Zvfqwbdota8f instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:47 +0800 Max Chou <max.chou@sifive.com> wrote:

> Support the Zvfqwbdota8f OCP FP8 batched dot-product instructions.
> These instructions perform 8 parallel dot products between OCP FP8 vectors,
> accumulating into FP32 elements.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/helper.h                       |  4 ++
>  target/riscv/insn32.decode                  |  4 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 13 ++++
>  target/riscv/tcg/vector_helper.c            | 69 +++++++++++++++++++++
>  4 files changed, 90 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1f2dfd6d557..a257436fb31 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1398,6 +1398,10 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  /* Zvfwbdota16bf - BF16 Batched Dot Product */
>  DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  
> +/* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
> +DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>  /* Zvfqwdota8f - OCP FP8 Dot Product */
>  DEF_HELPER_6(vfqwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  DEF_HELPER_6(vfqwdota_alt_vv, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 00ed64b73fd..48597915f7b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1108,6 +1108,10 @@ vfwdota_vv  100100 . ..... ..... 001 ..... 1110111 @r_vm
>  # *** Zvfwbdota16bf BF16 Batched Dot-Product Extension ***
>  vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
>  
> +# *** Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension ***
> +vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
> +vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
> +
>  # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>  vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index d4678171ac5..50f0f67ea60 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4417,3 +4417,16 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr * a)                 \
>  }
>  
>  GEN_ZVBDOTA_FP_TRANS(vfwbdota_vv, vext_vfwbdota_check, MO_32)
> +
> +/* Zvfqwbdota8f OCP FP8 Batched Dot-Product Extension */
> +static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    int32_t vd_eew = sew + 2;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, vd_eew) &&
> +           (s->cfg_ptr->ext_zvfqwbdota8f && sew == MO_8);
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
> +GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 6f3b666784e..e641e21d088 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6258,3 +6258,72 @@ void HELPER(vfwbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
>          }
>      }
>  }
> +
> +/*
> + * Zvfqwdota8f: OCP FP8 Dot Product with Accumulation
> + */
> +#define GEN_VEXT_ZVBDOTA_FP8(NAME, TYPE_VS2)                             \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
> +                  uint32_t ci, CPURISCVState *env, uint32_t desc)        \
> +{                                                                        \
> +    uint32_t vm = vext_vm(desc);                                         \
> +    uint32_t vl = env->vl;                                               \
> +    uint32_t vta = vext_vta(desc);                                       \
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);                         \
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;                          \
> +    uint32_t vd_emul = vext_lmul(desc);                                  \
> +    uint32_t total_elems = (vlenb << vd_emul) >> 2;                      \
> +    uint32_t vlmax = vlenb;                                              \
> +    uint32_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);             \
> +    uint32_t n, k;                                                       \
> +    uint8_t *a_vec, *b_vec;                                              \
> +    float32 acc, dot_result;                                             \
> +                                                                         \
> +    VSTART_CHECK_EARLY_EXIT(env, vl);                                    \
> +                                                                         \
> +    a_vec = g_new0(uint8_t, vlmax);                                      \
> +    b_vec = g_new0(uint8_t, vlmax);                                      \
> +                                                                         \
> +    FloatExceptionFlags pre_fflag =                                      \
> +        get_float_exception_flags(&env->fp_status);                      \
> +    for (n = 0; n < 8; n++) {                                            \
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {                        \
> +            continue;                                                    \
> +        }                                                                \
> +                                                                         \
> +        for (k = 0; k < vl; k++) {                                       \
> +            a_vec[k] = *((uint8_t *)vs2 + n * vlmax + H1(k));            \
> +            b_vec[k] = *((uint8_t *)vs1 + H1(k));                        \
> +        }                                                                \
> +                                                                         \
> +        FloatSNaNRule pre_snan_rule = get_snan_rule(&env->fp_status);    \
> +        set_snan_rule(float_snan_never, &env->fp_status);                \
> +        if (altfmt == 0) {                                               \
> +            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e4m3(      \
> +                    a_vec, b_vec, vlmax, &env->fp_status);               \
> +        } else {                                                         \
> +            dot_result = rvbna_dot_float8_##TYPE_VS2##_float8_e5m2(      \
> +                    a_vec, b_vec, vlmax, &env->fp_status);               \
> +        }                                                                \
> +        set_snan_rule(pre_snan_rule, &env->fp_status);                   \
> +                                                                         \
> +        acc = *((float32 *)vd + H4(ci + n));                             \
> +        *((float32 *)vd + H4(ci + n)) = rvbna_final_f32_add(             \
> +                dot_result, acc, &env->fp_status);                       \
> +    }                                                                    \
> +    riscv_cpu_check_fflags(env, pre_fflag);                              \
> +                                                                         \
> +    g_free(a_vec);                                                       \
> +    g_free(b_vec);                                                       \
> +                                                                         \
> +    env->vstart = 0;                                                     \
> +                                                                         \
> +    if (ci + 8 < total_elems) {                                          \
> +        if (vta_all_1s) {                                                \
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);   \
> +        }                                                                \
> +    }                                                                    \
> +}
> +
> +GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
> +GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 33/38] disas/riscv: Support Zvfqwbdota8f extension

[Max Chou]

Adds support to disassemble Zvfqwbdota8f instructions.
- vfqwbdota.vv
- vfqwbdota.alt.vv

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 3 +++
 disas/riscv.c        | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index b24ffb45d8e..58f6ddac35a 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -583,6 +583,9 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
 OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
 OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
 OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfqwbdota_alt_vv, "vfqwbdota.alt.vv", rv_codec_v_r_ci,
+   rv_fmt_vd_vs2_vs1_ci_vm)
+OP(vfqwbdota_vv, "vfqwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
 OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index af41c2204f5..a124cbb4bbe 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2648,6 +2648,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 38: return &op_vfqwdota_vv;
                 case 39: return &op_vfqwdota_alt_vv;
                 case 44: return &op_vfwbdota_vv;
+                case 46: return &op_vfqwbdota_vv;
+                case 47: return &op_vfqwbdota_alt_vv;
                 }
             }
             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
-- 
2.56.0

Re: [RFC PATCH 33/38] disas/riscv: Support Zvfqwbdota8f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support to disassemble Zvfqwbdota8f instructions.
> - vfqwbdota.vv
> - vfqwbdota.alt.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 3 +++
>   disas/riscv.c        | 2 ++
>   2 files changed, 5 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index b24ffb45d8e..58f6ddac35a 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -583,6 +583,9 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>   OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>   OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>   OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfqwbdota_alt_vv, "vfqwbdota.alt.vv", rv_codec_v_r_ci,
> +   rv_fmt_vd_vs2_vs1_ci_vm)
> +OP(vfqwbdota_vv, "vfqwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>   OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index af41c2204f5..a124cbb4bbe 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2648,6 +2648,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   case 38: return &op_vfqwdota_vv;
>                   case 39: return &op_vfqwdota_alt_vv;
>                   case 44: return &op_vfwbdota_vv;
> +                case 46: return &op_vfqwbdota_vv;
> +                case 47: return &op_vfqwbdota_alt_vv;
>                   }
>               }
>               if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {

Re: [RFC PATCH 33/38] disas/riscv: Support Zvfqwbdota8f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:48 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support to disassemble Zvfqwbdota8f instructions.
> - vfqwbdota.vv
> - vfqwbdota.alt.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 3 +++
>  disas/riscv.c        | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index b24ffb45d8e..58f6ddac35a 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -583,6 +583,9 @@ OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>  OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
>  OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
>  OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfqwbdota_alt_vv, "vfqwbdota.alt.vv", rv_codec_v_r_ci,
> +   rv_fmt_vd_vs2_vs1_ci_vm)
> +OP(vfqwbdota_vv, "vfqwbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>  OP(vfqwdota_alt_vv, "vfqwdota.alt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vfqwdota_vv, "vfqwdota.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index af41c2204f5..a124cbb4bbe 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2648,6 +2648,8 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  case 38: return &op_vfqwdota_vv;
>                  case 39: return &op_vfqwdota_alt_vv;
>                  case 44: return &op_vfwbdota_vv;
> +                case 46: return &op_vfqwbdota_vv;
> +                case 47: return &op_vfqwbdota_alt_vv;
>                  }
>              }
>              if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 34/38] target/riscv: Add cfg property for Zvfbdota32f extension

[Max Chou]

Add CPU configuration property of Zvfbdota32f extension which depends on
the Zve32f extension per the specification.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c                | 2 ++
 target/riscv/cpu_cfg_fields.h.inc | 1 +
 target/riscv/tcg/tcg-cpu.c        | 5 +++++
 3 files changed, 8 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0a35bc7c416..ed0f5ed976a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -231,6 +231,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
+    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfbdota32f, PRIV_VERSION_1_13_0,
+                                    ext_zvfbdota32f),
     ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 0385b58de0a..d85dd2cfd53 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -101,6 +101,7 @@ BOOL_FIELD(ext_zvks)
 BOOL_FIELD(ext_zvksc)
 BOOL_FIELD(ext_zvksg)
 BOOL_FIELD(ext_zmmul)
+BOOL_FIELD(ext_zvfbdota32f)
 BOOL_FIELD(ext_zvfbfa)
 BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a52637f5ca9..32b6f9894fc 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -731,6 +731,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfbdota32f && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfbdota32f extension depends on Zve32f extension");
+        return;
+    }
+
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
         return;
-- 
2.56.0

Re: [RFC PATCH 34/38] target/riscv: Add cfg property for Zvfbdota32f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add CPU configuration property of Zvfbdota32f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c                | 2 ++
>   target/riscv/cpu_cfg_fields.h.inc | 1 +
>   target/riscv/tcg/tcg-cpu.c        | 5 +++++
>   3 files changed, 8 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0a35bc7c416..ed0f5ed976a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -231,6 +231,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
>       ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
>       ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfbdota32f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfbdota32f),
>       ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),
>       ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
>       ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 0385b58de0a..d85dd2cfd53 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -101,6 +101,7 @@ BOOL_FIELD(ext_zvks)
>   BOOL_FIELD(ext_zvksc)
>   BOOL_FIELD(ext_zvksg)
>   BOOL_FIELD(ext_zmmul)
> +BOOL_FIELD(ext_zvfbdota32f)
>   BOOL_FIELD(ext_zvfbfa)
>   BOOL_FIELD(ext_zvfbfmin)
>   BOOL_FIELD(ext_zvfbfwma)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a52637f5ca9..32b6f9894fc 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -731,6 +731,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfbdota32f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfbdota32f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>       if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>           error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>           return;

Re: [RFC PATCH 34/38] target/riscv: Add cfg property for Zvfbdota32f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:49 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add CPU configuration property of Zvfbdota32f extension which depends on
> the Zve32f extension per the specification.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c                | 2 ++
>  target/riscv/cpu_cfg_fields.h.inc | 1 +
>  target/riscv/tcg/tcg-cpu.c        | 5 +++++
>  3 files changed, 8 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0a35bc7c416..ed0f5ed976a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -231,6 +231,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
>      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
>      ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
> +    ISA_EXPERIMENTAL_EXT_DATA_ENTRY(zvfbdota32f, PRIV_VERSION_1_13_0,
> +                                    ext_zvfbdota32f),
>      ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),
>      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
>      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 0385b58de0a..d85dd2cfd53 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -101,6 +101,7 @@ BOOL_FIELD(ext_zvks)
>  BOOL_FIELD(ext_zvksc)
>  BOOL_FIELD(ext_zvksg)
>  BOOL_FIELD(ext_zmmul)
> +BOOL_FIELD(ext_zvfbdota32f)
>  BOOL_FIELD(ext_zvfbfa)
>  BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a52637f5ca9..32b6f9894fc 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -731,6 +731,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>  
> +    if (cpu->cfg.ext_zvfbdota32f && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfbdota32f extension depends on Zve32f extension");
> +        return;
> +    }
> +
>      if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
>          error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
>          return;
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 35/38] target/riscv: Add implied rules for Zvfbdota32f extension

[Max Chou]

Add implied rules to enable the implied extensions of Zvfbdota32f
extension recursively.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ed0f5ed976a..ff09bafe667 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2903,6 +2903,15 @@ static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule ZVFBDOTA32F_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_zvfbdota32f),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32f),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
     .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
     .implied_multi_exts = {
@@ -3131,6 +3140,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVE64D_IMPLIED,
     &ZVE64F_IMPLIED,
     &ZVE64X_IMPLIED,
+    &ZVFBDOTA32F_IMPLIED,
     &ZVFBFA_IMPLIED,
     &ZVFBFMIN_IMPLIED,
     &ZVFBFWMA_IMPLIED,
-- 
2.56.0

Re: [RFC PATCH 35/38] target/riscv: Add implied rules for Zvfbdota32f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add implied rules to enable the implied extensions of Zvfbdota32f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/cpu.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ed0f5ed976a..ff09bafe667 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2903,6 +2903,15 @@ static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule ZVFBDOTA32F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfbdota32f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
>       .implied_multi_exts = {
> @@ -3131,6 +3140,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>       &ZVE64D_IMPLIED,
>       &ZVE64F_IMPLIED,
>       &ZVE64X_IMPLIED,
> +    &ZVFBDOTA32F_IMPLIED,
>       &ZVFBFA_IMPLIED,
>       &ZVFBFMIN_IMPLIED,
>       &ZVFBFWMA_IMPLIED,

Re: [RFC PATCH 35/38] target/riscv: Add implied rules for Zvfbdota32f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:50 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add implied rules to enable the implied extensions of Zvfbdota32f
> extension recursively.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ed0f5ed976a..ff09bafe667 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2903,6 +2903,15 @@ static RISCVCPUImpliedExtsRule ZVFQWBDOTA8F_IMPLIED = {
>      },
>  };
>  
> +static RISCVCPUImpliedExtsRule ZVFBDOTA32F_IMPLIED = {
> +    .ext = CPU_CFG_OFFSET(ext_zvfbdota32f),
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zve32f),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZVFWBDOTA16BF_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zvfwbdota16bf),
>      .implied_multi_exts = {
> @@ -3131,6 +3140,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
>      &ZVE64D_IMPLIED,
>      &ZVE64F_IMPLIED,
>      &ZVE64X_IMPLIED,
> +    &ZVFBDOTA32F_IMPLIED,
>      &ZVFBFA_IMPLIED,
>      &ZVFBFMIN_IMPLIED,
>      &ZVFBFWMA_IMPLIED,
> -- 
> 2.56.0
> 
> 
> 

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[RFC PATCH 36/38] target/riscv: rvv: Implement Zvfbdota32f instructions

[Max Chou]

Add support for the Zvfbdota32f FP32 batched dot-product instruction.
The vfbdota.vv instruction performs 8 parallel dot products between
FP32 vectors, accumulating into FP32 elements.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/helper.h                       |  3 ++
 target/riscv/insn32.decode                  |  3 ++
 target/riscv/tcg/insn_trans/trans_rvv.c.inc | 11 ++++
 target/riscv/tcg/vector_helper.c            | 58 +++++++++++++++++++++
 4 files changed, 75 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a257436fb31..94f4d9c40c6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1398,6 +1398,9 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
 /* Zvfwbdota16bf - BF16 Batched Dot Product */
 DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
 
+/* Zvfbdota32f - FP32 Batched Dot Product */
+DEF_HELPER_7(vfbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
+
 /* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
 DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
 DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 48597915f7b..7fdb7eb54da 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1112,6 +1112,9 @@ vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
 
+# *** Zvfbdota32f FP32 Batched Dot-Product Extension ***
+vfbdota_vv  101011 . ..... ..... 001 ..... 1110111 @r_vm
+
 # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
 vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
 vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index 50f0f67ea60..9b06c6a782c 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -4430,3 +4430,14 @@ static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
 
 GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
 GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
+
+/* Zvfbdota32f FP32 Batched Dot-Product Extension */
+static bool vext_vfbdota_check(DisasContext *s, arg_rmrr * a)
+{
+    int32_t sew = s->sew;
+    return s->mstatus_fs != EXT_STATUS_DISABLED &&
+           vext_zvbdota_base_check(s, a, sew) &&
+           (s->cfg_ptr->ext_zvfbdota32f && sew == MO_32);
+}
+
+GEN_ZVBDOTA_FP_TRANS(vfbdota_vv, vext_vfbdota_check, MO_32)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index e641e21d088..7d680747ddd 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -6327,3 +6327,61 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
 
 GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
 GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)
+
+/*
+ * Zvfbdota32f: FP32 Batched Dot Product with Accumulation
+ */
+void HELPER(vfbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
+                        CPURISCVState *env, uint32_t desc)
+{
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    uint32_t vta = vext_vta(desc);
+    uint32_t vta_all_1s = vext_vta_all_1s(desc);
+    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
+    uint32_t vd_emul = vext_lmul(desc);
+    uint32_t log_esz = 2;
+    uint32_t vlmax = vlenb >> MO_32;
+    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
+    uint32_t n, k;
+    float32 *a_vec, *b_vec;
+    float32 acc, prod, a, b;
+
+    VSTART_CHECK_EARLY_EXIT(env, vl);
+
+    a_vec = g_new0(float32, vlmax);
+    b_vec = g_new0(float32, vlmax);
+
+    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
+    for (n = 0; n < 8; n++) {
+        if (!vm && !vext_elem_mask(v0, ci + n)) {
+            continue;
+        }
+
+        for (k = 0; k < vl; k++) {
+            a_vec[k] = *((float32 *)vs2 + n * vlmax + H4(k));
+            b_vec[k] = *((float32 *)vs1 + H4(k));
+        }
+
+        acc = *((float32 *)vd + H4(ci + n));
+        for (k = 0; k < vlmax; k++) {
+            a = a_vec[k];
+            b = b_vec[k];
+            prod = float32_mul(a, b, &env->fp_status);
+            acc = float32_add(acc, prod, &env->fp_status);
+        }
+        *((float32 *)vd + H4(ci + n)) = acc;
+    }
+    riscv_cpu_check_fflags(env, pre_fflag);
+
+    g_free(a_vec);
+    g_free(b_vec);
+
+    env->vstart = 0;
+
+    if (ci + 8 < total_elems) {
+        if (vta_all_1s) {
+            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
+        }
+    }
+}
-- 
2.56.0

Re: [RFC PATCH 36/38] target/riscv: rvv: Implement Zvfbdota32f instructions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add support for the Zvfbdota32f FP32 batched dot-product instruction.
> The vfbdota.vv instruction performs 8 parallel dot products between
> FP32 vectors, accumulating into FP32 elements.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/helper.h                       |  3 ++
>   target/riscv/insn32.decode                  |  3 ++
>   target/riscv/tcg/insn_trans/trans_rvv.c.inc | 11 ++++
>   target/riscv/tcg/vector_helper.c            | 58 +++++++++++++++++++++
>   4 files changed, 75 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index a257436fb31..94f4d9c40c6 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1398,6 +1398,9 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>   /* Zvfwbdota16bf - BF16 Batched Dot Product */
>   DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   
> +/* Zvfbdota32f - FP32 Batched Dot Product */
> +DEF_HELPER_7(vfbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>   /* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
>   DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>   DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 48597915f7b..7fdb7eb54da 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1112,6 +1112,9 @@ vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
>   
> +# *** Zvfbdota32f FP32 Batched Dot-Product Extension ***
> +vfbdota_vv  101011 . ..... ..... 001 ..... 1110111 @r_vm
> +
>   # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>   vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>   vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 50f0f67ea60..9b06c6a782c 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4430,3 +4430,14 @@ static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
>   
>   GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
>   GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
> +
> +/* Zvfbdota32f FP32 Batched Dot-Product Extension */
> +static bool vext_vfbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, sew) &&
> +           (s->cfg_ptr->ext_zvfbdota32f && sew == MO_32);
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfbdota_vv, vext_vfbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index e641e21d088..7d680747ddd 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6327,3 +6327,61 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
>   
>   GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
>   GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)
> +
> +/*
> + * Zvfbdota32f: FP32 Batched Dot Product with Accumulation
> + */
> +void HELPER(vfbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
> +                        CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
> +    uint32_t vd_emul = vext_lmul(desc);
> +    uint32_t log_esz = 2;
> +    uint32_t vlmax = vlenb >> MO_32;
> +    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
> +    uint32_t n, k;
> +    float32 *a_vec, *b_vec;
> +    float32 acc, prod, a, b;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(float32, vlmax);
> +    b_vec = g_new0(float32, vlmax);

Same g_autofree comment from previous patches.  With this changed:


Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    for (n = 0; n < 8; n++) {
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {
> +            continue;
> +        }
> +
> +        for (k = 0; k < vl; k++) {
> +            a_vec[k] = *((float32 *)vs2 + n * vlmax + H4(k));
> +            b_vec[k] = *((float32 *)vs1 + H4(k));
> +        }
> +
> +        acc = *((float32 *)vd + H4(ci + n));
> +        for (k = 0; k < vlmax; k++) {
> +            a = a_vec[k];
> +            b = b_vec[k];
> +            prod = float32_mul(a, b, &env->fp_status);
> +            acc = float32_add(acc, prod, &env->fp_status);
> +        }
> +        *((float32 *)vd + H4(ci + n)) = acc;
> +    }
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (ci + 8 < total_elems) {
> +        if (vta_all_1s) {
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
> +        }
> +    }
> +}

Re: [RFC PATCH 36/38] target/riscv: rvv: Implement Zvfbdota32f instructions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:51 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add support for the Zvfbdota32f FP32 batched dot-product instruction.
> The vfbdota.vv instruction performs 8 parallel dot products between
> FP32 vectors, accumulating into FP32 elements.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>  target/riscv/helper.h                       |  3 ++
>  target/riscv/insn32.decode                  |  3 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 11 ++++
>  target/riscv/tcg/vector_helper.c            | 58 +++++++++++++++++++++
>  4 files changed, 75 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index a257436fb31..94f4d9c40c6 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1398,6 +1398,9 @@ DEF_HELPER_6(vfwdota_vv, void, ptr, ptr, ptr, ptr, env, i32)
>  /* Zvfwbdota16bf - BF16 Batched Dot Product */
>  DEF_HELPER_7(vfwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  
> +/* Zvfbdota32f - FP32 Batched Dot Product */
> +DEF_HELPER_7(vfbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> +
>  /* Zvfqwbdota8f - OCP FP8 Batched Dot Product */
>  DEF_HELPER_7(vfqwbdota_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
>  DEF_HELPER_7(vfqwbdota_alt_vv, void, ptr, ptr, ptr, ptr, i32, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 48597915f7b..7fdb7eb54da 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1112,6 +1112,9 @@ vfwbdota_vv 101100 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwbdota_vv     101110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwbdota_alt_vv 101111 . ..... ..... 001 ..... 1110111 @r_vm
>  
> +# *** Zvfbdota32f FP32 Batched Dot-Product Extension ***
> +vfbdota_vv  101011 . ..... ..... 001 ..... 1110111 @r_vm
> +
>  # *** Zvfqwdota8f OCP FP8 Dot-Product Extension ***
>  vfqwdota_vv     100110 . ..... ..... 001 ..... 1110111 @r_vm
>  vfqwdota_alt_vv 100111 . ..... ..... 001 ..... 1110111 @r_vm
> diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> index 50f0f67ea60..9b06c6a782c 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
> @@ -4430,3 +4430,14 @@ static bool vext_vfqwbdota_check(DisasContext *s, arg_rmrr * a)
>  
>  GEN_ZVBDOTA_FP_TRANS(vfqwbdota_vv, vext_vfqwbdota_check, MO_32)
>  GEN_ZVBDOTA_FP_TRANS(vfqwbdota_alt_vv, vext_vfqwbdota_check, MO_32)
> +
> +/* Zvfbdota32f FP32 Batched Dot-Product Extension */
> +static bool vext_vfbdota_check(DisasContext *s, arg_rmrr * a)
> +{
> +    int32_t sew = s->sew;
> +    return s->mstatus_fs != EXT_STATUS_DISABLED &&
> +           vext_zvbdota_base_check(s, a, sew) &&
> +           (s->cfg_ptr->ext_zvfbdota32f && sew == MO_32);
> +}
> +
> +GEN_ZVBDOTA_FP_TRANS(vfbdota_vv, vext_vfbdota_check, MO_32)
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index e641e21d088..7d680747ddd 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -6327,3 +6327,61 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,              \
>  
>  GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_vv, e4m3)
>  GEN_VEXT_ZVBDOTA_FP8(vfqwbdota_alt_vv, e5m2)
> +
> +/*
> + * Zvfbdota32f: FP32 Batched Dot Product with Accumulation
> + */
> +void HELPER(vfbdota_vv)(void *vd, void *v0, void *vs1, void *vs2, uint32_t ci,
> +                        CPURISCVState *env, uint32_t desc)
> +{
> +    uint32_t vm = vext_vm(desc);
> +    uint32_t vl = env->vl;
> +    uint32_t vta = vext_vta(desc);
> +    uint32_t vta_all_1s = vext_vta_all_1s(desc);
> +    uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
> +    uint32_t vd_emul = vext_lmul(desc);
> +    uint32_t log_esz = 2;
> +    uint32_t vlmax = vlenb >> MO_32;
> +    uint32_t total_elems = (vlenb << vd_emul) >> log_esz;
> +    uint32_t n, k;
> +    float32 *a_vec, *b_vec;
Please use g_autofree for these arrays as well.

Otherwise, LGTM.

Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> +    float32 acc, prod, a, b;
> +
> +    VSTART_CHECK_EARLY_EXIT(env, vl);
> +
> +    a_vec = g_new0(float32, vlmax);
> +    b_vec = g_new0(float32, vlmax);
> +
> +    FloatExceptionFlags pre_fflag = get_float_exception_flags(&env->fp_status);
> +    for (n = 0; n < 8; n++) {
> +        if (!vm && !vext_elem_mask(v0, ci + n)) {
> +            continue;
> +        }
> +
> +        for (k = 0; k < vl; k++) {
> +            a_vec[k] = *((float32 *)vs2 + n * vlmax + H4(k));
> +            b_vec[k] = *((float32 *)vs1 + H4(k));
> +        }
> +
> +        acc = *((float32 *)vd + H4(ci + n));
> +        for (k = 0; k < vlmax; k++) {
> +            a = a_vec[k];
> +            b = b_vec[k];
> +            prod = float32_mul(a, b, &env->fp_status);
> +            acc = float32_add(acc, prod, &env->fp_status);
> +        }
> +        *((float32 *)vd + H4(ci + n)) = acc;
> +    }
> +    riscv_cpu_check_fflags(env, pre_fflag);
> +
> +    g_free(a_vec);
> +    g_free(b_vec);
> +
> +    env->vstart = 0;
> +
> +    if (ci + 8 < total_elems) {
> +        if (vta_all_1s) {
> +            vext_set_elems_1s(vd, vta, (ci + 8) * 4, total_elems * 4);
> +        }
> +    }
> +}
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 37/38] disas/riscv: Support Zvfbdota32f extension

[Max Chou]

Adds support to disassemble Zvfbdota32f instructions.
- vfbdota.vv

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv-op.c.inc | 1 +
 disas/riscv.c        | 1 +
 2 files changed, 2 insertions(+)

diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 58f6ddac35a..779fc26a27c 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -538,6 +538,7 @@ OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
 OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
 OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
 OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfbdota_vv, "vfbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
 OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
 OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
diff --git a/disas/riscv.c b/disas/riscv.c
index a124cbb4bbe..8330ba34a30 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 36: return &op_vfwdota_vv;
                 case 38: return &op_vfqwdota_vv;
                 case 39: return &op_vfqwdota_alt_vv;
+                case 43: return &op_vfbdota_vv;
                 case 44: return &op_vfwbdota_vv;
                 case 46: return &op_vfqwbdota_vv;
                 case 47: return &op_vfqwbdota_alt_vv;
-- 
2.56.0

Re: [RFC PATCH 37/38] disas/riscv: Support Zvfbdota32f extension

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Adds support to disassemble Zvfbdota32f instructions.
> - vfbdota.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   disas/riscv-op.c.inc | 1 +
>   disas/riscv.c        | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 58f6ddac35a..779fc26a27c 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -538,6 +538,7 @@ OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>   OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>   OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>   OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfbdota_vv, "vfbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>   OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>   OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a124cbb4bbe..8330ba34a30 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                   case 36: return &op_vfwdota_vv;
>                   case 38: return &op_vfqwdota_vv;
>                   case 39: return &op_vfqwdota_alt_vv;
> +                case 43: return &op_vfbdota_vv;
>                   case 44: return &op_vfwbdota_vv;
>                   case 46: return &op_vfqwbdota_vv;
>                   case 47: return &op_vfqwbdota_alt_vv;

Re: [RFC PATCH 37/38] disas/riscv: Support Zvfbdota32f extension

[Chao Liu]

On Thu,  5 Nov 2026 03:41:52 +0800 Max Chou <max.chou@sifive.com> wrote:

> Adds support to disassemble Zvfbdota32f instructions.
> - vfbdota.vv
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 1 +
>  disas/riscv.c        | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 58f6ddac35a..779fc26a27c 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -538,6 +538,7 @@ OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>  OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
>  OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfbdota_vv, "vfbdota.vv", rv_codec_v_r_ci, rv_fmt_vd_vs2_vs1_ci_vm)
>  OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
>  OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a124cbb4bbe..8330ba34a30 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2647,6 +2647,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  case 36: return &op_vfwdota_vv;
>                  case 38: return &op_vfqwdota_vv;
>                  case 39: return &op_vfqwdota_alt_vv;
> +                case 43: return &op_vfbdota_vv;
>                  case 44: return &op_vfwbdota_vv;
>                  case 46: return &op_vfqwbdota_vv;
>                  case 47: return &op_vfqwbdota_alt_vv;
> -- 
> 2.56.0
> 
> 
> 

Sent using hkml (https://github.com/sjp38/hackermail)

[RFC PATCH 38/38] tests/tcg/riscv64: Add test for Zvdota/Zvbdota extensions

[Max Chou]

Add a test that exercises the RISC-V Zvdota/Zvbdota instructions.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 tests/tcg/riscv64/system/meson.build |  12 +
 tests/tcg/riscv64/test-zvdota.S      | 343 +++++++++++++++++++++++++++
 2 files changed, 355 insertions(+)
 create mode 100644 tests/tcg/riscv64/test-zvdota.S

diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/system/meson.build
index 3c8b018d9e9..01370badb0d 100644
--- a/tests/tcg/riscv64/system/meson.build
+++ b/tests/tcg/riscv64/system/meson.build
@@ -89,6 +89,18 @@ tests += {
   }
 }
 
+dot_cpu = ('rv64,v=true,vlen=512' +
+           ',x-zvqwdota8i=true,x-zvqwdota16i=true' +
+           ',x-zvqwbdota8i=true,x-zvqwbdota16i=true' +
+           ',x-zvfwdota16bf=true,x-zvfwbdota16bf=true' +
+           ',x-zvfqwdota8f=true,x-zvfqwbdota8f=true,x-zvfbdota32f=true')
+tests += {
+  'test-zvdota.S': {
+    'cflags': cflags,
+    'qemu_args': ['-cpu', dot_cpu, qemu_args],
+  }
+}
+
 if 'qemu-system-riscv64' in emulators
   tcg_tests += {
     'riscv64-softmmu': {
diff --git a/tests/tcg/riscv64/test-zvdota.S b/tests/tcg/riscv64/test-zvdota.S
new file mode 100644
index 00000000000..eefb615088f
--- /dev/null
+++ b/tests/tcg/riscv64/test-zvdota.S
@@ -0,0 +1,343 @@
+/*
+ * Test the Zvdota/Zvbdota extensions
+ *
+ * Each dot has four input pairs. Integer inputs distinguish all four
+ * signedness combinations; the -7 accumulator also exercises wraparound.
+ * Floating inputs represent A = [1, -2, 0.5, 4] and column n of B =
+ * [n + 1, -2, 3, 0.5]. With accumulator 1.5, C[n] = n + 10 exactly.
+ * Separate BF16 cases check round-to-odd in the final accumulator addition.
+ *
+ * Poisoned source tails must not contribute. Destination prestart/tail
+ * elements and masked-off batched outputs must remain undisturbed (tu/mu).
+ * The test requires VLEN 512, which also exercises ci = 8.
+ *
+ * Exit status is zero on success or the numbered check on failure, including
+ * unexpected traps.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+	.option arch, +v
+	.option norvc
+	.option norelax
+
+/* ci is an element index; its encoding is the index divided by eight. */
+#define DOT(f6, f3, vm, ci) \
+    (((f6) << 26) | ((vm) << 25) | ((8 | ((ci) / 8)) << 20) | \
+     (1 << 15) | ((f3) << 12) | (16 << 7) | 0x77)
+
+	.text
+
+/* Load four elements per source, leaving all remaining elements poisoned. */
+.macro LOAD_INPUT sew, a, b
+	vsetvli t0, zero, e\sew, m1, tu, mu
+	vmv.v.i v1, -1
+	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
+	vmv.v.i v\reg, -1
+	.endr
+	li	t0, 4
+	vsetvli t0, t0, e\sew, m1, tu, mu
+	la	t1, \a
+	vle\sew\().v v1, (t1)
+	la	t1, \b
+	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
+	vle\sew\().v v\reg, (t1)
+	addi	t1, t1, \sew / 2
+	.endr
+.endm
+
+/*
+ * Initialize an m4 destination at its output width, execute with the input
+ * vtype, and compare the whole m4 group (including untouched registers).
+ * v0 contains repeating 0xaa55: scalar dots mask inputs, batched dots outputs.
+ * Nonzero-ci cases give prestart elements a different accumulator seed.
+ */
+.macro RUN id, f6, f3, type, eew, exp, batch=0, vm=1, vl=4, ci=0
+	li	t6, \id
+	vsetvli s0, zero, e\eew, m4, tu, mu
+	.if \f3
+	li	s1, 0x3fc00000	/* FP32 accumulator = 1.5. */
+	.else
+	li	s1, -7
+	.endif
+	vmv.v.x v16, s1
+	.if \ci
+	li	t0, \ci
+	vsetvli t0, t0, e\eew, m4, tu, mu
+	addi	t0, s1, 1
+	vmv.v.x v16, t0
+	.endif
+	li	t1, \vl
+	li	t2, \type
+	vsetvl	t0, t1, t2
+	bne	t0, t1, fail
+	.word	DOT(\f6, \f3, \vm, \ci)
+	csrr	t0, vstart
+	bnez	t0, fail
+	csrr	t0, fflags
+	bnez	t0, fail
+	vsetvli t0, zero, e\eew, m4, tu, mu
+	la	a0, result
+	vse\eew\().v v16, (a0)
+	la	a1, \exp
+	mv	a2, s0
+	li	a3, \ci
+	.if \vl == 0
+	li	a4, 0
+	.elseif \batch
+	li	a4, 8
+	.else
+	li	a4, 1
+	.endif
+	li	a5, \eew / 8
+	mv	a6, s1
+	.if \batch && !\vm
+	li	a7, (0xaa55 >> \ci) & 0xff
+	.else
+	li	a7, 0xff
+	.endif
+	call	check_result
+.endm
+
+/* The trap handler verifies the cause, faulting PC and instruction bits. */
+.macro ILLEGAL id, f6, f3, type, start=0
+	li	t6, \id
+	li	t1, 4
+	li	t2, \type
+	vsetvl	t0, t1, t2
+	li	t0, \start
+	csrw	vstart, t0
+	la	s2, 1f
+	li	s3, DOT(\f6, \f3, 1, 0)
+1:	.word	DOT(\f6, \f3, 1, 0)
+	bnez	s2, fail	/* Must have taken the expected trap. */
+.endm
+
+	.global _start
+_start:
+	li	t6, 44		/* Setup failure. */
+	li	s2, 0		/* No trap expected outside ILLEGAL. */
+	la	t0, trap_handler
+	csrw	mtvec, t0
+	li	t0, (1 << 9) | (1 << 13)
+	csrs	mstatus, t0
+	csrw	fcsr, zero
+	csrr	t0, vlenb
+	li	t1, 64		/* VLEN 512 only. */
+	bne	t0, t1, fail
+	vsetvli t0, zero, e16, m1, tu, mu
+	li	t0, 0xaa55
+	vmv.v.x v0, t0
+
+	/* Integer scalar dots: vs2 signedness in opcode, vs1 in altfmt. */
+	LOAD_INPUT 8, a_i8, b_i8
+	RUN	1, 0x26, 0, 0x000, 32, exp_i8_uu
+	RUN	2, 0x27, 0, 0x000, 32, exp_i8_us
+	RUN	3, 0x26, 0, 0x100, 32, exp_i8_su
+	RUN	4, 0x27, 0, 0x100, 32, exp_i8_ss
+	RUN	5, 0x26, 0, 0x000, 32, exp_i8_mask, vm=0
+	RUN	6, 0x26, 0, 0x000, 32, exp_i8_uu, vl=0
+	LOAD_INPUT 16, a_i16, b_i16
+	RUN	7, 0x26, 0, 0x008, 64, exp_i16_uu
+	RUN	8, 0x27, 0, 0x008, 64, exp_i16_us
+	RUN	9, 0x26, 0, 0x108, 64, exp_i16_su
+	RUN	10, 0x27, 0, 0x108, 64, exp_i16_ss
+
+	/* Batched dots use all eight columns, even though vl is only four. */
+	LOAD_INPUT 8, a_i8, b_i8
+	RUN	11, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1
+	RUN	12, 0x2f, 0, 0x000, 32, exp_i8_us, batch=1
+	RUN	13, 0x2e, 0, 0x100, 32, exp_i8_su, batch=1
+	RUN	14, 0x2f, 0, 0x100, 32, exp_i8_ss, batch=1
+	RUN	15, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0
+	RUN	16, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vl=0
+	LOAD_INPUT 16, a_i16, b_i16
+	RUN	17, 0x2e, 0, 0x008, 64, exp_i16_uu, batch=1
+	RUN	18, 0x2f, 0, 0x008, 64, exp_i16_us, batch=1
+	RUN	19, 0x2e, 0, 0x108, 64, exp_i16_su, batch=1
+	RUN	20, 0x2f, 0, 0x108, 64, exp_i16_ss, batch=1
+
+	/* BF16 requires SEW=16, altfmt=1. */
+	LOAD_INPUT 16, a_bf16, b_bf16
+	RUN	21, 0x24, 1, 0x108, 32, exp_fp
+	RUN	22, 0x24, 1, 0x108, 32, exp_fp_mask, vm=0
+	RUN	23, 0x2c, 1, 0x108, 32, exp_fp, batch=1
+	RUN	24, 0x2c, 1, 0x108, 32, exp_fp, batch=1, vm=0
+
+	/* OFP8: ordinary/alt opcode selects vs2, altfmt selects vs1. */
+	LOAD_INPUT 8, a_e4m3, b_e4m3
+	RUN	25, 0x26, 1, 0x000, 32, exp_fp
+	RUN	29, 0x26, 1, 0x000, 32, exp_fp_mask, vm=0
+	RUN	30, 0x2e, 1, 0x000, 32, exp_fp, batch=1
+	RUN	34, 0x2e, 1, 0x000, 32, exp_fp, batch=1, vm=0
+	LOAD_INPUT 8, a_e4m3, b_e5m2
+	RUN	26, 0x27, 1, 0x000, 32, exp_fp
+	RUN	31, 0x2f, 1, 0x000, 32, exp_fp, batch=1
+	LOAD_INPUT 8, a_e5m2, b_e4m3
+	RUN	27, 0x26, 1, 0x100, 32, exp_fp
+	RUN	32, 0x2e, 1, 0x100, 32, exp_fp, batch=1
+	LOAD_INPUT 8, a_e5m2, b_e5m2
+	RUN	28, 0x27, 1, 0x100, 32, exp_fp
+	RUN	33, 0x2f, 1, 0x100, 32, exp_fp, batch=1
+
+	LOAD_INPUT 32, a_fp32, b_fp32
+	RUN	35, 0x2b, 1, 0x010, 32, exp_fp, batch=1
+	RUN	36, 0x2b, 1, 0x010, 32, exp_fp, batch=1, vm=0
+
+	/* 1.5 + 2^-24 rounds to odd (0x3fc00001), without setting NX. */
+	LOAD_INPUT 16, a_tiny, b_tiny
+	RUN	37, 0x24, 1, 0x108, 32, exp_odd
+	RUN	38, 0x2c, 1, 0x108, 32, exp_odd, batch=1
+
+	LOAD_INPUT 8, a_i8, b_i8
+	RUN	39, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, ci=8
+	RUN	40, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0, ci=8
+	ILLEGAL 41, 0x26, 0, 0x000, start=1	/* Nonzero vstart. */
+	ILLEGAL 42, 0x2e, 0, 0x001		/* Batched LMUL=2. */
+	ILLEGAL 43, 0x24, 1, 0x008		/* BF16 altfmt=0. */
+	li	a0, 0
+	j	_exit
+
+	.balign 4
+trap_handler:
+	beqz	s2, fail
+	csrr	t0, mcause
+	li	t1, 2		/* Illegal instruction. */
+	bne	t0, t1, fail
+	csrr	t0, mtval
+	bne	t0, s3, fail
+	csrr	t0, mepc
+	bne	t0, s2, fail
+	addi	t0, t0, 4
+	csrw	mepc, t0
+	csrw	vstart, zero
+	li	s2, 0
+	mret
+
+/*
+ * a0=result, a1=expected body, a2=total elements, a3=first body element,
+ * a4=body count, a5=element bytes, a6=seed, a7=active body mask.
+ * Prestart elements use seed + 1; masked-off body and tail elements use seed.
+ */
+check_result:
+	li	t0, 0
+1:	mv	t3, a6
+	bltu	t0, a3, 6f
+	sub	t1, t0, a3
+	bgeu	t1, a4, 3f
+	srl	t2, a7, t1
+	andi	t2, t2, 1
+	beqz	t2, 3f
+	mul	t2, t1, a5
+	add	t2, a1, t2
+	li	t3, 8
+	beq	a5, t3, 2f
+	lw	t3, 0(t2)
+	j	3f
+2:	ld	t3, 0(t2)
+3:	li	t2, 8
+	beq	a5, t2, 4f
+	lw	t2, 0(a0)
+	j	5f
+4:	ld	t2, 0(a0)
+5:	bne	t2, t3, fail
+	add	a0, a0, a5
+	addi	t0, t0, 1
+	bltu	t0, a2, 1b
+	ret
+6:	addi	t3, a6, 1
+	j	3b
+
+fail:
+	mv	a0, t6
+_exit:
+	la	a1, semiargs
+	li	t0, 0x20026
+	sd	t0, 0(a1)
+	sd	a0, 8(a1)
+	li	a0, 0x20
+	.balign 16
+	slli	zero, zero, 0x1f
+	ebreak
+	srai	zero, zero, 0x7
+	j	.
+
+	.data
+	.balign 8
+semiargs:
+	.space 16
+result:
+	.space 256	/* m4 at VLEN 512. */
+
+a_i8:
+	.byte 0xfe, 0x82, 2, 3
+b_i8:
+	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
+	.byte 0xff - \n, 0x80 + \n, 3, 7
+	.endr
+	.balign 2
+a_i16:
+	.half 0xfffe, 0x8002, 2, 3
+b_i16:
+	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
+	.half 0xffff - \n, 0x8000 + \n, 3, 7
+	.endr
+
+a_bf16:
+	.half 0x3f80, 0xc000, 0x3f00, 0x4080
+b_bf16:
+	.irp bits,0x3f80,0x4000,0x4040,0x4080,0x40a0,0x40c0,0x40e0,0x4100
+	.half \bits, 0xc000, 0x4040, 0x3f00
+	.endr
+a_e4m3:
+	.byte 0x38, 0xc0, 0x30, 0x48
+b_e4m3:
+	.irp bits, 0x38, 0x40, 0x44, 0x48, 0x4a, 0x4c, 0x4e, 0x50
+	.byte \bits, 0xc0, 0x44, 0x30
+	.endr
+a_e5m2:
+	.byte 0x3c, 0xc0, 0x38, 0x44
+b_e5m2:
+	.irp bits, 0x3c, 0x40, 0x42, 0x44, 0x45, 0x46, 0x47, 0x48
+	.byte \bits, 0xc0, 0x42, 0x38
+	.endr
+	.balign 4
+a_fp32:
+	.float 1.0, -2.0, 0.5, 4.0
+b_fp32:
+	.irp n, 1, 2, 3, 4, 5, 6, 7, 8
+	.float \n, -2.0, 3.0, 0.5
+	.endr
+a_tiny:
+	.half 0x3f80, 0, 0, 0
+b_tiny:
+	.rept 8
+	.half 0x3380, 0, 0, 0
+	.endr
+
+/* Suffixes describe vs1 then vs2; -7 + A dot B, modulo output width. */
+.macro EXPECT_INT name, width, a0, a1, b0, b1
+\name:
+	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
+	.\width -7 + (\a0) * ((\b0) - \n) + (\a1) * ((\b1) + \n) + 2 * 3 + 3 * 7
+	.endr
+.endm
+	.balign 8
+	EXPECT_INT exp_i8_uu, word, 254, 130, 255, 128
+	EXPECT_INT exp_i8_us, word, 254, 130, -1, -128
+	EXPECT_INT exp_i8_su, word, -2, -126, 255, 128
+	EXPECT_INT exp_i8_ss, word, -2, -126, -1, -128
+	EXPECT_INT exp_i16_uu, dword, 65534, 32770, 65535, 32768
+	EXPECT_INT exp_i16_us, dword, 65534, 32770, -1, -32768
+	EXPECT_INT exp_i16_su, dword, -2, -32766, 65535, 32768
+	EXPECT_INT exp_i16_ss, dword, -2, -32766, -1, -32768
+exp_i8_mask:
+	.word -7 + 254 * 255 + 2 * 3
+exp_fp:
+	.float 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0
+exp_fp_mask:
+	.float 4.0
+exp_odd:
+	.rept 8
+	.word 0x3fc00001
+	.endr
-- 
2.56.0

Re: [RFC PATCH 38/38] tests/tcg/riscv64: Add test for Zvdota/Zvbdota extensions

[Daniel Henrique Barboza]

On 11/4/2026 4:41 PM, Max Chou wrote:
> Add a test that exercises the RISC-V Zvdota/Zvbdota instructions.
> 

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   tests/tcg/riscv64/system/meson.build |  12 +
>   tests/tcg/riscv64/test-zvdota.S      | 343 +++++++++++++++++++++++++++
>   2 files changed, 355 insertions(+)
>   create mode 100644 tests/tcg/riscv64/test-zvdota.S
> 
> diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/system/meson.build
> index 3c8b018d9e9..01370badb0d 100644
> --- a/tests/tcg/riscv64/system/meson.build
> +++ b/tests/tcg/riscv64/system/meson.build
> @@ -89,6 +89,18 @@ tests += {
>     }
>   }
>   
> +dot_cpu = ('rv64,v=true,vlen=512' +
> +           ',x-zvqwdota8i=true,x-zvqwdota16i=true' +
> +           ',x-zvqwbdota8i=true,x-zvqwbdota16i=true' +
> +           ',x-zvfwdota16bf=true,x-zvfwbdota16bf=true' +
> +           ',x-zvfqwdota8f=true,x-zvfqwbdota8f=true,x-zvfbdota32f=true')
> +tests += {
> +  'test-zvdota.S': {
> +    'cflags': cflags,
> +    'qemu_args': ['-cpu', dot_cpu, qemu_args],
> +  }
> +}
> +
>   if 'qemu-system-riscv64' in emulators
>     tcg_tests += {
>       'riscv64-softmmu': {
> diff --git a/tests/tcg/riscv64/test-zvdota.S b/tests/tcg/riscv64/test-zvdota.S
> new file mode 100644
> index 00000000000..eefb615088f
> --- /dev/null
> +++ b/tests/tcg/riscv64/test-zvdota.S
> @@ -0,0 +1,343 @@
> +/*
> + * Test the Zvdota/Zvbdota extensions
> + *
> + * Each dot has four input pairs. Integer inputs distinguish all four
> + * signedness combinations; the -7 accumulator also exercises wraparound.
> + * Floating inputs represent A = [1, -2, 0.5, 4] and column n of B =
> + * [n + 1, -2, 3, 0.5]. With accumulator 1.5, C[n] = n + 10 exactly.
> + * Separate BF16 cases check round-to-odd in the final accumulator addition.
> + *
> + * Poisoned source tails must not contribute. Destination prestart/tail
> + * elements and masked-off batched outputs must remain undisturbed (tu/mu).
> + * The test requires VLEN 512, which also exercises ci = 8.
> + *
> + * Exit status is zero on success or the numbered check on failure, including
> + * unexpected traps.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +	.option arch, +v
> +	.option norvc
> +	.option norelax
> +
> +/* ci is an element index; its encoding is the index divided by eight. */
> +#define DOT(f6, f3, vm, ci) \
> +    (((f6) << 26) | ((vm) << 25) | ((8 | ((ci) / 8)) << 20) | \
> +     (1 << 15) | ((f3) << 12) | (16 << 7) | 0x77)
> +
> +	.text
> +
> +/* Load four elements per source, leaving all remaining elements poisoned. */
> +.macro LOAD_INPUT sew, a, b
> +	vsetvli t0, zero, e\sew, m1, tu, mu
> +	vmv.v.i v1, -1
> +	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
> +	vmv.v.i v\reg, -1
> +	.endr
> +	li	t0, 4
> +	vsetvli t0, t0, e\sew, m1, tu, mu
> +	la	t1, \a
> +	vle\sew\().v v1, (t1)
> +	la	t1, \b
> +	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
> +	vle\sew\().v v\reg, (t1)
> +	addi	t1, t1, \sew / 2
> +	.endr
> +.endm
> +
> +/*
> + * Initialize an m4 destination at its output width, execute with the input
> + * vtype, and compare the whole m4 group (including untouched registers).
> + * v0 contains repeating 0xaa55: scalar dots mask inputs, batched dots outputs.
> + * Nonzero-ci cases give prestart elements a different accumulator seed.
> + */
> +.macro RUN id, f6, f3, type, eew, exp, batch=0, vm=1, vl=4, ci=0
> +	li	t6, \id
> +	vsetvli s0, zero, e\eew, m4, tu, mu
> +	.if \f3
> +	li	s1, 0x3fc00000	/* FP32 accumulator = 1.5. */
> +	.else
> +	li	s1, -7
> +	.endif
> +	vmv.v.x v16, s1
> +	.if \ci
> +	li	t0, \ci
> +	vsetvli t0, t0, e\eew, m4, tu, mu
> +	addi	t0, s1, 1
> +	vmv.v.x v16, t0
> +	.endif
> +	li	t1, \vl
> +	li	t2, \type
> +	vsetvl	t0, t1, t2
> +	bne	t0, t1, fail
> +	.word	DOT(\f6, \f3, \vm, \ci)
> +	csrr	t0, vstart
> +	bnez	t0, fail
> +	csrr	t0, fflags
> +	bnez	t0, fail
> +	vsetvli t0, zero, e\eew, m4, tu, mu
> +	la	a0, result
> +	vse\eew\().v v16, (a0)
> +	la	a1, \exp
> +	mv	a2, s0
> +	li	a3, \ci
> +	.if \vl == 0
> +	li	a4, 0
> +	.elseif \batch
> +	li	a4, 8
> +	.else
> +	li	a4, 1
> +	.endif
> +	li	a5, \eew / 8
> +	mv	a6, s1
> +	.if \batch && !\vm
> +	li	a7, (0xaa55 >> \ci) & 0xff
> +	.else
> +	li	a7, 0xff
> +	.endif
> +	call	check_result
> +.endm
> +
> +/* The trap handler verifies the cause, faulting PC and instruction bits. */
> +.macro ILLEGAL id, f6, f3, type, start=0
> +	li	t6, \id
> +	li	t1, 4
> +	li	t2, \type
> +	vsetvl	t0, t1, t2
> +	li	t0, \start
> +	csrw	vstart, t0
> +	la	s2, 1f
> +	li	s3, DOT(\f6, \f3, 1, 0)
> +1:	.word	DOT(\f6, \f3, 1, 0)
> +	bnez	s2, fail	/* Must have taken the expected trap. */
> +.endm
> +
> +	.global _start
> +_start:
> +	li	t6, 44		/* Setup failure. */
> +	li	s2, 0		/* No trap expected outside ILLEGAL. */
> +	la	t0, trap_handler
> +	csrw	mtvec, t0
> +	li	t0, (1 << 9) | (1 << 13)
> +	csrs	mstatus, t0
> +	csrw	fcsr, zero
> +	csrr	t0, vlenb
> +	li	t1, 64		/* VLEN 512 only. */
> +	bne	t0, t1, fail
> +	vsetvli t0, zero, e16, m1, tu, mu
> +	li	t0, 0xaa55
> +	vmv.v.x v0, t0
> +
> +	/* Integer scalar dots: vs2 signedness in opcode, vs1 in altfmt. */
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	1, 0x26, 0, 0x000, 32, exp_i8_uu
> +	RUN	2, 0x27, 0, 0x000, 32, exp_i8_us
> +	RUN	3, 0x26, 0, 0x100, 32, exp_i8_su
> +	RUN	4, 0x27, 0, 0x100, 32, exp_i8_ss
> +	RUN	5, 0x26, 0, 0x000, 32, exp_i8_mask, vm=0
> +	RUN	6, 0x26, 0, 0x000, 32, exp_i8_uu, vl=0
> +	LOAD_INPUT 16, a_i16, b_i16
> +	RUN	7, 0x26, 0, 0x008, 64, exp_i16_uu
> +	RUN	8, 0x27, 0, 0x008, 64, exp_i16_us
> +	RUN	9, 0x26, 0, 0x108, 64, exp_i16_su
> +	RUN	10, 0x27, 0, 0x108, 64, exp_i16_ss
> +
> +	/* Batched dots use all eight columns, even though vl is only four. */
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	11, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1
> +	RUN	12, 0x2f, 0, 0x000, 32, exp_i8_us, batch=1
> +	RUN	13, 0x2e, 0, 0x100, 32, exp_i8_su, batch=1
> +	RUN	14, 0x2f, 0, 0x100, 32, exp_i8_ss, batch=1
> +	RUN	15, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0
> +	RUN	16, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vl=0
> +	LOAD_INPUT 16, a_i16, b_i16
> +	RUN	17, 0x2e, 0, 0x008, 64, exp_i16_uu, batch=1
> +	RUN	18, 0x2f, 0, 0x008, 64, exp_i16_us, batch=1
> +	RUN	19, 0x2e, 0, 0x108, 64, exp_i16_su, batch=1
> +	RUN	20, 0x2f, 0, 0x108, 64, exp_i16_ss, batch=1
> +
> +	/* BF16 requires SEW=16, altfmt=1. */
> +	LOAD_INPUT 16, a_bf16, b_bf16
> +	RUN	21, 0x24, 1, 0x108, 32, exp_fp
> +	RUN	22, 0x24, 1, 0x108, 32, exp_fp_mask, vm=0
> +	RUN	23, 0x2c, 1, 0x108, 32, exp_fp, batch=1
> +	RUN	24, 0x2c, 1, 0x108, 32, exp_fp, batch=1, vm=0
> +
> +	/* OFP8: ordinary/alt opcode selects vs2, altfmt selects vs1. */
> +	LOAD_INPUT 8, a_e4m3, b_e4m3
> +	RUN	25, 0x26, 1, 0x000, 32, exp_fp
> +	RUN	29, 0x26, 1, 0x000, 32, exp_fp_mask, vm=0
> +	RUN	30, 0x2e, 1, 0x000, 32, exp_fp, batch=1
> +	RUN	34, 0x2e, 1, 0x000, 32, exp_fp, batch=1, vm=0
> +	LOAD_INPUT 8, a_e4m3, b_e5m2
> +	RUN	26, 0x27, 1, 0x000, 32, exp_fp
> +	RUN	31, 0x2f, 1, 0x000, 32, exp_fp, batch=1
> +	LOAD_INPUT 8, a_e5m2, b_e4m3
> +	RUN	27, 0x26, 1, 0x100, 32, exp_fp
> +	RUN	32, 0x2e, 1, 0x100, 32, exp_fp, batch=1
> +	LOAD_INPUT 8, a_e5m2, b_e5m2
> +	RUN	28, 0x27, 1, 0x100, 32, exp_fp
> +	RUN	33, 0x2f, 1, 0x100, 32, exp_fp, batch=1
> +
> +	LOAD_INPUT 32, a_fp32, b_fp32
> +	RUN	35, 0x2b, 1, 0x010, 32, exp_fp, batch=1
> +	RUN	36, 0x2b, 1, 0x010, 32, exp_fp, batch=1, vm=0
> +
> +	/* 1.5 + 2^-24 rounds to odd (0x3fc00001), without setting NX. */
> +	LOAD_INPUT 16, a_tiny, b_tiny
> +	RUN	37, 0x24, 1, 0x108, 32, exp_odd
> +	RUN	38, 0x2c, 1, 0x108, 32, exp_odd, batch=1
> +
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	39, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, ci=8
> +	RUN	40, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0, ci=8
> +	ILLEGAL 41, 0x26, 0, 0x000, start=1	/* Nonzero vstart. */
> +	ILLEGAL 42, 0x2e, 0, 0x001		/* Batched LMUL=2. */
> +	ILLEGAL 43, 0x24, 1, 0x008		/* BF16 altfmt=0. */
> +	li	a0, 0
> +	j	_exit
> +
> +	.balign 4
> +trap_handler:
> +	beqz	s2, fail
> +	csrr	t0, mcause
> +	li	t1, 2		/* Illegal instruction. */
> +	bne	t0, t1, fail
> +	csrr	t0, mtval
> +	bne	t0, s3, fail
> +	csrr	t0, mepc
> +	bne	t0, s2, fail
> +	addi	t0, t0, 4
> +	csrw	mepc, t0
> +	csrw	vstart, zero
> +	li	s2, 0
> +	mret
> +
> +/*
> + * a0=result, a1=expected body, a2=total elements, a3=first body element,
> + * a4=body count, a5=element bytes, a6=seed, a7=active body mask.
> + * Prestart elements use seed + 1; masked-off body and tail elements use seed.
> + */
> +check_result:
> +	li	t0, 0
> +1:	mv	t3, a6
> +	bltu	t0, a3, 6f
> +	sub	t1, t0, a3
> +	bgeu	t1, a4, 3f
> +	srl	t2, a7, t1
> +	andi	t2, t2, 1
> +	beqz	t2, 3f
> +	mul	t2, t1, a5
> +	add	t2, a1, t2
> +	li	t3, 8
> +	beq	a5, t3, 2f
> +	lw	t3, 0(t2)
> +	j	3f
> +2:	ld	t3, 0(t2)
> +3:	li	t2, 8
> +	beq	a5, t2, 4f
> +	lw	t2, 0(a0)
> +	j	5f
> +4:	ld	t2, 0(a0)
> +5:	bne	t2, t3, fail
> +	add	a0, a0, a5
> +	addi	t0, t0, 1
> +	bltu	t0, a2, 1b
> +	ret
> +6:	addi	t3, a6, 1
> +	j	3b
> +
> +fail:
> +	mv	a0, t6
> +_exit:
> +	la	a1, semiargs
> +	li	t0, 0x20026
> +	sd	t0, 0(a1)
> +	sd	a0, 8(a1)
> +	li	a0, 0x20
> +	.balign 16
> +	slli	zero, zero, 0x1f
> +	ebreak
> +	srai	zero, zero, 0x7
> +	j	.
> +
> +	.data
> +	.balign 8
> +semiargs:
> +	.space 16
> +result:
> +	.space 256	/* m4 at VLEN 512. */
> +
> +a_i8:
> +	.byte 0xfe, 0x82, 2, 3
> +b_i8:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.byte 0xff - \n, 0x80 + \n, 3, 7
> +	.endr
> +	.balign 2
> +a_i16:
> +	.half 0xfffe, 0x8002, 2, 3
> +b_i16:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.half 0xffff - \n, 0x8000 + \n, 3, 7
> +	.endr
> +
> +a_bf16:
> +	.half 0x3f80, 0xc000, 0x3f00, 0x4080
> +b_bf16:
> +	.irp bits,0x3f80,0x4000,0x4040,0x4080,0x40a0,0x40c0,0x40e0,0x4100
> +	.half \bits, 0xc000, 0x4040, 0x3f00
> +	.endr
> +a_e4m3:
> +	.byte 0x38, 0xc0, 0x30, 0x48
> +b_e4m3:
> +	.irp bits, 0x38, 0x40, 0x44, 0x48, 0x4a, 0x4c, 0x4e, 0x50
> +	.byte \bits, 0xc0, 0x44, 0x30
> +	.endr
> +a_e5m2:
> +	.byte 0x3c, 0xc0, 0x38, 0x44
> +b_e5m2:
> +	.irp bits, 0x3c, 0x40, 0x42, 0x44, 0x45, 0x46, 0x47, 0x48
> +	.byte \bits, 0xc0, 0x42, 0x38
> +	.endr
> +	.balign 4
> +a_fp32:
> +	.float 1.0, -2.0, 0.5, 4.0
> +b_fp32:
> +	.irp n, 1, 2, 3, 4, 5, 6, 7, 8
> +	.float \n, -2.0, 3.0, 0.5
> +	.endr
> +a_tiny:
> +	.half 0x3f80, 0, 0, 0
> +b_tiny:
> +	.rept 8
> +	.half 0x3380, 0, 0, 0
> +	.endr
> +
> +/* Suffixes describe vs1 then vs2; -7 + A dot B, modulo output width. */
> +.macro EXPECT_INT name, width, a0, a1, b0, b1
> +\name:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.\width -7 + (\a0) * ((\b0) - \n) + (\a1) * ((\b1) + \n) + 2 * 3 + 3 * 7
> +	.endr
> +.endm
> +	.balign 8
> +	EXPECT_INT exp_i8_uu, word, 254, 130, 255, 128
> +	EXPECT_INT exp_i8_us, word, 254, 130, -1, -128
> +	EXPECT_INT exp_i8_su, word, -2, -126, 255, 128
> +	EXPECT_INT exp_i8_ss, word, -2, -126, -1, -128
> +	EXPECT_INT exp_i16_uu, dword, 65534, 32770, 65535, 32768
> +	EXPECT_INT exp_i16_us, dword, 65534, 32770, -1, -32768
> +	EXPECT_INT exp_i16_su, dword, -2, -32766, 65535, 32768
> +	EXPECT_INT exp_i16_ss, dword, -2, -32766, -1, -32768
> +exp_i8_mask:
> +	.word -7 + 254 * 255 + 2 * 3
> +exp_fp:
> +	.float 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0
> +exp_fp_mask:
> +	.float 4.0
> +exp_odd:
> +	.rept 8
> +	.word 0x3fc00001
> +	.endr

Re: [RFC PATCH 38/38] tests/tcg/riscv64: Add test for Zvdota/Zvbdota extensions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:53 +0800 Max Chou <max.chou@sifive.com> wrote:

> Add a test that exercises the RISC-V Zvdota/Zvbdota instructions.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  tests/tcg/riscv64/system/meson.build |  12 +
>  tests/tcg/riscv64/test-zvdota.S      | 343 +++++++++++++++++++++++++++
>  2 files changed, 355 insertions(+)
>  create mode 100644 tests/tcg/riscv64/test-zvdota.S
> 
> diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/system/meson.build
> index 3c8b018d9e9..01370badb0d 100644
> --- a/tests/tcg/riscv64/system/meson.build
> +++ b/tests/tcg/riscv64/system/meson.build
> @@ -89,6 +89,18 @@ tests += {
>    }
>  }
>  
> +dot_cpu = ('rv64,v=true,vlen=512' +
> +           ',x-zvqwdota8i=true,x-zvqwdota16i=true' +
> +           ',x-zvqwbdota8i=true,x-zvqwbdota16i=true' +
> +           ',x-zvfwdota16bf=true,x-zvfwbdota16bf=true' +
> +           ',x-zvfqwdota8f=true,x-zvfqwbdota8f=true,x-zvfbdota32f=true')
> +tests += {
> +  'test-zvdota.S': {
> +    'cflags': cflags,
> +    'qemu_args': ['-cpu', dot_cpu, qemu_args],
> +  }
> +}
> +
>  if 'qemu-system-riscv64' in emulators
>    tcg_tests += {
>      'riscv64-softmmu': {
> diff --git a/tests/tcg/riscv64/test-zvdota.S b/tests/tcg/riscv64/test-zvdota.S
> new file mode 100644
> index 00000000000..eefb615088f
> --- /dev/null
> +++ b/tests/tcg/riscv64/test-zvdota.S
> @@ -0,0 +1,343 @@
> +/*
> + * Test the Zvdota/Zvbdota extensions
> + *
> + * Each dot has four input pairs. Integer inputs distinguish all four
> + * signedness combinations; the -7 accumulator also exercises wraparound.
> + * Floating inputs represent A = [1, -2, 0.5, 4] and column n of B =
> + * [n + 1, -2, 3, 0.5]. With accumulator 1.5, C[n] = n + 10 exactly.
> + * Separate BF16 cases check round-to-odd in the final accumulator addition.
> + *
> + * Poisoned source tails must not contribute. Destination prestart/tail
> + * elements and masked-off batched outputs must remain undisturbed (tu/mu).
> + * The test requires VLEN 512, which also exercises ci = 8.
> + *
> + * Exit status is zero on success or the numbered check on failure, including
> + * unexpected traps.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +	.option arch, +v
> +	.option norvc
> +	.option norelax
> +
> +/* ci is an element index; its encoding is the index divided by eight. */
> +#define DOT(f6, f3, vm, ci) \
> +    (((f6) << 26) | ((vm) << 25) | ((8 | ((ci) / 8)) << 20) | \
> +     (1 << 15) | ((f3) << 12) | (16 << 7) | 0x77)
> +
> +	.text
> +
> +/* Load four elements per source, leaving all remaining elements poisoned. */
> +.macro LOAD_INPUT sew, a, b
> +	vsetvli t0, zero, e\sew, m1, tu, mu
> +	vmv.v.i v1, -1
> +	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
> +	vmv.v.i v\reg, -1
> +	.endr
> +	li	t0, 4
> +	vsetvli t0, t0, e\sew, m1, tu, mu
> +	la	t1, \a
> +	vle\sew\().v v1, (t1)
> +	la	t1, \b
> +	.irp reg, 8, 9, 10, 11, 12, 13, 14, 15
> +	vle\sew\().v v\reg, (t1)
> +	addi	t1, t1, \sew / 2
> +	.endr
> +.endm
> +
> +/*
> + * Initialize an m4 destination at its output width, execute with the input
> + * vtype, and compare the whole m4 group (including untouched registers).
> + * v0 contains repeating 0xaa55: scalar dots mask inputs, batched dots outputs.
> + * Nonzero-ci cases give prestart elements a different accumulator seed.
> + */
> +.macro RUN id, f6, f3, type, eew, exp, batch=0, vm=1, vl=4, ci=0
> +	li	t6, \id
> +	vsetvli s0, zero, e\eew, m4, tu, mu
> +	.if \f3
> +	li	s1, 0x3fc00000	/* FP32 accumulator = 1.5. */
> +	.else
> +	li	s1, -7
> +	.endif
> +	vmv.v.x v16, s1
> +	.if \ci
> +	li	t0, \ci
> +	vsetvli t0, t0, e\eew, m4, tu, mu
> +	addi	t0, s1, 1
> +	vmv.v.x v16, t0
> +	.endif
> +	li	t1, \vl
> +	li	t2, \type
> +	vsetvl	t0, t1, t2
> +	bne	t0, t1, fail
> +	.word	DOT(\f6, \f3, \vm, \ci)
> +	csrr	t0, vstart
> +	bnez	t0, fail
> +	csrr	t0, fflags
> +	bnez	t0, fail
> +	vsetvli t0, zero, e\eew, m4, tu, mu
> +	la	a0, result
> +	vse\eew\().v v16, (a0)
> +	la	a1, \exp
> +	mv	a2, s0
> +	li	a3, \ci
> +	.if \vl == 0
> +	li	a4, 0
> +	.elseif \batch
> +	li	a4, 8
> +	.else
> +	li	a4, 1
> +	.endif
> +	li	a5, \eew / 8
> +	mv	a6, s1
> +	.if \batch && !\vm
> +	li	a7, (0xaa55 >> \ci) & 0xff
> +	.else
> +	li	a7, 0xff
> +	.endif
> +	call	check_result
> +.endm
> +
> +/* The trap handler verifies the cause, faulting PC and instruction bits. */
> +.macro ILLEGAL id, f6, f3, type, start=0
> +	li	t6, \id
> +	li	t1, 4
> +	li	t2, \type
> +	vsetvl	t0, t1, t2
> +	li	t0, \start
> +	csrw	vstart, t0
> +	la	s2, 1f
> +	li	s3, DOT(\f6, \f3, 1, 0)
> +1:	.word	DOT(\f6, \f3, 1, 0)
> +	bnez	s2, fail	/* Must have taken the expected trap. */
> +.endm
> +
> +	.global _start
> +_start:
> +	li	t6, 44		/* Setup failure. */
> +	li	s2, 0		/* No trap expected outside ILLEGAL. */
> +	la	t0, trap_handler
> +	csrw	mtvec, t0
> +	li	t0, (1 << 9) | (1 << 13)
> +	csrs	mstatus, t0
> +	csrw	fcsr, zero
> +	csrr	t0, vlenb
> +	li	t1, 64		/* VLEN 512 only. */
> +	bne	t0, t1, fail
> +	vsetvli t0, zero, e16, m1, tu, mu
> +	li	t0, 0xaa55
> +	vmv.v.x v0, t0
> +
> +	/* Integer scalar dots: vs2 signedness in opcode, vs1 in altfmt. */
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	1, 0x26, 0, 0x000, 32, exp_i8_uu
> +	RUN	2, 0x27, 0, 0x000, 32, exp_i8_us
> +	RUN	3, 0x26, 0, 0x100, 32, exp_i8_su
> +	RUN	4, 0x27, 0, 0x100, 32, exp_i8_ss
> +	RUN	5, 0x26, 0, 0x000, 32, exp_i8_mask, vm=0
> +	RUN	6, 0x26, 0, 0x000, 32, exp_i8_uu, vl=0
> +	LOAD_INPUT 16, a_i16, b_i16
> +	RUN	7, 0x26, 0, 0x008, 64, exp_i16_uu
> +	RUN	8, 0x27, 0, 0x008, 64, exp_i16_us
> +	RUN	9, 0x26, 0, 0x108, 64, exp_i16_su
> +	RUN	10, 0x27, 0, 0x108, 64, exp_i16_ss
> +
> +	/* Batched dots use all eight columns, even though vl is only four. */
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	11, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1
> +	RUN	12, 0x2f, 0, 0x000, 32, exp_i8_us, batch=1
> +	RUN	13, 0x2e, 0, 0x100, 32, exp_i8_su, batch=1
> +	RUN	14, 0x2f, 0, 0x100, 32, exp_i8_ss, batch=1
> +	RUN	15, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0
> +	RUN	16, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vl=0
> +	LOAD_INPUT 16, a_i16, b_i16
> +	RUN	17, 0x2e, 0, 0x008, 64, exp_i16_uu, batch=1
> +	RUN	18, 0x2f, 0, 0x008, 64, exp_i16_us, batch=1
> +	RUN	19, 0x2e, 0, 0x108, 64, exp_i16_su, batch=1
> +	RUN	20, 0x2f, 0, 0x108, 64, exp_i16_ss, batch=1
> +
> +	/* BF16 requires SEW=16, altfmt=1. */
> +	LOAD_INPUT 16, a_bf16, b_bf16
> +	RUN	21, 0x24, 1, 0x108, 32, exp_fp
> +	RUN	22, 0x24, 1, 0x108, 32, exp_fp_mask, vm=0
> +	RUN	23, 0x2c, 1, 0x108, 32, exp_fp, batch=1
> +	RUN	24, 0x2c, 1, 0x108, 32, exp_fp, batch=1, vm=0
> +
> +	/* OFP8: ordinary/alt opcode selects vs2, altfmt selects vs1. */
> +	LOAD_INPUT 8, a_e4m3, b_e4m3
> +	RUN	25, 0x26, 1, 0x000, 32, exp_fp
> +	RUN	29, 0x26, 1, 0x000, 32, exp_fp_mask, vm=0
> +	RUN	30, 0x2e, 1, 0x000, 32, exp_fp, batch=1
> +	RUN	34, 0x2e, 1, 0x000, 32, exp_fp, batch=1, vm=0
> +	LOAD_INPUT 8, a_e4m3, b_e5m2
> +	RUN	26, 0x27, 1, 0x000, 32, exp_fp
> +	RUN	31, 0x2f, 1, 0x000, 32, exp_fp, batch=1
> +	LOAD_INPUT 8, a_e5m2, b_e4m3
> +	RUN	27, 0x26, 1, 0x100, 32, exp_fp
> +	RUN	32, 0x2e, 1, 0x100, 32, exp_fp, batch=1
> +	LOAD_INPUT 8, a_e5m2, b_e5m2
> +	RUN	28, 0x27, 1, 0x100, 32, exp_fp
> +	RUN	33, 0x2f, 1, 0x100, 32, exp_fp, batch=1
> +
> +	LOAD_INPUT 32, a_fp32, b_fp32
> +	RUN	35, 0x2b, 1, 0x010, 32, exp_fp, batch=1
> +	RUN	36, 0x2b, 1, 0x010, 32, exp_fp, batch=1, vm=0
> +
> +	/* 1.5 + 2^-24 rounds to odd (0x3fc00001), without setting NX. */
> +	LOAD_INPUT 16, a_tiny, b_tiny
> +	RUN	37, 0x24, 1, 0x108, 32, exp_odd
> +	RUN	38, 0x2c, 1, 0x108, 32, exp_odd, batch=1
> +
> +	LOAD_INPUT 8, a_i8, b_i8
> +	RUN	39, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, ci=8
> +	RUN	40, 0x2e, 0, 0x000, 32, exp_i8_uu, batch=1, vm=0, ci=8
> +	ILLEGAL 41, 0x26, 0, 0x000, start=1	/* Nonzero vstart. */
> +	ILLEGAL 42, 0x2e, 0, 0x001		/* Batched LMUL=2. */
> +	ILLEGAL 43, 0x24, 1, 0x008		/* BF16 altfmt=0. */
> +	li	a0, 0
> +	j	_exit
> +
> +	.balign 4
> +trap_handler:
> +	beqz	s2, fail
> +	csrr	t0, mcause
> +	li	t1, 2		/* Illegal instruction. */
> +	bne	t0, t1, fail
> +	csrr	t0, mtval
> +	bne	t0, s3, fail
> +	csrr	t0, mepc
> +	bne	t0, s2, fail
> +	addi	t0, t0, 4
> +	csrw	mepc, t0
> +	csrw	vstart, zero
> +	li	s2, 0
> +	mret
> +
> +/*
> + * a0=result, a1=expected body, a2=total elements, a3=first body element,
> + * a4=body count, a5=element bytes, a6=seed, a7=active body mask.
> + * Prestart elements use seed + 1; masked-off body and tail elements use seed.
> + */
> +check_result:
> +	li	t0, 0
> +1:	mv	t3, a6
> +	bltu	t0, a3, 6f
> +	sub	t1, t0, a3
> +	bgeu	t1, a4, 3f
> +	srl	t2, a7, t1
> +	andi	t2, t2, 1
> +	beqz	t2, 3f
> +	mul	t2, t1, a5
> +	add	t2, a1, t2
> +	li	t3, 8
> +	beq	a5, t3, 2f
> +	lw	t3, 0(t2)
> +	j	3f
> +2:	ld	t3, 0(t2)
> +3:	li	t2, 8
> +	beq	a5, t2, 4f
> +	lw	t2, 0(a0)
> +	j	5f
> +4:	ld	t2, 0(a0)
> +5:	bne	t2, t3, fail
> +	add	a0, a0, a5
> +	addi	t0, t0, 1
> +	bltu	t0, a2, 1b
> +	ret
> +6:	addi	t3, a6, 1
> +	j	3b
> +
> +fail:
> +	mv	a0, t6
> +_exit:
> +	la	a1, semiargs
> +	li	t0, 0x20026
> +	sd	t0, 0(a1)
> +	sd	a0, 8(a1)
> +	li	a0, 0x20
> +	.balign 16
> +	slli	zero, zero, 0x1f
> +	ebreak
> +	srai	zero, zero, 0x7
> +	j	.
> +
> +	.data
> +	.balign 8
> +semiargs:
> +	.space 16
> +result:
> +	.space 256	/* m4 at VLEN 512. */
> +
> +a_i8:
> +	.byte 0xfe, 0x82, 2, 3
> +b_i8:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.byte 0xff - \n, 0x80 + \n, 3, 7
> +	.endr
> +	.balign 2
> +a_i16:
> +	.half 0xfffe, 0x8002, 2, 3
> +b_i16:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.half 0xffff - \n, 0x8000 + \n, 3, 7
> +	.endr
> +
> +a_bf16:
> +	.half 0x3f80, 0xc000, 0x3f00, 0x4080
> +b_bf16:
> +	.irp bits,0x3f80,0x4000,0x4040,0x4080,0x40a0,0x40c0,0x40e0,0x4100
> +	.half \bits, 0xc000, 0x4040, 0x3f00
> +	.endr
> +a_e4m3:
> +	.byte 0x38, 0xc0, 0x30, 0x48
> +b_e4m3:
> +	.irp bits, 0x38, 0x40, 0x44, 0x48, 0x4a, 0x4c, 0x4e, 0x50
> +	.byte \bits, 0xc0, 0x44, 0x30
> +	.endr
> +a_e5m2:
> +	.byte 0x3c, 0xc0, 0x38, 0x44
> +b_e5m2:
> +	.irp bits, 0x3c, 0x40, 0x42, 0x44, 0x45, 0x46, 0x47, 0x48
> +	.byte \bits, 0xc0, 0x42, 0x38
> +	.endr
> +	.balign 4
> +a_fp32:
> +	.float 1.0, -2.0, 0.5, 4.0
> +b_fp32:
> +	.irp n, 1, 2, 3, 4, 5, 6, 7, 8
> +	.float \n, -2.0, 3.0, 0.5
> +	.endr
> +a_tiny:
> +	.half 0x3f80, 0, 0, 0
> +b_tiny:
> +	.rept 8
> +	.half 0x3380, 0, 0, 0
> +	.endr
> +
> +/* Suffixes describe vs1 then vs2; -7 + A dot B, modulo output width. */
> +.macro EXPECT_INT name, width, a0, a1, b0, b1
> +\name:
> +	.irp n, 0, 1, 2, 3, 4, 5, 6, 7
> +	.\width -7 + (\a0) * ((\b0) - \n) + (\a1) * ((\b1) + \n) + 2 * 3 + 3 * 7
> +	.endr
> +.endm
> +	.balign 8
> +	EXPECT_INT exp_i8_uu, word, 254, 130, 255, 128
> +	EXPECT_INT exp_i8_us, word, 254, 130, -1, -128
> +	EXPECT_INT exp_i8_su, word, -2, -126, 255, 128
> +	EXPECT_INT exp_i8_ss, word, -2, -126, -1, -128
> +	EXPECT_INT exp_i16_uu, dword, 65534, 32770, 65535, 32768
> +	EXPECT_INT exp_i16_us, dword, 65534, 32770, -1, -32768
> +	EXPECT_INT exp_i16_su, dword, -2, -32766, 65535, 32768
> +	EXPECT_INT exp_i16_ss, dword, -2, -32766, -1, -32768
> +exp_i8_mask:
> +	.word -7 + 254 * 255 + 2 * 3
> +exp_fp:
> +	.float 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0
> +exp_fp_mask:
> +	.float 4.0
> +exp_odd:
> +	.rept 8
> +	.word 0x3fc00001
> +	.endr
> -- 
> 2.56.0
> 
> 
> 

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Re: [RFC PATCH 00/38] target/riscv: Add Zvdota/Zvbdota families of dot-product extensions

[Chao Liu]

On Thu,  5 Nov 2026 03:41:15 +0800 Max Chou <max.chou@sifive.com> wrote:

> This RFC patchset introduces the Zvdota/Zvbdota families of dot-product
> extensions based on the ISA specification
> (https://github.com/riscv/riscv-isa-manual/pull/2618 v1.0 commit: 570e32e)
> - Zvdota: Zvqwdota8i/Zvqwdota16i/Zvfwdota16bf/Zvfqwdota8f
> - Zvbdota: Zvqwbdota8i/Zvqwbdota16i/Zvfwbdota16bf/Zvfqwbdota8f/Zvfbdota32f
> 
> This RFC patchset assigns the Zvdota/Zvbdota cpu properties as the
> experimental cpu isa extension properties. These experimental cpu isa
> extension properties will be replaced after the Zvdota/Zvbdota isa
> specification is ratified.
> 
> The toolchains support Zvdota/Zvbdota families extensions:
>  - LLVM (after 23.1.0)
>    - Support v0.2 Zvdota/Zvbdota extensions
>      - https://releases.llvm.org/23.1.0/docs/RISCVUsage.html
>    - llvm/llvm-project#196467, commit d25ec4b84487, merged 2026-05-27.
>      - https://github.com/llvm/llvm-project/pull/196467
>  - GCC (reviewing)
>    - Upstream patchset: <20261014093604.829234-3-jiawei@iscas.ac.cn>
> 
> References:
>  - riscv-isa-manual PR: https://github.com/riscv/riscv-isa-manual/pull/2618
> 
I've run cross-validation tests based on fp-conv tools [1], and I haven't
found any issues so far. Looks good to me.

Link:
[1]: https://sw23.github.io/fp-conv/

Tested-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> rnax
> 
> Max Chou (38):
>   fpu/softfloat: Support OCP(Open Compute Project) OFP8 checking
>     functions
>   target/riscv: Introduce riscv_init_fp_status
>   target/riscv: rvv: Introduce RVBNA algorithm for Zvdota/Zvbdota
>     extensions
>   target/riscv: Add cfg property for Zvqwdota8i extension
>   target/riscv: Add implied rules for Zvqwdota8i extension
>   target/riscv: rvv: Implement Zvqwdota8i instructions
>   disas/riscv: Support Zvqwdota8i extension
>   target/riscv: Add Zvqwdota16i cpu property
>   target/riscv: Add Zvqwdota16i dependency imply rule
>   target/riscv: rvv: Implement Zvqwdota16i instructions
>   target/riscv: Add cfg property for Zvfwdota16bf extension
>   target/riscv: Add implied rules for Zvfwdota16bf extension
>   target/riscv: rvv: Implement Zvfwdota16bf instruction
>   disas/riscv: Support Zvfwdota16bf extension
>   target/riscv: Add cfg property for Zvfqwdota8f extension
>   target/riscv: Add implied rules for Zvfqwdota8f extension
>   target/riscv: rvv: Implement Zvfqwdota8f instructions
>   disas/riscv: Support Zvfqwdota8f extension
>   target/riscv: Add cfg property for Zvqwbdota8i extension
>   target/riscv: Add implied rules for Zvqwbdota8i extension
>   target/riscv: rvv: Implement Zvqwbdota8i instructions
>   disas/riscv: Support Zvqwbdota8i extension
>   target/riscv: Add cfg property for Zvqwbdota16i extension
>   target/riscv: Add implied rules for Zvqwbdota16i extension
>   target/riscv: rvv: Implement Zvqwbdota16i instructions
>   target/riscv: Add cfg property for Zvfwbdota16bf extension
>   target/riscv: Add implied rules for Zvfwbdota16bf extension
>   target/riscv: rvv: Implement Zvfwbdota16bf instruction
>   disas/riscv: Support Zvfwbdota16bf extension
>   target/riscv: Add cfg property for Zvfqwbdota8f extension
>   target/riscv: Add implied rules for Zvfqwbdota8f extension
>   target/riscv: rvv: Implement Zvfqwbdota8f instructions
>   disas/riscv: Support Zvfqwbdota8f extension
>   target/riscv: Add cfg property for Zvfbdota32f extension
>   target/riscv: Add implied rules for Zvfbdota32f extension
>   target/riscv: rvv: Implement Zvfbdota32f instructions
>   disas/riscv: Support Zvfbdota32f extension
>   tests/tcg/riscv64: Add test for Zvdota/Zvbdota extensions
> 
>  MAINTAINERS                                 |   6 +
>  disas/riscv-op.c.inc                        |  12 +
>  disas/riscv.c                               |  26 ++
>  disas/riscv.h                               |   2 +
>  fpu/softfloat-specialize.c.inc              |  55 +++
>  include/fpu/softfloat.h                     |  70 ++++
>  target/riscv/cpu.c                          | 121 +++++-
>  target/riscv/cpu_cfg_fields.h.inc           |   9 +
>  target/riscv/helper.h                       |  28 ++
>  target/riscv/insn32.decode                  |  25 ++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc | 305 ++++++++++++++
>  target/riscv/tcg/meson.build                |   2 +-
>  target/riscv/tcg/rvbna.c                    | 185 +++++++++
>  target/riscv/tcg/rvbna.h                    |  40 ++
>  target/riscv/tcg/tcg-cpu.c                  |  45 +++
>  target/riscv/tcg/vector_helper.c            | 424 +++++++++++++++++++-
>  tests/tcg/riscv64/system/meson.build        |  12 +
>  tests/tcg/riscv64/test-zvdota.S             | 343 ++++++++++++++++
>  18 files changed, 1703 insertions(+), 7 deletions(-)
>  create mode 100644 target/riscv/tcg/rvbna.c
>  create mode 100644 target/riscv/tcg/rvbna.h
>  create mode 100644 tests/tcg/riscv64/test-zvdota.S
> 
> -- 
> 2.56.0
> 
> 
> 

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