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From: <Conor.Dooley@microchip.com>
To: <tongtiangen@huawei.com>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <palmer@rivosinc.com>,
	<aou@eecs.berkeley.edu>, <Conor.Dooley@microchip.com>
Cc: <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<wangkefeng.wang@huawei.com>, <guohanjun@huawei.com>
Subject: Re: [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable
Date: Wed, 24 Aug 2022 16:49:12 +0000	[thread overview]
Message-ID: <207ef9da-34d3-b059-9bfd-871a0c6ddab2@microchip.com> (raw)
In-Reply-To: <4063da85-b110-4afd-2023-59d4da41c27f@huawei.com>

On 24/08/2022 07:31, Tong Tiangen wrote:
> Hi riscv maintainers, kindly ping...
> 
> Thanks,
> Tong.
> 
> 在 2022/8/15 11:20, Tong Tiangen 写道:

It's barely been more than a week, relax :)

checkpatch really does not like one of the macros you added. Please
consider whether this is valid:

ERROR: Macros with complex values should be enclosed in parentheses
#38: FILE: arch/riscv/include/asm/asm-extable.h:61:
+#define _ASM_EXTABLE_KACCESS_ERR_ZERO(insn, fixup, err, zero)          \
+       __DEFINE_ASM_GPR_NUMS                                           \
+       __ASM_EXTABLE_RAW(#insn, #fixup,                                \
+                         __stringify(EX_TYPE_KACCESS_ERR_ZERO),        \
+                         "("                                           \
+                           EX_DATA_REG(ERR, err) " | "                 \
+                           EX_DATA_REG(ZERO, zero)                     \
+                         ")")

Thanks,
Conor.

>> This patchset do some refactorings related to riscv's uaccess and extable,
>> mainly for the usage of __get/put_user_nocheck() which not distinguish user
>> access and kernel access.
>>
>> v1 -> v2:
>>    According to Conor's suggestion, split into two logically independent
>>    patches.
>>
>> Tong Tiangen (2):
>>    riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck
>>    riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support
>>
>>   arch/riscv/include/asm/asm-extable.h |  12 ++
>>   arch/riscv/include/asm/uaccess.h     | 162 +++++++++++++--------------
>>   arch/riscv/mm/extable.c              |   1 +
>>   3 files changed, 94 insertions(+), 81 deletions(-)
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <tongtiangen@huawei.com>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <palmer@rivosinc.com>,
	<aou@eecs.berkeley.edu>, <Conor.Dooley@microchip.com>
Cc: <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<wangkefeng.wang@huawei.com>, <guohanjun@huawei.com>
Subject: Re: [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable
Date: Wed, 24 Aug 2022 16:49:12 +0000	[thread overview]
Message-ID: <207ef9da-34d3-b059-9bfd-871a0c6ddab2@microchip.com> (raw)
In-Reply-To: <4063da85-b110-4afd-2023-59d4da41c27f@huawei.com>

On 24/08/2022 07:31, Tong Tiangen wrote:
> Hi riscv maintainers, kindly ping...
> 
> Thanks,
> Tong.
> 
> 在 2022/8/15 11:20, Tong Tiangen 写道:

It's barely been more than a week, relax :)

checkpatch really does not like one of the macros you added. Please
consider whether this is valid:

ERROR: Macros with complex values should be enclosed in parentheses
#38: FILE: arch/riscv/include/asm/asm-extable.h:61:
+#define _ASM_EXTABLE_KACCESS_ERR_ZERO(insn, fixup, err, zero)          \
+       __DEFINE_ASM_GPR_NUMS                                           \
+       __ASM_EXTABLE_RAW(#insn, #fixup,                                \
+                         __stringify(EX_TYPE_KACCESS_ERR_ZERO),        \
+                         "("                                           \
+                           EX_DATA_REG(ERR, err) " | "                 \
+                           EX_DATA_REG(ZERO, zero)                     \
+                         ")")

Thanks,
Conor.

>> This patchset do some refactorings related to riscv's uaccess and extable,
>> mainly for the usage of __get/put_user_nocheck() which not distinguish user
>> access and kernel access.
>>
>> v1 -> v2:
>>    According to Conor's suggestion, split into two logically independent
>>    patches.
>>
>> Tong Tiangen (2):
>>    riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck
>>    riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support
>>
>>   arch/riscv/include/asm/asm-extable.h |  12 ++
>>   arch/riscv/include/asm/uaccess.h     | 162 +++++++++++++--------------
>>   arch/riscv/mm/extable.c              |   1 +
>>   3 files changed, 94 insertions(+), 81 deletions(-)
>>

  reply	other threads:[~2022-08-24 16:49 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15  3:20 [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable Tong Tiangen
2022-08-15  3:20 ` Tong Tiangen
2022-08-15  3:20 ` [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck Tong Tiangen
2022-08-15  3:20   ` Tong Tiangen
2022-08-25 10:56   ` Andrew Jones
2022-08-25 10:56     ` Andrew Jones
2022-08-26  6:33     ` Tong Tiangen
2022-08-26  6:33       ` Tong Tiangen
2022-08-26  7:43       ` Andrew Jones
2022-08-26  7:43         ` Andrew Jones
2022-08-27 10:39         ` Tong Tiangen
2022-08-27 10:39           ` Tong Tiangen
2022-08-26  9:30   ` Arnd Bergmann
2022-08-26  9:30     ` Arnd Bergmann
2022-08-27 10:43     ` Tong Tiangen
2022-08-27 10:43       ` Tong Tiangen
2022-08-27 12:49       ` Arnd Bergmann
2022-08-27 12:49         ` Arnd Bergmann
2022-08-29  1:26         ` Tong Tiangen
2022-08-29  1:26           ` Tong Tiangen
2022-08-15  3:20 ` [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support Tong Tiangen
2022-08-15  3:20   ` Tong Tiangen
2022-08-25 11:06   ` Andrew Jones
2022-08-25 11:06     ` Andrew Jones
2022-08-26  6:44     ` Tong Tiangen
2022-08-26  6:44       ` Tong Tiangen
2022-08-26  8:16       ` Andrew Jones
2022-08-26  8:16         ` Andrew Jones
2022-08-27 10:39         ` Tong Tiangen
2022-08-27 10:39           ` Tong Tiangen
2022-09-21 20:25           ` Palmer Dabbelt
2022-09-21 20:25             ` Palmer Dabbelt
2022-10-21 12:23             ` Tong Tiangen
2022-10-21 12:23               ` Tong Tiangen
2022-08-24  6:31 ` [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable Tong Tiangen
2022-08-24  6:31   ` Tong Tiangen
2022-08-24 16:49   ` Conor.Dooley [this message]
2022-08-24 16:49     ` Conor.Dooley
2022-08-25  3:04     ` Tong Tiangen
2022-08-25  3:04       ` Tong Tiangen

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