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From: Kenneth Graunke <kenneth@whitecape.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
Date: Thu, 04 Jan 2018 15:39:23 -0800	[thread overview]
Message-ID: <2209082.bMokASrcsY@kirito> (raw)
In-Reply-To: <151510098613.6838.1512668093211672119@mail.alporthouse.com>


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On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-01-04 19:38:05)
> > Geminilake requires the 3D driver to select whether barriers are
> > intended for compute shaders, or tessellation control shaders, by
> > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > switching pipelines.  Failure to do this properly can result in GPU
> > hangs.
> > 
> > Unfortunately, this means it needs to switch mid-batch, so only
> > userspace can properly set it.  To facilitate this, the kernel needs
> > to whitelist the register.
> > 
> > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> > Cc: stable@vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h        | 2 ++
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> >  2 files changed, 7 insertions(+)
> > 
> > Hello,
> > 
> > We unfortunately need to whitelist an extra register for GPU hang fix
> > on Geminilake.  Here's the corresponding Mesa patch:
> 
> Thankfully it appears to be context saved. Has a w/a name been assigned
> for this?
> -Chris

There doesn't appear to be one.  The workaround page lists it, but there
is no name.  The register description has a note saying that you need to
set this, but doesn't call it out as a workaround.

That's why I put a generic comment, rather than the name.

--Ken

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WARNING: multiple messages have this Message-ID (diff)
From: Kenneth Graunke <kenneth@whitecape.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
Date: Thu, 04 Jan 2018 15:39:23 -0800	[thread overview]
Message-ID: <2209082.bMokASrcsY@kirito> (raw)
In-Reply-To: <151510098613.6838.1512668093211672119@mail.alporthouse.com>

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On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-01-04 19:38:05)
> > Geminilake requires the 3D driver to select whether barriers are
> > intended for compute shaders, or tessellation control shaders, by
> > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > switching pipelines.  Failure to do this properly can result in GPU
> > hangs.
> > 
> > Unfortunately, this means it needs to switch mid-batch, so only
> > userspace can properly set it.  To facilitate this, the kernel needs
> > to whitelist the register.
> > 
> > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> > Cc: stable@vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h        | 2 ++
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> >  2 files changed, 7 insertions(+)
> > 
> > Hello,
> > 
> > We unfortunately need to whitelist an extra register for GPU hang fix
> > on Geminilake.  Here's the corresponding Mesa patch:
> 
> Thankfully it appears to be context saved. Has a w/a name been assigned
> for this?
> -Chris

There doesn't appear to be one.  The workaround page lists it, but there
is no name.  The register description has a note saying that you need to
set this, but doesn't call it out as a workaround.

That's why I put a generic comment, rather than the name.

--Ken

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  reply	other threads:[~2018-01-04 23:39 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-04 19:38 [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake Kenneth Graunke
2018-01-04 19:38 ` Kenneth Graunke
2018-01-04 20:24 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-01-04 21:23 ` [Intel-gfx] [PATCH] " Chris Wilson
2018-01-04 21:23   ` Chris Wilson
2018-01-04 23:39   ` Kenneth Graunke [this message]
2018-01-04 23:39     ` Kenneth Graunke
2018-01-05  0:41     ` Rodrigo Vivi
2018-01-05  0:41       ` [Intel-gfx] " Rodrigo Vivi
2018-01-05  6:06       ` Kenneth Graunke
2018-01-05  6:06         ` [Intel-gfx] " Kenneth Graunke
2018-01-05  6:53         ` Vivi, Rodrigo
2019-02-28 18:17         ` [Intel-gfx] " Chris Wilson
2018-01-04 21:53 ` ✗ Fi.CI.IGT: warning for " Patchwork

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