* [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-04 19:38 ` Kenneth Graunke 0 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-04 19:38 UTC (permalink / raw) To: intel-gfx; +Cc: Kenneth Graunke, stable Geminilake requires the 3D driver to select whether barriers are intended for compute shaders, or tessellation control shaders, by whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when switching pipelines. Failure to do this properly can result in GPU hangs. Unfortunately, this means it needs to switch mid-batch, so only userspace can properly set it. To facilitate this, the kernel needs to whitelist the register. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: stable@vger.kernel.org --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ 2 files changed, 7 insertions(+) Hello, We unfortunately need to whitelist an extra register for GPU hang fix on Geminilake. Here's the corresponding Mesa patch: https://patchwork.freedesktop.org/patch/196047/ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 966e4df9700e..505c605eff98 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7079,6 +7079,8 @@ enum { #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) #define DISABLE_PIXEL_MASK_CAMMING (1<<14) +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) + #define GEN7_L3SQCREG1 _MMIO(0xB010) #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index ebdcbcbacb3c..d64a9f907550 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; + /* Userspace needs to toggle "Barrier Mode" to avoid GPU hangs */ + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1); + if (ret) + return ret; + /* WaToEnableHwFixForPushConstHWBug:glk */ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); -- 2.15.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-04 19:38 ` Kenneth Graunke 0 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-04 19:38 UTC (permalink / raw) To: intel-gfx; +Cc: Kenneth Graunke, stable Geminilake requires the 3D driver to select whether barriers are intended for compute shaders, or tessellation control shaders, by whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when switching pipelines. Failure to do this properly can result in GPU hangs. Unfortunately, this means it needs to switch mid-batch, so only userspace can properly set it. To facilitate this, the kernel needs to whitelist the register. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: stable@vger.kernel.org --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ 2 files changed, 7 insertions(+) Hello, We unfortunately need to whitelist an extra register for GPU hang fix on Geminilake. Here's the corresponding Mesa patch: https://patchwork.freedesktop.org/patch/196047/ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 966e4df9700e..505c605eff98 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7079,6 +7079,8 @@ enum { #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) #define DISABLE_PIXEL_MASK_CAMMING (1<<14) +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) + #define GEN7_L3SQCREG1 _MMIO(0xB010) #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index ebdcbcbacb3c..d64a9f907550 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; + /* Userspace needs to toggle "Barrier Mode" to avoid GPU hangs */ + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1); + if (ret) + return ret; + /* WaToEnableHwFixForPushConstHWBug:glk */ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); -- 2.15.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-04 19:38 ` Kenneth Graunke (?) @ 2018-01-04 20:24 ` Patchwork -1 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2018-01-04 20:24 UTC (permalink / raw) To: Kenneth Graunke; +Cc: intel-gfx == Series Details == Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. URL : https://patchwork.freedesktop.org/series/36039/ State : success == Summary == Series 36039v1 drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. https://patchwork.freedesktop.org/api/1.0/series/36039/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:427s fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:424s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:369s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:477s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:275s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:484s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:451s fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:263s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:515s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:390s fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:402s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:408s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:454s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:415s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:465s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:497s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:457s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:497s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:570s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:435s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:507s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:522s fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:493s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:473s fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:427s fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:398s Blacklisted hosts: fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:562s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:596s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:463s 1902822a64e3140b0d89ee7042ec4aa89c81afa6 drm-tip: 2018y-01m-04d-19h-38m-27s UTC integration manifest abab48d0ad38 drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7609/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-04 19:38 ` Kenneth Graunke @ 2018-01-04 21:23 ` Chris Wilson -1 siblings, 0 replies; 14+ messages in thread From: Chris Wilson @ 2018-01-04 21:23 UTC (permalink / raw) To: intel-gfx; +Cc: Kenneth Graunke, stable Quoting Kenneth Graunke (2018-01-04 19:38:05) > Geminilake requires the 3D driver to select whether barriers are > intended for compute shaders, or tessellation control shaders, by > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > switching pipelines. Failure to do this properly can result in GPU > hangs. > > Unfortunately, this means it needs to switch mid-batch, so only > userspace can properly set it. To facilitate this, the kernel needs > to whitelist the register. > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > 2 files changed, 7 insertions(+) > > Hello, > > We unfortunately need to whitelist an extra register for GPU hang fix > on Geminilake. Here's the corresponding Mesa patch: Thankfully it appears to be context saved. Has a w/a name been assigned for this? -Chris ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-04 21:23 ` Chris Wilson 0 siblings, 0 replies; 14+ messages in thread From: Chris Wilson @ 2018-01-04 21:23 UTC (permalink / raw) To: Kenneth Graunke, intel-gfx; +Cc: Kenneth Graunke, stable Quoting Kenneth Graunke (2018-01-04 19:38:05) > Geminilake requires the 3D driver to select whether barriers are > intended for compute shaders, or tessellation control shaders, by > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > switching pipelines. Failure to do this properly can result in GPU > hangs. > > Unfortunately, this means it needs to switch mid-batch, so only > userspace can properly set it. To facilitate this, the kernel needs > to whitelist the register. > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > 2 files changed, 7 insertions(+) > > Hello, > > We unfortunately need to whitelist an extra register for GPU hang fix > on Geminilake. Here's the corresponding Mesa patch: Thankfully it appears to be context saved. Has a w/a name been assigned for this? -Chris ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-04 21:23 ` Chris Wilson @ 2018-01-04 23:39 ` Kenneth Graunke -1 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-04 23:39 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, stable [-- Attachment #1.1: Type: text/plain, Size: 1339 bytes --] On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > Geminilake requires the 3D driver to select whether barriers are > > intended for compute shaders, or tessellation control shaders, by > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > switching pipelines. Failure to do this properly can result in GPU > > hangs. > > > > Unfortunately, this means it needs to switch mid-batch, so only > > userspace can properly set it. To facilitate this, the kernel needs > > to whitelist the register. > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > Cc: stable@vger.kernel.org > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > 2 files changed, 7 insertions(+) > > > > Hello, > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > on Geminilake. Here's the corresponding Mesa patch: > > Thankfully it appears to be context saved. Has a w/a name been assigned > for this? > -Chris There doesn't appear to be one. The workaround page lists it, but there is no name. The register description has a note saying that you need to set this, but doesn't call it out as a workaround. That's why I put a generic comment, rather than the name. --Ken [-- Attachment #1.2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 833 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-04 23:39 ` Kenneth Graunke 0 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-04 23:39 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, stable [-- Attachment #1: Type: text/plain, Size: 1339 bytes --] On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > Geminilake requires the 3D driver to select whether barriers are > > intended for compute shaders, or tessellation control shaders, by > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > switching pipelines. Failure to do this properly can result in GPU > > hangs. > > > > Unfortunately, this means it needs to switch mid-batch, so only > > userspace can properly set it. To facilitate this, the kernel needs > > to whitelist the register. > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > Cc: stable@vger.kernel.org > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > 2 files changed, 7 insertions(+) > > > > Hello, > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > on Geminilake. Here's the corresponding Mesa patch: > > Thankfully it appears to be context saved. Has a w/a name been assigned > for this? > -Chris There doesn't appear to be one. The workaround page lists it, but there is no name. The register description has a note saying that you need to set this, but doesn't call it out as a workaround. That's why I put a generic comment, rather than the name. --Ken [-- Attachment #2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-04 23:39 ` [Intel-gfx] " Kenneth Graunke @ 2018-01-05 0:41 ` Rodrigo Vivi -1 siblings, 0 replies; 14+ messages in thread From: Rodrigo Vivi @ 2018-01-05 0:41 UTC (permalink / raw) To: Kenneth Graunke; +Cc: intel-gfx, stable On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > > Geminilake requires the 3D driver to select whether barriers are > > > intended for compute shaders, or tessellation control shaders, by > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > > switching pipelines. Failure to do this properly can result in GPU > > > hangs. > > > > > > Unfortunately, this means it needs to switch mid-batch, so only > > > userspace can properly set it. To facilitate this, the kernel needs > > > to whitelist the register. > > > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > > Cc: stable@vger.kernel.org > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > > 2 files changed, 7 insertions(+) > > > > > > Hello, > > > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > > on Geminilake. Here's the corresponding Mesa patch: > > > > Thankfully it appears to be context saved. Has a w/a name been assigned > > for this? > > -Chris > > There doesn't appear to be one. The workaround page lists it, but there > is no name. The register description has a note saying that you need to > set this, but doesn't call it out as a workaround. It mentions only BXT:ALL, but not mention to GLK. Should we add to both then? > > That's why I put a generic comment, rather than the name. On Display side we started using the row name for this case, to help easily finding this later. ex: "Display WA #0390: skl,kbl" The number for this apparently is: WA #0862 Maybe we could use this one to start /* GT WA #0862: bxt,glk */ GT? GEM? Unnamed WA #0862? Thanks, Rodrigo. > > --Ken > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-05 0:41 ` Rodrigo Vivi 0 siblings, 0 replies; 14+ messages in thread From: Rodrigo Vivi @ 2018-01-05 0:41 UTC (permalink / raw) To: Kenneth Graunke; +Cc: Chris Wilson, intel-gfx, stable On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > > Geminilake requires the 3D driver to select whether barriers are > > > intended for compute shaders, or tessellation control shaders, by > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > > switching pipelines. Failure to do this properly can result in GPU > > > hangs. > > > > > > Unfortunately, this means it needs to switch mid-batch, so only > > > userspace can properly set it. To facilitate this, the kernel needs > > > to whitelist the register. > > > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > > Cc: stable@vger.kernel.org > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > > 2 files changed, 7 insertions(+) > > > > > > Hello, > > > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > > on Geminilake. Here's the corresponding Mesa patch: > > > > Thankfully it appears to be context saved. Has a w/a name been assigned > > for this? > > -Chris > > There doesn't appear to be one. The workaround page lists it, but there > is no name. The register description has a note saying that you need to > set this, but doesn't call it out as a workaround. It mentions only BXT:ALL, but not mention to GLK. Should we add to both then? > > That's why I put a generic comment, rather than the name. On Display side we started using the row name for this case, to help easily finding this later. ex: "Display WA #0390: skl,kbl" The number for this apparently is: WA #0862 Maybe we could use this one to start /* GT WA #0862: bxt,glk */ GT? GEM? Unnamed WA #0862? Thanks, Rodrigo. > > --Ken > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-05 0:41 ` [Intel-gfx] " Rodrigo Vivi @ 2018-01-05 6:06 ` Kenneth Graunke -1 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-05 6:06 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, stable [-- Attachment #1.1: Type: text/plain, Size: 2784 bytes --] On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote: > On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: > > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > > > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > > > Geminilake requires the 3D driver to select whether barriers are > > > > intended for compute shaders, or tessellation control shaders, by > > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > > > switching pipelines. Failure to do this properly can result in GPU > > > > hangs. > > > > > > > > Unfortunately, this means it needs to switch mid-batch, so only > > > > userspace can properly set it. To facilitate this, the kernel needs > > > > to whitelist the register. > > > > > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > > > Cc: stable@vger.kernel.org > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > > > 2 files changed, 7 insertions(+) > > > > > > > > Hello, > > > > > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > > > on Geminilake. Here's the corresponding Mesa patch: > > > > > > Thankfully it appears to be context saved. Has a w/a name been assigned > > > for this? > > > -Chris > > > > There doesn't appear to be one. The workaround page lists it, but there > > is no name. The register description has a note saying that you need to > > set this, but doesn't call it out as a workaround. > > It mentions only BXT:ALL, but not mention to GLK. > > Should we add to both then? Well, that's irritating. On the workarounds page, it does indeed say "BXT" with no mention of GLK. But the workaround text says to set "SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)." Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7 is "Barrier Mode" on [GLK] only, with no mention of BXT. It's marked reserved PBC on [SKL+, not GLK, not KBL]. On KBL it's something else. I believe Mark saw hangs in tessellation control shader hangs on Geminilake only, and never saw this issue on Broxton. So, my guess is that the workaround really is new on Geminilake, and the BXT tag on the workarounds page is incorrect. (Mark, does that sound right to you?) > > That's why I put a generic comment, rather than the name. > > On Display side we started using the row name for this case, to help > easily finding this later. > > ex: "Display WA #0390: skl,kbl" > > The number for this apparently is: > WA #0862 > > Maybe we could use this one to start > /* GT WA #0862: bxt,glk */ > > GT? GEM? > Unnamed WA #0862? Including #0862 seems like a good idea. I'm happy to change the comment to whatever you'd prefer. --Ken [-- Attachment #1.2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 833 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. @ 2018-01-05 6:06 ` Kenneth Graunke 0 siblings, 0 replies; 14+ messages in thread From: Kenneth Graunke @ 2018-01-05 6:06 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Chris Wilson, intel-gfx, stable, mark.a.janes [-- Attachment #1: Type: text/plain, Size: 2784 bytes --] On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote: > On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: > > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > > > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > > > Geminilake requires the 3D driver to select whether barriers are > > > > intended for compute shaders, or tessellation control shaders, by > > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > > > switching pipelines. Failure to do this properly can result in GPU > > > > hangs. > > > > > > > > Unfortunately, this means it needs to switch mid-batch, so only > > > > userspace can properly set it. To facilitate this, the kernel needs > > > > to whitelist the register. > > > > > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > > > Cc: stable@vger.kernel.org > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > > > 2 files changed, 7 insertions(+) > > > > > > > > Hello, > > > > > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > > > on Geminilake. Here's the corresponding Mesa patch: > > > > > > Thankfully it appears to be context saved. Has a w/a name been assigned > > > for this? > > > -Chris > > > > There doesn't appear to be one. The workaround page lists it, but there > > is no name. The register description has a note saying that you need to > > set this, but doesn't call it out as a workaround. > > It mentions only BXT:ALL, but not mention to GLK. > > Should we add to both then? Well, that's irritating. On the workarounds page, it does indeed say "BXT" with no mention of GLK. But the workaround text says to set "SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)." Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7 is "Barrier Mode" on [GLK] only, with no mention of BXT. It's marked reserved PBC on [SKL+, not GLK, not KBL]. On KBL it's something else. I believe Mark saw hangs in tessellation control shader hangs on Geminilake only, and never saw this issue on Broxton. So, my guess is that the workaround really is new on Geminilake, and the BXT tag on the workarounds page is incorrect. (Mark, does that sound right to you?) > > That's why I put a generic comment, rather than the name. > > On Display side we started using the row name for this case, to help > easily finding this later. > > ex: "Display WA #0390: skl,kbl" > > The number for this apparently is: > WA #0862 > > Maybe we could use this one to start > /* GT WA #0862: bxt,glk */ > > GT? GEM? > Unnamed WA #0862? Including #0862 seems like a good idea. I'm happy to change the comment to whatever you'd prefer. --Ken [-- Attachment #2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-05 6:06 ` [Intel-gfx] " Kenneth Graunke (?) @ 2018-01-05 6:53 ` Vivi, Rodrigo -1 siblings, 0 replies; 14+ messages in thread From: Vivi, Rodrigo @ 2018-01-05 6:53 UTC (permalink / raw) To: Kenneth Graunke; +Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org [-- Attachment #1.1: Type: text/plain, Size: 3170 bytes --] On Jan 4, 2018, at 10:07 PM, Kenneth Graunke <kenneth@whitecape.org<mailto:kenneth@whitecape.org>> wrote: On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote: On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: Quoting Kenneth Graunke (2018-01-04 19:38:05) Geminilake requires the 3D driver to select whether barriers are intended for compute shaders, or tessellation control shaders, by whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when switching pipelines. Failure to do this properly can result in GPU hangs. Unfortunately, this means it needs to switch mid-batch, so only userspace can properly set it. To facilitate this, the kernel needs to whitelist the register. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org<mailto:kenneth@whitecape.org>> Cc: stable@vger.kernel.org<mailto:stable@vger.kernel.org> --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ 2 files changed, 7 insertions(+) Hello, We unfortunately need to whitelist an extra register for GPU hang fix on Geminilake. Here's the corresponding Mesa patch: Thankfully it appears to be context saved. Has a w/a name been assigned for this? -Chris There doesn't appear to be one. The workaround page lists it, but there is no name. The register description has a note saying that you need to set this, but doesn't call it out as a workaround. It mentions only BXT:ALL, but not mention to GLK. Should we add to both then? Well, that's irritating. Indeed. As always :) On the workarounds page, it does indeed say "BXT" with no mention of GLK. But the workaround text says to set "SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)." Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7 is "Barrier Mode" on [GLK] only, with no mention of BXT. It's marked reserved PBC on [SKL+, not GLK, not KBL]. On KBL it's something else. I have no ways to check this bit right now, But your explanation makes sense so I agree with you... Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com<mailto:rodrigo.vivi@intel.com>> I believe Mark saw hangs in tessellation control shader hangs on Geminilake only, and never saw this issue on Broxton. So, my guess is that the workaround really is new on Geminilake, and the BXT tag on the workarounds page is incorrect. (Mark, does that sound right to you?) Probably worth a mention on comment or commit msg?! That's why I put a generic comment, rather than the name. On Display side we started using the row name for this case, to help easily finding this later. ex: "Display WA #0390: skl,kbl" The number for this apparently is: WA #0862 Maybe we could use this one to start /* GT WA #0862: bxt,glk */ GT? GEM? Unnamed WA #0862? Including #0862 seems like a good idea. I'm happy to change the comment to whatever you'd prefer. Leave your comment and add WA #0862... If later we define a standardized style we come back and change this. Thanks Rodrigo --Ken [-- Attachment #1.2: Type: text/html, Size: 10544 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-05 6:06 ` [Intel-gfx] " Kenneth Graunke (?) (?) @ 2019-02-28 18:17 ` Chris Wilson -1 siblings, 0 replies; 14+ messages in thread From: Chris Wilson @ 2019-02-28 18:17 UTC (permalink / raw) To: Kenneth Graunke, Rodrigo Vivi; +Cc: intel-gfx, stable, mark.a.janes Quoting Kenneth Graunke (2018-01-05 06:06:34) > On Thursday, January 4, 2018 4:41:35 PM PST Rodrigo Vivi wrote: > > On Thu, Jan 04, 2018 at 11:39:23PM +0000, Kenneth Graunke wrote: > > > On Thursday, January 4, 2018 1:23:06 PM PST Chris Wilson wrote: > > > > Quoting Kenneth Graunke (2018-01-04 19:38:05) > > > > > Geminilake requires the 3D driver to select whether barriers are > > > > > intended for compute shaders, or tessellation control shaders, by > > > > > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > > > > > switching pipelines. Failure to do this properly can result in GPU > > > > > hangs. > > > > > > > > > > Unfortunately, this means it needs to switch mid-batch, so only > > > > > userspace can properly set it. To facilitate this, the kernel needs > > > > > to whitelist the register. > > > > > > > > > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > > > > Cc: stable@vger.kernel.org > > > > > --- > > > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > > > > > 2 files changed, 7 insertions(+) > > > > > > > > > > Hello, > > > > > > > > > > We unfortunately need to whitelist an extra register for GPU hang fix > > > > > on Geminilake. Here's the corresponding Mesa patch: > > > > > > > > Thankfully it appears to be context saved. Has a w/a name been assigned > > > > for this? > > > > -Chris > > > > > > There doesn't appear to be one. The workaround page lists it, but there > > > is no name. The register description has a note saying that you need to > > > set this, but doesn't call it out as a workaround. > > > > It mentions only BXT:ALL, but not mention to GLK. > > > > Should we add to both then? > > Well, that's irritating. On the workarounds page, it does indeed say > "BXT" with no mention of GLK. But the workaround text says to set > "SLICE_COMMON_CHICKEN_ECO1 Barrier Mode [...] (bit 7 of MMIO 0x731C)." > > Looking at the register definition for SLICE_COMMON_ECO_CHICKEN1, bit 7 > is "Barrier Mode" on [GLK] only, with no mention of BXT. It's marked > reserved PBC on [SKL+, not GLK, not KBL]. On KBL it's something else. > > I believe Mark saw hangs in tessellation control shader hangs on > Geminilake only, and never saw this issue on Broxton. So, my guess is > that the workaround really is new on Geminilake, and the BXT tag on the > workarounds page is incorrect. (Mark, does that sound right to you?) Hi, I'm back! This fails a selftest on glk as we can't even write to the register 0x731c, or at least can't read from the register. Did bspec ever get updated to include this register & wa? -Chris ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.IGT: warning for drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. 2018-01-04 19:38 ` Kenneth Graunke ` (2 preceding siblings ...) (?) @ 2018-01-04 21:53 ` Patchwork -1 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2018-01-04 21:53 UTC (permalink / raw) To: Kenneth Graunke; +Cc: intel-gfx == Series Details == Series: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. URL : https://patchwork.freedesktop.org/series/36039/ State : warning == Summary == Test kms_flip: Subgroup vblank-vs-modeset-suspend-interruptible: pass -> SKIP (shard-snb) Subgroup flip-vs-modeset-vs-hang-interruptible: dmesg-warn -> PASS (shard-snb) fdo#104311 Subgroup nonexisting-fb: pass -> SKIP (shard-hsw) Test gem_tiled_swapping: Subgroup non-threaded: incomplete -> PASS (shard-hsw) fdo#104218 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-indfb-draw-render: fail -> PASS (shard-snb) fdo#101623 Subgroup fbc-1p-primscrn-pri-shrfb-draw-render: fail -> PASS (shard-snb) fdo#103167 +1 Test kms_cursor_legacy: Subgroup flip-vs-cursor-crc-atomic: pass -> SKIP (shard-hsw) Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-left-edge: pass -> SKIP (shard-hsw) Subgroup pipe-c-128x128-bottom-edge: pass -> SKIP (shard-hsw) Test kms_cursor_crc: Subgroup cursor-256x256-suspend: incomplete -> PASS (shard-hsw) fdo#103375 fdo#104311 https://bugs.freedesktop.org/show_bug.cgi?id=104311 fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 shard-hsw total:2636 pass:1486 dwarn:1 dfail:0 fail:10 skip:1139 time:8647s shard-snb total:2713 pass:1309 dwarn:1 dfail:0 fail:11 skip:1392 time:7744s Blacklisted hosts: shard-apl total:2713 pass:1686 dwarn:1 dfail:0 fail:25 skip:1001 time:13296s shard-kbl total:2713 pass:1804 dwarn:1 dfail:0 fail:30 skip:878 time:10383s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7609/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-02-28 18:17 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-01-04 19:38 [PATCH] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake Kenneth Graunke 2018-01-04 19:38 ` Kenneth Graunke 2018-01-04 20:24 ` ✓ Fi.CI.BAT: success for " Patchwork 2018-01-04 21:23 ` [Intel-gfx] [PATCH] " Chris Wilson 2018-01-04 21:23 ` Chris Wilson 2018-01-04 23:39 ` Kenneth Graunke 2018-01-04 23:39 ` [Intel-gfx] " Kenneth Graunke 2018-01-05 0:41 ` Rodrigo Vivi 2018-01-05 0:41 ` [Intel-gfx] " Rodrigo Vivi 2018-01-05 6:06 ` Kenneth Graunke 2018-01-05 6:06 ` [Intel-gfx] " Kenneth Graunke 2018-01-05 6:53 ` Vivi, Rodrigo 2019-02-28 18:17 ` [Intel-gfx] " Chris Wilson 2018-01-04 21:53 ` ✗ Fi.CI.IGT: warning for " Patchwork
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