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From: "Rémi Denis-Courmont" <remi@remlab.net>
To: Mark Rutland <mark.rutland@arm.com>
Cc: catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] arm64: clean up trampoline vector loads
Date: Mon, 23 Mar 2020 14:08:53 +0200	[thread overview]
Message-ID: <2345780.q8flsOIESp@basile.remlab.net> (raw)
In-Reply-To: <20200323120700.GB2597@C02TD0UTHF1T.local>

Le maanantaina 23. maaliskuuta 2020, 14.07.00 EET Mark Rutland a écrit :
> On Thu, Mar 19, 2020 at 11:14:05AM +0200, Rémi Denis-Courmont wrote:
> > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > 
> > This switches from custom instruction patterns to the regular large
> > memory model sequence with ADRP and LDR. In doing so, the ADD
> > instruction can be eliminated in the SDEI handler, and the code no
> > longer assumes that the trampoline vectors and the vectors address both
> > start on a page boundary.
> > 
> > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > ---
> > 
> >  arch/arm64/kernel/entry.S | 9 ++++-----
> >  1 file changed, 4 insertions(+), 5 deletions(-)
> > 
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index e5d4e30ee242..24f828739696 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++ b/arch/arm64/kernel/entry.S
> > @@ -805,9 +805,9 @@ alternative_else_nop_endif
> > 
> >  2:
> >  	tramp_map_kernel	x30
> >  
> >  #ifdef CONFIG_RANDOMIZE_BASE
> > 
> > -	adr	x30, tramp_vectors + PAGE_SIZE
> > +	adrp	x30, tramp_vectors + PAGE_SIZE
> > 
> >  alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
> > 
> > -	ldr	x30, [x30]
> > +	ldr	x30, [x30, #:lo12:__entry_tramp_data_start]
> 
> I think this is busted for !4K kernels once we reduce the alignment of
> __entry_tramp_data_start.
> 
> The ADRP gives us a 64K aligned address (with bits 15:0 clear). The lo12
> relocation gives us bits 11:0, so we haven't accounted for bits 15:12.

IMU, ADRP gives a 4K aligned value, regardless of MMU (TCR) settings.

I rather suspect that the problem is with my C code diff assuming that 
PAGE_MASK is 4095.

-- 
Rémi Denis-Courmont
http://www.remlab.net/




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WARNING: multiple messages have this Message-ID (diff)
From: "Rémi Denis-Courmont" <remi@remlab.net>
To: Mark Rutland <mark.rutland@arm.com>
Cc: catalin.marinas@arm.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org, james.morse@arm.com,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] arm64: clean up trampoline vector loads
Date: Mon, 23 Mar 2020 14:08:53 +0200	[thread overview]
Message-ID: <2345780.q8flsOIESp@basile.remlab.net> (raw)
In-Reply-To: <20200323120700.GB2597@C02TD0UTHF1T.local>

Le maanantaina 23. maaliskuuta 2020, 14.07.00 EET Mark Rutland a écrit :
> On Thu, Mar 19, 2020 at 11:14:05AM +0200, Rémi Denis-Courmont wrote:
> > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > 
> > This switches from custom instruction patterns to the regular large
> > memory model sequence with ADRP and LDR. In doing so, the ADD
> > instruction can be eliminated in the SDEI handler, and the code no
> > longer assumes that the trampoline vectors and the vectors address both
> > start on a page boundary.
> > 
> > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > ---
> > 
> >  arch/arm64/kernel/entry.S | 9 ++++-----
> >  1 file changed, 4 insertions(+), 5 deletions(-)
> > 
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index e5d4e30ee242..24f828739696 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++ b/arch/arm64/kernel/entry.S
> > @@ -805,9 +805,9 @@ alternative_else_nop_endif
> > 
> >  2:
> >  	tramp_map_kernel	x30
> >  
> >  #ifdef CONFIG_RANDOMIZE_BASE
> > 
> > -	adr	x30, tramp_vectors + PAGE_SIZE
> > +	adrp	x30, tramp_vectors + PAGE_SIZE
> > 
> >  alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
> > 
> > -	ldr	x30, [x30]
> > +	ldr	x30, [x30, #:lo12:__entry_tramp_data_start]
> 
> I think this is busted for !4K kernels once we reduce the alignment of
> __entry_tramp_data_start.
> 
> The ADRP gives us a 64K aligned address (with bits 15:0 clear). The lo12
> relocation gives us bits 11:0, so we haven't accounted for bits 15:12.

IMU, ADRP gives a 4K aligned value, regardless of MMU (TCR) settings.

I rather suspect that the problem is with my C code diff assuming that 
PAGE_MASK is 4095.

-- 
Rémi Denis-Courmont
http://www.remlab.net/




  reply	other threads:[~2020-03-23 12:09 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19  9:12 [PATCHv3 0/3] clean up KPTI / SDEI trampoline data alignment Rémi Denis-Courmont
2020-03-19  9:12 ` Rémi Denis-Courmont
2020-03-19  9:14 ` [PATCH 1/3] arm64: clean up trampoline vector loads Rémi Denis-Courmont
2020-03-19  9:14   ` Rémi Denis-Courmont
2020-03-23 12:07   ` Mark Rutland
2020-03-23 12:07     ` Mark Rutland
2020-03-23 12:08     ` Rémi Denis-Courmont [this message]
2020-03-23 12:08       ` Rémi Denis-Courmont
2020-03-23 12:14       ` Mark Rutland
2020-03-23 12:14         ` Mark Rutland
2020-03-23 19:04         ` Catalin Marinas
2020-03-23 19:04           ` Catalin Marinas
2020-03-23 20:42           ` Rémi Denis-Courmont
2020-03-23 20:42             ` Rémi Denis-Courmont
2020-03-24 10:37             ` Catalin Marinas
2020-03-24 10:37               ` Catalin Marinas
2020-03-24 10:52             ` Mark Rutland
2020-03-24 10:52               ` Mark Rutland
2020-03-24 11:23               ` Catalin Marinas
2020-03-24 11:23                 ` Catalin Marinas
2020-03-19  9:14 ` [PATCH 2/3] arm64/sdei: gather trampolines' .rodata Rémi Denis-Courmont
2020-03-19  9:14   ` Rémi Denis-Courmont
2020-03-19  9:14 ` [PATCH 3/3] arm64: reduce trampoline data alignment Rémi Denis-Courmont
2020-03-19  9:14   ` Rémi Denis-Courmont
2020-03-21 13:40   ` Catalin Marinas
2020-03-21 13:41     ` Catalin Marinas
2020-03-23 11:58     ` Mark Rutland
2020-03-23 11:58       ` Mark Rutland
2020-03-19 18:37 ` [PATCHv3 0/3] clean up KPTI / SDEI " Will Deacon
2020-03-19 18:37   ` Will Deacon
2020-03-20 16:54 ` Catalin Marinas
2020-03-20 16:54   ` Catalin Marinas
  -- strict thread matches above, loose matches on Subject: below --
2020-03-16 12:40 [PATCH 1/3] arm64: clean up trampoline vector loads Rémi Denis-Courmont
2020-03-16 12:40 ` Rémi Denis-Courmont
2020-03-17 22:30 ` Will Deacon
2020-03-17 22:30   ` Will Deacon
2020-03-18 17:57 ` Catalin Marinas
2020-03-18 17:57   ` Catalin Marinas
2020-03-18 18:06   ` Catalin Marinas
2020-03-18 18:06     ` Catalin Marinas
2020-03-18 18:29     ` Rémi Denis-Courmont
2020-03-18 18:29       ` Rémi Denis-Courmont
2020-03-18 19:48       ` Remi Denis-Courmont
2020-03-18 19:48         ` Remi Denis-Courmont

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