From: Heiko Stübner <heiko@sntech.de>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH -next v18 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context
Date: Mon, 17 Apr 2023 17:55:03 +0200 [thread overview]
Message-ID: <2456518.jZfb76A358@diego> (raw)
In-Reply-To: <20230414155843.12963-8-andy.chiu@sifive.com>
Am Freitag, 14. April 2023, 17:58:30 CEST schrieb Andy Chiu:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch is used to detect the size of CPU vector registers and use
> riscv_v_vsize to save the size of all the vector registers. It assumes all
> harts has the same capabilities in a SMP system. If a core detects VLENB
> that is different from the boot core, then it warns and turns off V
> support for user space.
>
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: guoren@linux.alibaba.com, Jisheng Zhang <jszhang@kernel.org>,
Xianting Tian <xianting.tian@linux.alibaba.com>,
Liao Chang <liaochang1@huawei.com>,
Masahiro Yamada <masahiroy@kernel.org>,
vineetg@rivosinc.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
Vincent Chen <vincent.chen@sifive.com>,
Conor Dooley <conor.dooley@microchip.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
greentime.hu@sifive.com, Li Zhengyu <lizhengyu3@huawei.com>,
Andrew Jones <ajones@ventanamicro.com>,
Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH -next v18 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context
Date: Mon, 17 Apr 2023 17:55:03 +0200 [thread overview]
Message-ID: <2456518.jZfb76A358@diego> (raw)
In-Reply-To: <20230414155843.12963-8-andy.chiu@sifive.com>
Am Freitag, 14. April 2023, 17:58:30 CEST schrieb Andy Chiu:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch is used to detect the size of CPU vector registers and use
> riscv_v_vsize to save the size of all the vector registers. It assumes all
> harts has the same capabilities in a SMP system. If a core detects VLENB
> that is different from the boot core, then it warns and turns off V
> support for user space.
>
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
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WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: guoren@linux.alibaba.com, Jisheng Zhang <jszhang@kernel.org>,
Xianting Tian <xianting.tian@linux.alibaba.com>,
Liao Chang <liaochang1@huawei.com>,
Masahiro Yamada <masahiroy@kernel.org>,
vineetg@rivosinc.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
Vincent Chen <vincent.chen@sifive.com>,
Conor Dooley <conor.dooley@microchip.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
greentime.hu@sifive.com, Li Zhengyu <lizhengyu3@huawei.com>,
Andrew Jones <ajones@ventanamicro.com>,
Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH -next v18 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context
Date: Mon, 17 Apr 2023 17:55:03 +0200 [thread overview]
Message-ID: <2456518.jZfb76A358@diego> (raw)
In-Reply-To: <20230414155843.12963-8-andy.chiu@sifive.com>
Am Freitag, 14. April 2023, 17:58:30 CEST schrieb Andy Chiu:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch is used to detect the size of CPU vector registers and use
> riscv_v_vsize to save the size of all the vector registers. It assumes all
> harts has the same capabilities in a SMP system. If a core detects VLENB
> that is different from the boot core, then it warns and turns off V
> support for user space.
>
> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
next prev parent reply other threads:[~2023-04-17 15:55 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-14 15:58 [PATCH -next v18 00/20] riscv: Add vector ISA support Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 01/20] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 02/20] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 03/20] riscv: Add new csr defines related to vector extension Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 04/20] riscv: Clear vector regfile on bootup Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 05/20] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-17 15:52 ` Heiko Stübner
2023-04-17 15:52 ` Heiko Stübner
2023-04-17 15:52 ` Heiko Stübner
2023-04-14 15:58 ` [PATCH -next v18 06/20] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-17 15:55 ` Heiko Stübner
2023-04-17 15:55 ` Heiko Stübner
2023-04-17 15:55 ` Heiko Stübner
2023-04-14 15:58 ` [PATCH -next v18 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 16:47 ` Conor Dooley
2023-04-14 16:47 ` Conor Dooley
2023-04-14 16:47 ` Conor Dooley
2023-04-17 15:55 ` Heiko Stübner [this message]
2023-04-17 15:55 ` Heiko Stübner
2023-04-17 15:55 ` Heiko Stübner
2023-04-14 15:58 ` [PATCH -next v18 08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 09/20] riscv: Add task switch support for vector Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 10/20] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 16:40 ` Conor Dooley
2023-04-14 16:40 ` Conor Dooley
2023-04-14 16:40 ` Conor Dooley
2023-04-14 15:58 ` [PATCH -next v18 11/20] riscv: Add ptrace vector support Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 12/20] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 13/20] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 14/20] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 15/20] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 17/20] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 18/20] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 19/20] riscv: detect assembler support for .option arch Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` [PATCH -next v18 20/20] riscv: Enable Vector code to be built Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-14 15:58 ` Andy Chiu
2023-04-17 15:56 ` [PATCH -next v18 00/20] riscv: Add vector ISA support Ben Dooks
2023-04-17 15:56 ` Ben Dooks
2023-04-17 15:56 ` Ben Dooks
2023-04-17 16:26 ` Andy Chiu
2023-04-17 16:26 ` Andy Chiu
2023-04-17 16:26 ` Andy Chiu
2023-04-19 7:43 ` Björn Töpel
2023-04-19 7:43 ` Björn Töpel
2023-04-19 7:43 ` Björn Töpel
2023-04-19 14:54 ` Björn Töpel
2023-04-19 14:54 ` Björn Töpel
2023-04-19 14:54 ` Björn Töpel
2023-04-19 15:18 ` Palmer Dabbelt
2023-04-19 15:18 ` Palmer Dabbelt
2023-04-19 15:18 ` Palmer Dabbelt
2023-04-20 16:36 ` Andy Chiu
2023-04-20 16:36 ` Andy Chiu
2023-04-20 16:36 ` Andy Chiu
2023-04-26 14:27 ` Palmer Dabbelt
2023-04-26 14:27 ` Palmer Dabbelt
2023-04-26 14:27 ` Palmer Dabbelt
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